[0a18747] | 1 | /* |
---|
| 2 | * Cache Management Support Routines for the MC68040 |
---|
| 3 | * |
---|
| 4 | * $Id$ |
---|
| 5 | */ |
---|
| 6 | |
---|
| 7 | #include <rtems.h> |
---|
| 8 | #include "cache_.h" |
---|
| 9 | |
---|
| 10 | |
---|
| 11 | /* |
---|
| 12 | * CACHE MANAGER: The following functions are CPU-specific. |
---|
| 13 | * They provide the basic implementation for the rtems_* cache |
---|
| 14 | * management routines. If a given function has no meaning for the CPU, |
---|
| 15 | * it does nothing by default. |
---|
| 16 | * |
---|
| 17 | * FIXME: Some functions simply have not been implemented. |
---|
| 18 | */ |
---|
| 19 | |
---|
| 20 | #if defined(ppc603) /* And possibly others */ |
---|
| 21 | |
---|
| 22 | /* Helpful macros */ |
---|
| 23 | #define PPC_Get_HID0( _value ) \ |
---|
| 24 | do { \ |
---|
| 25 | _value = 0; /* to avoid warnings */ \ |
---|
| 26 | asm volatile( \ |
---|
| 27 | "mfspr %0, 0x3f0;" /* get HID0 */ \ |
---|
| 28 | "isync" \ |
---|
| 29 | : "=r" (_value) \ |
---|
| 30 | : "0" (_value) \ |
---|
| 31 | ); \ |
---|
| 32 | } while (0) |
---|
| 33 | |
---|
| 34 | #define PPC_Set_HID0( _value ) \ |
---|
| 35 | do { \ |
---|
| 36 | asm volatile( \ |
---|
| 37 | "isync;" \ |
---|
| 38 | "mtspr 0x3f0, %0;" /* load HID0 */ \ |
---|
| 39 | "isync" \ |
---|
| 40 | : "=r" (_value) \ |
---|
| 41 | : "0" (_value) \ |
---|
| 42 | ); \ |
---|
| 43 | } while (0) |
---|
| 44 | |
---|
[5e77d129] | 45 | void _CPU_cache_enable_data ( |
---|
[0a18747] | 46 | void ) |
---|
| 47 | { |
---|
| 48 | unsigned32 value; |
---|
| 49 | PPC_Get_HID0( value ); |
---|
| 50 | value |= 0x00004000; /* set DCE bit */ |
---|
| 51 | PPC_Set_HID0( value ); |
---|
| 52 | } |
---|
| 53 | |
---|
[5e77d129] | 54 | void _CPU_cache_disable_data ( |
---|
[0a18747] | 55 | void ) |
---|
| 56 | { |
---|
| 57 | unsigned32 value; |
---|
| 58 | PPC_Get_HID0( value ); |
---|
| 59 | value &= 0xFFFFBFFF; /* clear DCE bit */ |
---|
| 60 | PPC_Set_HID0( value ); |
---|
| 61 | } |
---|
| 62 | |
---|
[5e77d129] | 63 | void _CPU_cache_enable_inst ( |
---|
[0a18747] | 64 | void ) |
---|
| 65 | { |
---|
| 66 | unsigned32 value; |
---|
| 67 | PPC_Get_HID0( value ); |
---|
| 68 | value |= 0x00008000; /* Set ICE bit */ |
---|
| 69 | PPC_Set_HID0( value ); |
---|
| 70 | } |
---|
| 71 | |
---|
[5e77d129] | 72 | void _CPU_cache_disable_inst ( |
---|
[0a18747] | 73 | void ) |
---|
| 74 | { |
---|
| 75 | unsigned32 value; |
---|
| 76 | PPC_Get_HID0( value ); |
---|
| 77 | value &= 0xFFFF7FFF; /* Clear ICE bit */ |
---|
| 78 | PPC_Set_HID0( value ); |
---|
| 79 | } |
---|
| 80 | |
---|
| 81 | #elif ( defined(mpc860) || defined(mpc821) ) |
---|
| 82 | |
---|
| 83 | #define mtspr(_spr,_reg) \ |
---|
| 84 | __asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) ) |
---|
| 85 | #define isync \ |
---|
| 86 | __asm__ volatile ("isync\n"::) |
---|
| 87 | |
---|
[5e77d129] | 88 | void _CPU_cache_flush_1_data_line( |
---|
[0a18747] | 89 | const void * _address ) |
---|
| 90 | { |
---|
| 91 | register const void *__address = _address; |
---|
| 92 | asm volatile ( "dcbf 0,%0" :: "r" (__address) ); |
---|
| 93 | } |
---|
| 94 | |
---|
[5e77d129] | 95 | void _CPU_cache_invalidate_1_data_line( |
---|
[0a18747] | 96 | const void * _address ) |
---|
| 97 | { |
---|
| 98 | register const void *__address = _address; |
---|
| 99 | asm volatile ( "dcbi 0,%0" :: "r" (__address) ); |
---|
| 100 | } |
---|
| 101 | |
---|
[5e77d129] | 102 | void _CPU_cache_flush_entire_data ( void ) {} |
---|
| 103 | void _CPU_cache_invalidate_entire_data ( void ) {} |
---|
| 104 | void _CPU_cache_freeze_data ( void ) {} |
---|
| 105 | void _CPU_cache_unfreeze_data ( void ) {} |
---|
[0a18747] | 106 | |
---|
[5e77d129] | 107 | void _CPU_cache_enable_data ( void ) |
---|
[0a18747] | 108 | { |
---|
| 109 | unsigned32 r1; |
---|
| 110 | r1 = (0x2<<24); |
---|
| 111 | mtspr( 568, r1 ); |
---|
| 112 | isync; |
---|
| 113 | } |
---|
| 114 | |
---|
[5e77d129] | 115 | void _CPU_cache_disable_data ( void ) |
---|
[0a18747] | 116 | { |
---|
| 117 | unsigned32 r1; |
---|
| 118 | r1 = (0x4<<24); |
---|
| 119 | mtspr( 568, r1 ); |
---|
| 120 | isync; |
---|
| 121 | } |
---|
| 122 | |
---|
[5e77d129] | 123 | void _CPU_cache_invalidate_1_inst_line( |
---|
[0a18747] | 124 | const void * _address ) |
---|
| 125 | { |
---|
| 126 | register const void *__address = _address; |
---|
| 127 | asm volatile ( "icbi 0,%0" :: "r" (__address) ); |
---|
| 128 | } |
---|
| 129 | |
---|
[5e77d129] | 130 | void _CPU_cache_invalidate_entire_inst ( void ) {} |
---|
| 131 | void _CPU_cache_freeze_inst ( void ) {} |
---|
| 132 | void _CPU_cache_unfreeze_inst ( void ) {} |
---|
[0a18747] | 133 | |
---|
[5e77d129] | 134 | void _CPU_cache_enable_inst ( void ) |
---|
[0a18747] | 135 | { |
---|
| 136 | unsigned32 r1; |
---|
| 137 | r1 = (0x2<<24); |
---|
| 138 | mtspr( 560, r1 ); |
---|
| 139 | isync; |
---|
| 140 | } |
---|
| 141 | |
---|
[5e77d129] | 142 | void _CPU_cache_disable_inst ( void ) |
---|
[0a18747] | 143 | { |
---|
| 144 | unsigned32 r1; |
---|
| 145 | r1 = (0x4<<24); |
---|
| 146 | mtspr( 560, r1 ); |
---|
| 147 | isync; |
---|
| 148 | } |
---|
| 149 | #endif |
---|
| 150 | |
---|
| 151 | /* end of file */ |
---|