[0a18747] | 1 | /* |
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| 2 | * Cache Management Support Routines for the MC68040 |
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[48694da] | 3 | * Modified for MPC8260 Andy Dachs <a.dachs@sstl.co.uk> |
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| 4 | * Surrey Satellite Technology Limited (SSTL), 2001 |
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[0a18747] | 5 | * |
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| 6 | * $Id$ |
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| 7 | */ |
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| 8 | |
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| 9 | #include <rtems.h> |
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| 10 | #include "cache_.h" |
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| 11 | |
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| 12 | |
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| 13 | /* |
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| 14 | * CACHE MANAGER: The following functions are CPU-specific. |
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| 15 | * They provide the basic implementation for the rtems_* cache |
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| 16 | * management routines. If a given function has no meaning for the CPU, |
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| 17 | * it does nothing by default. |
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| 18 | * |
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| 19 | * FIXME: Some functions simply have not been implemented. |
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| 20 | */ |
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| 21 | |
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[48694da] | 22 | #if defined(ppc603) || defined(mpc8260) /* And possibly others */ |
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[0a18747] | 23 | |
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| 24 | /* Helpful macros */ |
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| 25 | #define PPC_Get_HID0( _value ) \ |
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| 26 | do { \ |
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| 27 | _value = 0; /* to avoid warnings */ \ |
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| 28 | asm volatile( \ |
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| 29 | "mfspr %0, 0x3f0;" /* get HID0 */ \ |
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| 30 | "isync" \ |
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| 31 | : "=r" (_value) \ |
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| 32 | : "0" (_value) \ |
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| 33 | ); \ |
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| 34 | } while (0) |
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| 35 | |
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| 36 | #define PPC_Set_HID0( _value ) \ |
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| 37 | do { \ |
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| 38 | asm volatile( \ |
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| 39 | "isync;" \ |
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| 40 | "mtspr 0x3f0, %0;" /* load HID0 */ \ |
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| 41 | "isync" \ |
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| 42 | : "=r" (_value) \ |
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| 43 | : "0" (_value) \ |
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| 44 | ); \ |
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| 45 | } while (0) |
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| 46 | |
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[5e77d129] | 47 | void _CPU_cache_enable_data ( |
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[0a18747] | 48 | void ) |
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| 49 | { |
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| 50 | unsigned32 value; |
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| 51 | PPC_Get_HID0( value ); |
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| 52 | value |= 0x00004000; /* set DCE bit */ |
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| 53 | PPC_Set_HID0( value ); |
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| 54 | } |
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| 55 | |
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[5e77d129] | 56 | void _CPU_cache_disable_data ( |
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[0a18747] | 57 | void ) |
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| 58 | { |
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| 59 | unsigned32 value; |
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| 60 | PPC_Get_HID0( value ); |
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| 61 | value &= 0xFFFFBFFF; /* clear DCE bit */ |
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| 62 | PPC_Set_HID0( value ); |
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| 63 | } |
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| 64 | |
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[667c8a0] | 65 | void _CPU_cache_enable_instruction ( |
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[0a18747] | 66 | void ) |
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| 67 | { |
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| 68 | unsigned32 value; |
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| 69 | PPC_Get_HID0( value ); |
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| 70 | value |= 0x00008000; /* Set ICE bit */ |
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| 71 | PPC_Set_HID0( value ); |
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| 72 | } |
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| 73 | |
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[667c8a0] | 74 | void _CPU_cache_disable_instruction ( |
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[0a18747] | 75 | void ) |
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| 76 | { |
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| 77 | unsigned32 value; |
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| 78 | PPC_Get_HID0( value ); |
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| 79 | value &= 0xFFFF7FFF; /* Clear ICE bit */ |
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| 80 | PPC_Set_HID0( value ); |
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| 81 | } |
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| 82 | |
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[667c8a0] | 83 | #elif ( defined(mpx8xx) || defined(mpc860) || defined(mpc821) ) |
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[0a18747] | 84 | |
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| 85 | #define mtspr(_spr,_reg) \ |
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| 86 | __asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) ) |
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| 87 | #define isync \ |
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| 88 | __asm__ volatile ("isync\n"::) |
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| 89 | |
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[5e77d129] | 90 | void _CPU_cache_flush_1_data_line( |
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[0a18747] | 91 | const void * _address ) |
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| 92 | { |
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| 93 | register const void *__address = _address; |
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| 94 | asm volatile ( "dcbf 0,%0" :: "r" (__address) ); |
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| 95 | } |
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| 96 | |
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[5e77d129] | 97 | void _CPU_cache_invalidate_1_data_line( |
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[0a18747] | 98 | const void * _address ) |
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| 99 | { |
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| 100 | register const void *__address = _address; |
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| 101 | asm volatile ( "dcbi 0,%0" :: "r" (__address) ); |
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| 102 | } |
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| 103 | |
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[5e77d129] | 104 | void _CPU_cache_flush_entire_data ( void ) {} |
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| 105 | void _CPU_cache_invalidate_entire_data ( void ) {} |
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| 106 | void _CPU_cache_freeze_data ( void ) {} |
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| 107 | void _CPU_cache_unfreeze_data ( void ) {} |
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[0a18747] | 108 | |
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[5e77d129] | 109 | void _CPU_cache_enable_data ( void ) |
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[0a18747] | 110 | { |
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| 111 | unsigned32 r1; |
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| 112 | r1 = (0x2<<24); |
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| 113 | mtspr( 568, r1 ); |
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| 114 | isync; |
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| 115 | } |
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| 116 | |
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[5e77d129] | 117 | void _CPU_cache_disable_data ( void ) |
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[0a18747] | 118 | { |
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| 119 | unsigned32 r1; |
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| 120 | r1 = (0x4<<24); |
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| 121 | mtspr( 568, r1 ); |
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| 122 | isync; |
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| 123 | } |
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| 124 | |
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[667c8a0] | 125 | void _CPU_cache_invalidate_1_instruction_line( |
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[0a18747] | 126 | const void * _address ) |
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| 127 | { |
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| 128 | register const void *__address = _address; |
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| 129 | asm volatile ( "icbi 0,%0" :: "r" (__address) ); |
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| 130 | } |
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| 131 | |
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[667c8a0] | 132 | void _CPU_cache_invalidate_entire_instruction ( void ) {} |
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| 133 | void _CPU_cache_freeze_instruction ( void ) {} |
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| 134 | void _CPU_cache_unfreeze_instruction ( void ) {} |
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[0a18747] | 135 | |
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[667c8a0] | 136 | void _CPU_cache_enable_instruction ( void ) |
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[0a18747] | 137 | { |
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| 138 | unsigned32 r1; |
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| 139 | r1 = (0x2<<24); |
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| 140 | mtspr( 560, r1 ); |
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| 141 | isync; |
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| 142 | } |
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| 143 | |
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[667c8a0] | 144 | void _CPU_cache_disable_instruction ( void ) |
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[0a18747] | 145 | { |
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| 146 | unsigned32 r1; |
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| 147 | r1 = (0x4<<24); |
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| 148 | mtspr( 560, r1 ); |
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| 149 | isync; |
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| 150 | } |
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| 151 | #endif |
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| 152 | |
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| 153 | /* end of file */ |
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