1 | /* |
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2 | * mmu.h |
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3 | * |
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4 | * PowerPC memory management structures |
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5 | * |
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6 | * It is a stripped down version of linux ppc file... |
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7 | * |
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8 | * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) |
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9 | * Canon Centre Recherche France. |
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10 | * |
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11 | * The license and distribution terms for this file may be |
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12 | * found in found in the file LICENSE in this distribution or at |
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13 | * http://www.OARcorp.com/rtems/license.html. |
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14 | * |
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15 | * $Id$ |
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16 | */ |
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17 | |
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18 | #ifndef _PPC_MMU_H_ |
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19 | #define _PPC_MMU_H_ |
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20 | |
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21 | #ifndef ASM |
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22 | /* Hardware Page Table Entry */ |
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23 | typedef struct _PTE { |
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24 | unsigned long v:1; /* Entry is valid */ |
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25 | unsigned long vsid:24; /* Virtual segment identifier */ |
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26 | unsigned long h:1; /* Hash algorithm indicator */ |
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27 | unsigned long api:6; /* Abbreviated page index */ |
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28 | unsigned long rpn:20; /* Real (physical) page number */ |
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29 | unsigned long :3; /* Unused */ |
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30 | unsigned long r:1; /* Referenced */ |
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31 | unsigned long c:1; /* Changed */ |
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32 | unsigned long w:1; /* Write-thru cache mode */ |
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33 | unsigned long i:1; /* Cache inhibited */ |
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34 | unsigned long m:1; /* Memory coherence */ |
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35 | unsigned long g:1; /* Guarded */ |
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36 | unsigned long :1; /* Unused */ |
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37 | unsigned long pp:2; /* Page protection */ |
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38 | } PTE; |
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39 | |
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40 | /* Values for PP (assumes Ks=0, Kp=1) */ |
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41 | #define PP_RWXX 0 /* Supervisor read/write, User none */ |
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42 | #define PP_RWRX 1 /* Supervisor read/write, User read */ |
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43 | #define PP_RWRW 2 /* Supervisor read/write, User read/write */ |
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44 | #define PP_RXRX 3 /* Supervisor read, User read */ |
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45 | |
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46 | /* Segment Register */ |
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47 | typedef struct _SEGREG { |
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48 | unsigned long t:1; /* Normal or I/O type */ |
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49 | unsigned long ks:1; /* Supervisor 'key' (normally 0) */ |
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50 | unsigned long kp:1; /* User 'key' (normally 1) */ |
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51 | unsigned long n:1; /* No-execute */ |
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52 | unsigned long :4; /* Unused */ |
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53 | unsigned long vsid:24; /* Virtual Segment Identifier */ |
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54 | } SEGREG; |
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55 | |
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56 | /* Block Address Translation (BAT) Registers */ |
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57 | typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */ |
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58 | unsigned long bepi:15; /* Effective page index (virtual address) */ |
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59 | unsigned long :8; /* unused */ |
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60 | unsigned long w:1; |
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61 | unsigned long i:1; /* Cache inhibit */ |
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62 | unsigned long m:1; /* Memory coherence */ |
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63 | unsigned long ks:1; /* Supervisor key (normally 0) */ |
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64 | unsigned long kp:1; /* User key (normally 1) */ |
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65 | unsigned long pp:2; /* Page access protections */ |
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66 | } P601_BATU; |
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67 | |
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68 | typedef struct _BATU { /* Upper part of BAT (all except 601) */ |
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69 | unsigned long bepi:15; /* Effective page index (virtual address) */ |
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70 | unsigned long :4; /* Unused */ |
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71 | unsigned long bl:11; /* Block size mask */ |
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72 | unsigned long vs:1; /* Supervisor valid */ |
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73 | unsigned long vp:1; /* User valid */ |
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74 | } BATU; |
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75 | |
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76 | typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */ |
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77 | unsigned long brpn:15; /* Real page index (physical address) */ |
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78 | unsigned long :10; /* Unused */ |
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79 | unsigned long v:1; /* Valid bit */ |
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80 | unsigned long bl:6; /* Block size mask */ |
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81 | } P601_BATL; |
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82 | |
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83 | typedef struct _BATL { /* Lower part of BAT (all except 601) */ |
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84 | unsigned long brpn:15; /* Real page index (physical address) */ |
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85 | unsigned long :10; /* Unused */ |
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86 | unsigned long w:1; /* Write-thru cache */ |
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87 | unsigned long i:1; /* Cache inhibit */ |
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88 | unsigned long m:1; /* Memory coherence */ |
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89 | unsigned long g:1; /* Guarded (MBZ in IBAT) */ |
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90 | unsigned long :1; /* Unused */ |
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91 | unsigned long pp:2; /* Page access protections */ |
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92 | } BATL; |
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93 | |
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94 | typedef struct _BAT { |
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95 | BATU batu; /* Upper register */ |
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96 | BATL batl; /* Lower register */ |
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97 | } BAT; |
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98 | |
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99 | typedef struct _P601_BAT { |
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100 | P601_BATU batu; /* Upper register */ |
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101 | P601_BATL batl; /* Lower register */ |
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102 | } P601_BAT; |
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103 | |
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104 | /* Block size masks */ |
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105 | #define BL_128K 0x000 |
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106 | #define BL_256K 0x001 |
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107 | #define BL_512K 0x003 |
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108 | #define BL_1M 0x007 |
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109 | #define BL_2M 0x00F |
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110 | #define BL_4M 0x01F |
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111 | #define BL_8M 0x03F |
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112 | #define BL_16M 0x07F |
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113 | #define BL_32M 0x0FF |
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114 | #define BL_64M 0x1FF |
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115 | #define BL_128M 0x3FF |
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116 | #define BL_256M 0x7FF |
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117 | |
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118 | /* BAT Access Protection */ |
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119 | #define BPP_XX 0x00 /* No access */ |
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120 | #define BPP_RX 0x01 /* Read only */ |
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121 | #define BPP_RW 0x02 /* Read/write */ |
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122 | |
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123 | /* |
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124 | * Simulated two-level MMU. This structure is used by the kernel |
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125 | * to keep track of MMU mappings and is used to update/maintain |
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126 | * the hardware HASH table which is really a cache of mappings. |
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127 | * |
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128 | * The simulated structures mimic the hardware available on other |
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129 | * platforms, notably the 80x86 and 680x0. |
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130 | */ |
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131 | |
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132 | typedef struct _pte { |
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133 | unsigned long page_num:20; |
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134 | unsigned long flags:12; /* Page flags (some unused bits) */ |
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135 | } pte; |
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136 | |
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137 | #define PD_SHIFT (10+12) /* Page directory */ |
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138 | #define PD_MASK 0x03FF |
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139 | #define PT_SHIFT (12) /* Page Table */ |
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140 | #define PT_MASK 0x03FF |
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141 | #define PG_SHIFT (12) /* Page Entry */ |
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142 | |
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143 | |
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144 | /* MMU context */ |
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145 | |
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146 | typedef struct _MMU_context { |
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147 | SEGREG segs[16]; /* Segment registers */ |
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148 | pte **pmap; /* Two-level page-map structure */ |
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149 | } MMU_context; |
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150 | |
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151 | /* Used to set up SDR1 register */ |
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152 | #define HASH_TABLE_SIZE_64K 0x00010000 |
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153 | #define HASH_TABLE_SIZE_128K 0x00020000 |
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154 | #define HASH_TABLE_SIZE_256K 0x00040000 |
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155 | #define HASH_TABLE_SIZE_512K 0x00080000 |
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156 | #define HASH_TABLE_SIZE_1M 0x00100000 |
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157 | #define HASH_TABLE_SIZE_2M 0x00200000 |
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158 | #define HASH_TABLE_SIZE_4M 0x00400000 |
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159 | #define HASH_TABLE_MASK_64K 0x000 |
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160 | #define HASH_TABLE_MASK_128K 0x001 |
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161 | #define HASH_TABLE_MASK_256K 0x003 |
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162 | #define HASH_TABLE_MASK_512K 0x007 |
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163 | #define HASH_TABLE_MASK_1M 0x00F |
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164 | #define HASH_TABLE_MASK_2M 0x01F |
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165 | #define HASH_TABLE_MASK_4M 0x03F |
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166 | |
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167 | /* invalidate a TLB entry */ |
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168 | extern inline void _tlbie(unsigned long va) |
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169 | { |
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170 | asm volatile ("tlbie %0" : : "r"(va)); |
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171 | } |
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172 | |
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173 | extern void _tlbia(void); /* invalidate all TLB entries */ |
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174 | #endif /* ASM */ |
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175 | |
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176 | /* Control/status registers for the MPC8xx. |
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177 | * A write operation to these registers causes serialized access. |
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178 | * During software tablewalk, the registers used perform mask/shift-add |
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179 | * operations when written/read. A TLB entry is created when the Mx_RPN |
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180 | * is written, and the contents of several registers are used to |
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181 | * create the entry. |
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182 | */ |
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183 | #define MI_CTR 784 /* Instruction TLB control register */ |
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184 | #define MI_GPM 0x80000000 /* Set domain manager mode */ |
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185 | #define MI_PPM 0x40000000 /* Set subpage protection */ |
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186 | #define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ |
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187 | #define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */ |
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188 | #define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ |
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189 | #define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */ |
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190 | #define MI_RESETVAL 0x00000000 /* Value of register at reset */ |
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191 | |
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192 | /* These are the Ks and Kp from the PowerPC books. For proper operation, |
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193 | * Ks = 0, Kp = 1. |
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194 | */ |
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195 | #define MI_AP 786 |
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196 | #define MI_Ks 0x80000000 /* Should not be set */ |
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197 | #define MI_Kp 0x40000000 /* Should always be set */ |
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198 | |
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199 | /* The effective page number register. When read, contains the information |
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200 | * about the last instruction TLB miss. When MI_RPN is written, bits in |
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201 | * this register are used to create the TLB entry. |
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202 | */ |
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203 | #define MI_EPN 787 |
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204 | #define MI_EPNMASK 0xfffff000 /* Effective page number for entry */ |
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205 | #define MI_EVALID 0x00000200 /* Entry is valid */ |
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206 | #define MI_ASIDMASK 0x0000000f /* ASID match value */ |
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207 | /* Reset value is undefined */ |
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208 | |
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209 | /* A "level 1" or "segment" or whatever you want to call it register. |
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210 | * For the instruction TLB, it contains bits that get loaded into the |
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211 | * TLB entry when the MI_RPN is written. |
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212 | */ |
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213 | #define MI_TWC 789 |
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214 | #define MI_APG 0x000001e0 /* Access protection group (0) */ |
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215 | #define MI_GUARDED 0x00000010 /* Guarded storage */ |
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216 | #define MI_PSMASK 0x0000000c /* Mask of page size bits */ |
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217 | #define MI_PS8MEG 0x0000000c /* 8M page size */ |
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218 | #define MI_PS512K 0x00000004 /* 512K page size */ |
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219 | #define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */ |
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220 | #define MI_SVALID 0x00000001 /* Segment entry is valid */ |
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221 | /* Reset value is undefined */ |
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222 | |
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223 | /* Real page number. Defined by the pte. Writing this register |
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224 | * causes a TLB entry to be created for the instruction TLB, using |
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225 | * additional information from the MI_EPN, and MI_TWC registers. |
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226 | */ |
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227 | #define MI_RPN 790 |
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228 | |
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229 | /* Define an RPN value for mapping kernel memory to large virtual |
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230 | * pages for boot initialization. This has real page number of 0, |
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231 | * large page size, shared page, cache enabled, and valid. |
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232 | * Also mark all subpages valid and write access. |
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233 | */ |
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234 | #define MI_BOOTINIT 0x000001fd |
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235 | |
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236 | #define MD_CTR 792 /* Data TLB control register */ |
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237 | #define MD_GPM 0x80000000 /* Set domain manager mode */ |
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238 | #define MD_PPM 0x40000000 /* Set subpage protection */ |
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239 | #define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ |
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240 | #define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */ |
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241 | #define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */ |
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242 | #define MD_TWAM 0x04000000 /* Use 4K page hardware assist */ |
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243 | #define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ |
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244 | #define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */ |
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245 | #define MD_RESETVAL 0x04000000 /* Value of register at reset */ |
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246 | |
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247 | #define M_CASID 793 /* Address space ID (context) to match */ |
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248 | #define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */ |
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249 | |
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250 | |
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251 | /* These are the Ks and Kp from the PowerPC books. For proper operation, |
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252 | * Ks = 0, Kp = 1. |
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253 | */ |
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254 | #define MD_AP 794 |
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255 | #define MD_Ks 0x80000000 /* Should not be set */ |
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256 | #define MD_Kp 0x40000000 /* Should always be set */ |
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257 | |
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258 | /* The effective page number register. When read, contains the information |
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259 | * about the last instruction TLB miss. When MD_RPN is written, bits in |
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260 | * this register are used to create the TLB entry. |
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261 | */ |
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262 | #define MD_EPN 795 |
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263 | #define MD_EPNMASK 0xfffff000 /* Effective page number for entry */ |
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264 | #define MD_EVALID 0x00000200 /* Entry is valid */ |
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265 | #define MD_ASIDMASK 0x0000000f /* ASID match value */ |
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266 | /* Reset value is undefined */ |
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267 | |
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268 | /* The pointer to the base address of the first level page table. |
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269 | * During a software tablewalk, reading this register provides the address |
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270 | * of the entry associated with MD_EPN. |
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271 | */ |
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272 | #define M_TWB 796 |
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273 | #define M_L1TB 0xfffff000 /* Level 1 table base address */ |
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274 | #define M_L1INDX 0x00000ffc /* Level 1 index, when read */ |
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275 | /* Reset value is undefined */ |
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276 | |
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277 | /* A "level 1" or "segment" or whatever you want to call it register. |
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278 | * For the data TLB, it contains bits that get loaded into the TLB entry |
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279 | * when the MD_RPN is written. It is also provides the hardware assist |
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280 | * for finding the PTE address during software tablewalk. |
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281 | */ |
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282 | #define MD_TWC 797 |
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283 | #define MD_L2TB 0xfffff000 /* Level 2 table base address */ |
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284 | #define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */ |
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285 | #define MD_APG 0x000001e0 /* Access protection group (0) */ |
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286 | #define MD_GUARDED 0x00000010 /* Guarded storage */ |
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287 | #define MD_PSMASK 0x0000000c /* Mask of page size bits */ |
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288 | #define MD_PS8MEG 0x0000000c /* 8M page size */ |
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289 | #define MD_PS512K 0x00000004 /* 512K page size */ |
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290 | #define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */ |
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291 | #define MD_WT 0x00000002 /* Use writethrough page attribute */ |
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292 | #define MD_SVALID 0x00000001 /* Segment entry is valid */ |
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293 | /* Reset value is undefined */ |
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294 | |
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295 | |
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296 | /* Real page number. Defined by the pte. Writing this register |
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297 | * causes a TLB entry to be created for the data TLB, using |
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298 | * additional information from the MD_EPN, and MD_TWC registers. |
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299 | */ |
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300 | #define MD_RPN 798 |
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301 | |
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302 | /* This is a temporary storage register that could be used to save |
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303 | * a processor working register during a tablewalk. |
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304 | */ |
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305 | #define M_TW 799 |
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306 | #endif /* _PPC_MMU_H_ */ |
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