source: rtems/c/src/lib/libcpu/powerpc/shared/include/spr.h @ 73b5bd5d

4.104.114.84.95
Last change on this file since 73b5bd5d was 21e1c44, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 4, 2003 at 6:53:10 PM

2003-09-04 Joel Sherrill <joel@…>

  • mpc6xx/clock/c_clock.c, mpc6xx/clock/c_clock.h, mpc6xx/exceptions/raw_exception.c, mpc6xx/exceptions/raw_exception.h, mpc6xx/mmu/bat.c, mpc6xx/mmu/bat.h, mpc6xx/mmu/mmuAsm.S, mpc6xx/timer/timer.c, mpc8260/clock/clock.c, mpc8260/console-generic/console-generic.c, mpc8260/cpm/brg.c, mpc8260/exceptions/raw_exception.c, mpc8260/exceptions/raw_exception.h, mpc8260/include/cpm.h, mpc8260/include/mmu.h, mpc8260/mmu/mmu.c, mpc8260/timer/timer.c, mpc8xx/clock/clock.c, mpc8xx/console-generic/console-generic.c, mpc8xx/exceptions/raw_exception.c, mpc8xx/exceptions/raw_exception.h, mpc8xx/include/cpm.h, mpc8xx/include/mmu.h, mpc8xx/mmu/mmu.c, mpc8xx/timer/timer.c, ppc403/clock/clock.c, ppc403/console/console.c.polled, ppc403/timer/timer.c, rtems/powerpc/debugmod.h, shared/include/byteorder.h, shared/include/cpuIdent.c, shared/include/cpuIdent.h, shared/include/io.h, shared/include/mmu.h, shared/include/page.h, shared/include/pgtable.h, shared/include/spr.h: URL for license changed.
  • Property mode set to 100644
File size: 1.5 KB
RevLine 
[abd9401]1/*
2 *  spr.h -- Access to special purpose registers.
3 *
4 *  Copyright (C) 1998 Gabriel Paubert, paubert@iram.es
5 *
6 *  Modified to compile in RTEMS development environment
7 *  by Eric Valette
8 *
9 *  Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
10 *
11 *  The license and distribution terms for this file may be
12 *  found in found in the file LICENSE in this distribution or at
[21e1c44]13 *  http://www.rtems.com/license/LICENSE.
[abd9401]14 *
15 * $Id$
16 *
17 */
18
19
20#ifndef _PPC_SPR_H
21#define _PPC_SPR_H
22
[a73a977]23#include <rtems/powerpc/registers.h>
[abd9401]24
25#define __MFSPR(reg, val) \
26        __asm__ __volatile__("mfspr %0,"#reg : "=r" (val))
27
28#define __MTSPR(val, reg) \
29        __asm__ __volatile__("mtspr "#reg",%0" : : "r" (val))
30
31
32#define SPR_RW(reg) \
33static inline unsigned long _read_##reg(void) \
34{\
35        unsigned long val;\
36        __MFSPR(reg, val);\
37        return val;\
38}\
39static inline void _write_##reg(unsigned long val)\
40{\
41        __MTSPR(val,reg);\
42        return;\
43}
44
45#define SPR_RO(reg) \
46static inline unsigned long _read_##reg(void) \
47{\
48        unsigned long val;\
49        __MFSPR(reg,val);\
50        return val;\
51}
52
53static inline unsigned long _read_MSR(void)
54{
55        unsigned long val;
56        asm volatile("mfmsr %0" : "=r" (val));
57        return val;
58} 
59
60static inline void _write_MSR(unsigned long val)
61{
62        asm volatile("mtmsr %0" : : "r" (val));
63        return;
64}
65
66static inline unsigned long _read_SR(void * va)
67{
68        unsigned long val;
69        asm volatile("mfsrin %0,%1" : "=r" (val): "r" (va));
70        return val;
71} 
72
73static inline void _write_SR(unsigned long val, void * va)
74{
75        asm volatile("mtsrin %0,%1" : : "r"(val), "r" (va): "memory");
76        return;
77}
78
79
80#endif
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