1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup powerpc_shared |
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5 | * |
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6 | * @brief General purpose assembler macros, linker command file support and |
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7 | * some inline functions for direct register access. |
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8 | */ |
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9 | |
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10 | /* |
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11 | * Copyright (c) 2008-2014 embedded brains GmbH. |
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12 | * |
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13 | * embedded brains GmbH |
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14 | * Dornierstr. 4 |
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15 | * 82178 Puchheim |
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16 | * Germany |
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17 | * <rtems@embedded-brains.de> |
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18 | * |
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19 | * access function for Device Control Registers inspired by "ppc405common.h" |
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20 | * from Michael Hamel ADInstruments May 2008 |
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21 | * |
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22 | * The license and distribution terms for this file may be |
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23 | * found in the file LICENSE in this distribution or at |
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24 | * http://www.rtems.org/license/LICENSE. |
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25 | */ |
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26 | |
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27 | /** |
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28 | * @defgroup powerpc_shared Shared PowerPC Code |
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29 | */ |
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30 | |
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31 | #ifndef __LIBCPU_POWERPC_UTILITY_H |
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32 | #define __LIBCPU_POWERPC_UTILITY_H |
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33 | |
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34 | #if !defined(ASM) |
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35 | #include <rtems.h> |
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36 | #endif |
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37 | |
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38 | #include <rtems/score/cpu.h> |
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39 | #include <rtems/powerpc/registers.h> |
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40 | #include <rtems/powerpc/powerpc.h> |
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41 | |
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42 | #ifdef __cplusplus |
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43 | extern "C" { |
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44 | #endif |
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45 | |
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46 | #if !defined(ASM) |
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47 | |
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48 | #include <rtems/bspIo.h> |
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49 | #include <rtems/system.h> |
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50 | |
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51 | #include <libcpu/cpuIdent.h> |
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52 | |
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53 | #define LINKER_SYMBOL(sym) extern char sym []; |
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54 | |
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55 | /** |
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56 | * @brief Read one byte from @a src. |
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57 | */ |
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58 | static inline uint8_t ppc_read_byte(const volatile void *src) |
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59 | { |
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60 | uint8_t value; |
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61 | |
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62 | __asm__ volatile ( |
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63 | "lbz %0, 0(%1)" |
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64 | : "=r" (value) |
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65 | : "b" (src) |
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66 | ); |
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67 | |
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68 | return value; |
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69 | } |
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70 | |
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71 | /** |
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72 | * @brief Read one half word from @a src. |
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73 | */ |
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74 | static inline uint16_t ppc_read_half_word(const volatile void *src) |
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75 | { |
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76 | uint16_t value; |
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77 | |
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78 | __asm__ volatile ( |
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79 | "lhz %0, 0(%1)" |
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80 | : "=r" (value) |
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81 | : "b" (src) |
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82 | ); |
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83 | |
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84 | return value; |
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85 | } |
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86 | |
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87 | /** |
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88 | * @brief Read one word from @a src. |
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89 | */ |
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90 | static inline uint32_t ppc_read_word(const volatile void *src) |
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91 | { |
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92 | uint32_t value; |
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93 | |
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94 | __asm__ volatile ( |
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95 | "lwz %0, 0(%1)" |
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96 | : "=r" (value) |
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97 | : "b" (src) |
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98 | ); |
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99 | |
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100 | return value; |
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101 | } |
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102 | |
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103 | /** |
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104 | * @brief Write one byte @a value to @a dest. |
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105 | */ |
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106 | static inline void ppc_write_byte(uint8_t value, volatile void *dest) |
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107 | { |
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108 | __asm__ volatile ( |
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109 | "stb %0, 0(%1)" |
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110 | : |
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111 | : "r" (value), "b" (dest) |
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112 | ); |
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113 | } |
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114 | |
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115 | /** |
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116 | * @brief Write one half word @a value to @a dest. |
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117 | */ |
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118 | static inline void ppc_write_half_word(uint16_t value, volatile void *dest) |
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119 | { |
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120 | __asm__ volatile ( |
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121 | "sth %0, 0(%1)" |
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122 | : |
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123 | : "r" (value), "b" (dest) |
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124 | ); |
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125 | } |
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126 | |
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127 | /** |
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128 | * @brief Write one word @a value to @a dest. |
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129 | */ |
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130 | static inline void ppc_write_word(uint32_t value, volatile void *dest) |
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131 | { |
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132 | __asm__ volatile ( |
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133 | "stw %0, 0(%1)" : |
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134 | : "r" (value), "b" (dest) |
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135 | ); |
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136 | } |
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137 | |
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138 | |
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139 | static inline void *ppc_stack_pointer(void) |
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140 | { |
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141 | void *sp; |
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142 | |
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143 | __asm__ volatile ( |
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144 | "mr %0, 1" |
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145 | : "=r" (sp) |
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146 | ); |
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147 | |
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148 | return sp; |
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149 | } |
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150 | |
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151 | static inline void ppc_set_stack_pointer(void *sp) |
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152 | { |
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153 | __asm__ volatile ( |
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154 | "mr 1, %0" |
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155 | : |
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156 | : "r" (sp) |
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157 | ); |
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158 | } |
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159 | |
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160 | static inline void *ppc_link_register(void) |
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161 | { |
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162 | void *lr; |
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163 | |
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164 | __asm__ volatile ( |
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165 | "mflr %0" |
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166 | : "=r" (lr) |
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167 | ); |
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168 | |
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169 | return lr; |
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170 | } |
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171 | |
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172 | static inline void ppc_set_link_register(void *lr) |
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173 | { |
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174 | __asm__ volatile ( |
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175 | "mtlr %0" |
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176 | : |
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177 | : "r" (lr) |
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178 | ); |
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179 | } |
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180 | |
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181 | static inline uint32_t ppc_machine_state_register(void) |
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182 | { |
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183 | uint32_t msr; |
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184 | |
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185 | __asm__ volatile ( |
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186 | "mfmsr %0" |
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187 | : "=r" (msr) |
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188 | ); |
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189 | |
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190 | return msr; |
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191 | } |
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192 | |
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193 | static inline void ppc_set_machine_state_register(uint32_t msr) |
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194 | { |
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195 | __asm__ volatile ( |
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196 | "mtmsr %0" |
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197 | : |
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198 | : "r" (msr) |
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199 | ); |
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200 | } |
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201 | |
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202 | static inline void ppc_synchronize_data(void) |
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203 | { |
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204 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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205 | |
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206 | __asm__ volatile ("sync"); |
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207 | } |
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208 | |
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209 | static inline void ppc_synchronize_instructions(void) |
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210 | { |
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211 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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212 | |
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213 | __asm__ volatile ("isync"); |
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214 | } |
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215 | |
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216 | static inline void ppc_enforce_in_order_execution_of_io(void) |
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217 | { |
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218 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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219 | |
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220 | __asm__ volatile ("eieio"); |
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221 | } |
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222 | |
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223 | static inline void ppc_data_cache_block_flush(void *addr) |
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224 | { |
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225 | __asm__ volatile ( |
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226 | "dcbf 0, %0" |
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227 | : |
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228 | : "r" (addr) |
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229 | : "memory" |
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230 | ); |
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231 | } |
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232 | |
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233 | static inline void ppc_data_cache_block_flush_2( |
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234 | void *base, |
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235 | uintptr_t offset |
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236 | ) |
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237 | { |
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238 | __asm__ volatile ( |
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239 | "dcbf %0, %1" |
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240 | : |
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241 | : "b" (base), "r" (offset) |
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242 | : "memory" |
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243 | ); |
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244 | } |
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245 | |
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246 | static inline void ppc_data_cache_block_invalidate(void *addr) |
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247 | { |
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248 | __asm__ volatile ( |
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249 | "dcbi 0, %0" |
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250 | : |
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251 | : "r" (addr) |
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252 | : "memory" |
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253 | ); |
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254 | } |
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255 | |
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256 | static inline void ppc_data_cache_block_invalidate_2( |
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257 | void *base, |
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258 | uintptr_t offset |
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259 | ) |
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260 | { |
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261 | __asm__ volatile ( |
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262 | "dcbi %0, %1" |
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263 | : |
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264 | : "b" (base), "r" (offset) |
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265 | : "memory" |
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266 | ); |
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267 | } |
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268 | |
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269 | static inline void ppc_data_cache_block_store(const void *addr) |
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270 | { |
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271 | __asm__ volatile ( |
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272 | "dcbst 0, %0" |
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273 | : |
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274 | : "r" (addr) |
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275 | ); |
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276 | } |
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277 | |
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278 | static inline void ppc_data_cache_block_store_2( |
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279 | const void *base, |
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280 | uintptr_t offset |
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281 | ) |
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282 | { |
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283 | __asm__ volatile ( |
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284 | "dcbst %0, %1" |
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285 | : |
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286 | : "b" (base), "r" (offset) |
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287 | ); |
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288 | } |
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289 | |
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290 | static inline void ppc_data_cache_block_touch(const void *addr) |
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291 | { |
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292 | __asm__ volatile ( |
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293 | "dcbt 0, %0" |
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294 | : |
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295 | : "r" (addr) |
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296 | ); |
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297 | } |
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298 | |
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299 | static inline void ppc_data_cache_block_touch_2( |
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300 | const void *base, |
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301 | uintptr_t offset |
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302 | ) |
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303 | { |
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304 | __asm__ volatile ( |
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305 | "dcbt %0, %1" |
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306 | : |
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307 | : "b" (base), "r" (offset) |
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308 | ); |
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309 | } |
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310 | |
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311 | static inline void ppc_data_cache_block_touch_for_store(const void *addr) |
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312 | { |
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313 | __asm__ volatile ( |
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314 | "dcbtst 0, %0" |
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315 | : |
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316 | : "r" (addr) |
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317 | ); |
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318 | } |
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319 | |
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320 | static inline void ppc_data_cache_block_touch_for_store_2( |
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321 | const void *base, |
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322 | uintptr_t offset |
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323 | ) |
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324 | { |
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325 | __asm__ volatile ( |
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326 | "dcbtst %0, %1" |
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327 | : |
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328 | : "b" (base), "r" (offset) |
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329 | ); |
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330 | } |
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331 | |
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332 | static inline void ppc_data_cache_block_clear_to_zero(void *addr) |
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333 | { |
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334 | __asm__ volatile ( |
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335 | "dcbz 0, %0" |
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336 | : |
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337 | : "r" (addr) |
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338 | : "memory" |
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339 | ); |
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340 | } |
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341 | |
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342 | static inline void ppc_data_cache_block_clear_to_zero_2( |
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343 | void *base, |
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344 | uintptr_t offset |
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345 | ) |
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346 | { |
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347 | __asm__ volatile ( |
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348 | "dcbz %0, %1" |
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349 | : |
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350 | : "b" (base), "r" (offset) |
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351 | : "memory" |
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352 | ); |
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353 | } |
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354 | |
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355 | static inline void ppc_instruction_cache_block_invalidate(void *addr) |
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356 | { |
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357 | __asm__ volatile ( |
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358 | "icbi 0, %0" |
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359 | : |
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360 | : "r" (addr) |
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361 | ); |
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362 | } |
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363 | |
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364 | static inline void ppc_instruction_cache_block_invalidate_2( |
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365 | void *base, |
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366 | uintptr_t offset |
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367 | ) |
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368 | { |
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369 | __asm__ volatile ( |
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370 | "icbi %0, %1" |
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371 | : |
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372 | : "b" (base), "r" (offset) |
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373 | ); |
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374 | } |
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375 | |
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376 | /** |
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377 | * @brief Enables external exceptions. |
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378 | * |
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379 | * You can use this function to enable the external exceptions and restore the |
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380 | * machine state with ppc_external_exceptions_disable() later. |
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381 | */ |
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382 | static inline uint32_t ppc_external_exceptions_enable(void) |
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383 | { |
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384 | uint32_t current_msr; |
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385 | uint32_t new_msr; |
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386 | |
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387 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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388 | |
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389 | __asm__ volatile ( |
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390 | "mfmsr %0;" |
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391 | "ori %1, %0, 0x8000;" |
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392 | "mtmsr %1" |
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393 | : "=r" (current_msr), "=r" (new_msr) |
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394 | ); |
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395 | |
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396 | return current_msr; |
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397 | } |
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398 | |
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399 | /** |
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400 | * @brief Restores machine state. |
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401 | * |
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402 | * @see ppc_external_exceptions_enable() |
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403 | */ |
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404 | static inline void ppc_external_exceptions_disable(uint32_t msr) |
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405 | { |
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406 | ppc_set_machine_state_register(msr); |
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407 | |
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408 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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409 | } |
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410 | |
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411 | static inline uint32_t ppc_count_leading_zeros(uint32_t value) |
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412 | { |
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413 | uint32_t count; |
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414 | |
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415 | __asm__ ( |
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416 | "cntlzw %0, %1;" |
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417 | : "=r" (count) |
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418 | : "r" (value) |
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419 | ); |
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420 | |
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421 | return count; |
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422 | } |
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423 | |
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424 | /* |
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425 | * Simple spin delay in microsecond units for device drivers. |
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426 | * This is very dependent on the clock speed of the target. |
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427 | */ |
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428 | |
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429 | #if defined(mpx8xx) || defined(mpc860) || defined(mpc821) |
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430 | /* Wonderful bookE doesn't have mftb/mftbu; they only |
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431 | * define the TBRU/TBRL SPRs so we use these. Luckily, |
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432 | * we run in supervisory mode so that should work on |
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433 | * all CPUs. In user mode we'd have a problem... |
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434 | * 2007/11/30, T.S. |
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435 | * |
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436 | * OTOH, PSIM currently lacks support for reading |
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437 | * SPRs 268/269. You need GDB patch sim/2376 to avoid |
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438 | * a crash... |
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439 | * OTOH, the MPC8xx do not allow to read the timebase registers via mfspr. |
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440 | * we NEED a mftb to access the time base. |
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441 | * 2009/10/30 Th. D. |
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442 | */ |
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443 | #define CPU_Get_timebase_low( _value ) \ |
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444 | __asm__ volatile( "mftb %0" : "=r" (_value) ) |
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445 | #else |
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446 | #define CPU_Get_timebase_low( _value ) \ |
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447 | __asm__ volatile( "mfspr %0,268" : "=r" (_value) ) |
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448 | #endif |
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449 | |
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450 | /* Must be provided for rtems_bsp_delay to work */ |
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451 | extern uint32_t bsp_clicks_per_usec; |
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452 | |
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453 | #define rtems_bsp_delay( _microseconds ) \ |
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454 | do { \ |
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455 | uint32_t start, ticks, now; \ |
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456 | CPU_Get_timebase_low( start ) ; \ |
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457 | ticks = (_microseconds) * bsp_clicks_per_usec; \ |
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458 | do \ |
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459 | CPU_Get_timebase_low( now ) ; \ |
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460 | while (now - start < ticks); \ |
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461 | } while (0) |
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462 | |
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463 | #define rtems_bsp_delay_in_bus_cycles( _cycles ) \ |
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464 | do { \ |
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465 | uint32_t start, now; \ |
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466 | CPU_Get_timebase_low( start ); \ |
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467 | do \ |
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468 | CPU_Get_timebase_low( now ); \ |
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469 | while (now - start < (_cycles)); \ |
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470 | } while (0) |
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471 | |
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472 | /* |
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473 | * Routines to access the decrementer register |
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474 | */ |
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475 | |
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476 | #define PPC_Set_decrementer( _clicks ) \ |
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477 | do { \ |
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478 | __asm__ volatile( "mtdec %0" : : "r" ((_clicks)) ); \ |
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479 | } while (0) |
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480 | |
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481 | #define PPC_Get_decrementer( _clicks ) \ |
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482 | __asm__ volatile( "mfdec %0" : "=r" (_clicks) ) |
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483 | |
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484 | /* |
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485 | * Routines to access the time base register |
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486 | */ |
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487 | |
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488 | static inline uint64_t PPC_Get_timebase_register( void ) |
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489 | { |
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490 | uint32_t tbr_low; |
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491 | uint32_t tbr_high; |
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492 | uint32_t tbr_high_old; |
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493 | uint64_t tbr; |
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494 | |
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495 | do { |
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496 | #if defined(mpx8xx) || defined(mpc860) || defined(mpc821) |
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497 | /* See comment above (CPU_Get_timebase_low) */ |
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498 | __asm__ volatile( "mftbu %0" : "=r" (tbr_high_old)); |
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499 | __asm__ volatile( "mftb %0" : "=r" (tbr_low)); |
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500 | __asm__ volatile( "mftbu %0" : "=r" (tbr_high)); |
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501 | #else |
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502 | __asm__ volatile( "mfspr %0, 269" : "=r" (tbr_high_old)); |
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503 | __asm__ volatile( "mfspr %0, 268" : "=r" (tbr_low)); |
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504 | __asm__ volatile( "mfspr %0, 269" : "=r" (tbr_high)); |
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505 | #endif |
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506 | } while ( tbr_high_old != tbr_high ); |
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507 | |
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508 | tbr = tbr_high; |
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509 | tbr <<= 32; |
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510 | tbr |= tbr_low; |
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511 | return tbr; |
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512 | } |
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513 | |
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514 | static inline void PPC_Set_timebase_register (uint64_t tbr) |
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515 | { |
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516 | uint32_t tbr_low; |
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517 | uint32_t tbr_high; |
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518 | |
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519 | tbr_low = (uint32_t) tbr; |
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520 | tbr_high = (uint32_t) (tbr >> 32); |
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521 | __asm__ volatile( "mtspr 284, %0" : : "r" (tbr_low)); |
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522 | __asm__ volatile( "mtspr 285, %0" : : "r" (tbr_high)); |
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523 | |
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524 | } |
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525 | |
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526 | static inline uint32_t ppc_decrementer_register(void) |
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527 | { |
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528 | uint32_t dec; |
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529 | |
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530 | PPC_Get_decrementer(dec); |
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531 | |
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532 | return dec; |
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533 | } |
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534 | |
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535 | static inline void ppc_set_decrementer_register(uint32_t dec) |
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536 | { |
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537 | PPC_Set_decrementer(dec); |
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538 | } |
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539 | |
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540 | /** |
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541 | * @brief Preprocessor magic for stringification of @a x. |
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542 | */ |
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543 | #define PPC_STRINGOF(x) #x |
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544 | |
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545 | /** |
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546 | * @brief Returns the value of the Special Purpose Register with number @a spr. |
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547 | * |
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548 | * @note This macro uses a GNU C extension. |
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549 | */ |
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550 | #define PPC_SPECIAL_PURPOSE_REGISTER(spr) \ |
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551 | ({ \ |
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552 | uint32_t val; \ |
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553 | __asm__ volatile (\ |
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554 | "mfspr %0, " PPC_STRINGOF(spr) \ |
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555 | : "=r" (val) \ |
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556 | ); \ |
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557 | val;\ |
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558 | } ) |
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559 | |
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560 | /** |
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561 | * @brief Sets the Special Purpose Register with number @a spr to the value in |
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562 | * @a val. |
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563 | */ |
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564 | #define PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val) \ |
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565 | do { \ |
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566 | __asm__ volatile (\ |
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567 | "mtspr " PPC_STRINGOF(spr) ", %0" \ |
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568 | : \ |
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569 | : "r" (val) \ |
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570 | ); \ |
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571 | } while (0) |
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572 | |
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573 | /** |
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574 | * @brief Sets in the Special Purpose Register with number @a spr all bits |
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575 | * which are set in @a bits. |
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576 | * |
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577 | * Interrupts are disabled throughout this operation. |
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578 | */ |
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579 | #define PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS(spr, bits) \ |
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580 | do { \ |
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581 | ISR_Level level; \ |
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582 | uint32_t val; \ |
---|
583 | uint32_t mybits = bits; \ |
---|
584 | _ISR_Disable_without_giant(level); \ |
---|
585 | val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \ |
---|
586 | val |= mybits; \ |
---|
587 | PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \ |
---|
588 | _ISR_Enable_without_giant(level); \ |
---|
589 | } while (0) |
---|
590 | |
---|
591 | /** |
---|
592 | * @brief Sets in the Special Purpose Register with number @a spr all bits |
---|
593 | * which are set in @a bits. The previous register value will be masked with |
---|
594 | * @a mask. |
---|
595 | * |
---|
596 | * Interrupts are disabled throughout this operation. |
---|
597 | */ |
---|
598 | #define PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS_MASKED(spr, bits, mask) \ |
---|
599 | do { \ |
---|
600 | ISR_Level level; \ |
---|
601 | uint32_t val; \ |
---|
602 | uint32_t mybits = bits; \ |
---|
603 | uint32_t mymask = mask; \ |
---|
604 | _ISR_Disable_without_giant(level); \ |
---|
605 | val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \ |
---|
606 | val &= ~mymask; \ |
---|
607 | val |= mybits; \ |
---|
608 | PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \ |
---|
609 | _ISR_Enable_without_giant(level); \ |
---|
610 | } while (0) |
---|
611 | |
---|
612 | /** |
---|
613 | * @brief Clears in the Special Purpose Register with number @a spr all bits |
---|
614 | * which are set in @a bits. |
---|
615 | * |
---|
616 | * Interrupts are disabled throughout this operation. |
---|
617 | */ |
---|
618 | #define PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS(spr, bits) \ |
---|
619 | do { \ |
---|
620 | ISR_Level level; \ |
---|
621 | uint32_t val; \ |
---|
622 | uint32_t mybits = bits; \ |
---|
623 | _ISR_Disable_without_giant(level); \ |
---|
624 | val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \ |
---|
625 | val &= ~mybits; \ |
---|
626 | PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \ |
---|
627 | _ISR_Enable_without_giant(level); \ |
---|
628 | } while (0) |
---|
629 | |
---|
630 | /** |
---|
631 | * @brief Returns the value of the Thread Management Register with number @a tmr. |
---|
632 | * |
---|
633 | * @note This macro uses a GNU C extension. |
---|
634 | */ |
---|
635 | #define PPC_THREAD_MGMT_REGISTER(tmr) \ |
---|
636 | ({ \ |
---|
637 | uint32_t val; \ |
---|
638 | __asm__ volatile (\ |
---|
639 | "mftmr %0, " PPC_STRINGOF(tmr) \ |
---|
640 | : "=r" (val) \ |
---|
641 | ); \ |
---|
642 | val;\ |
---|
643 | } ) |
---|
644 | |
---|
645 | /** |
---|
646 | * @brief Sets the Thread Management Register with number @a tmr to the value in |
---|
647 | * @a val. |
---|
648 | */ |
---|
649 | #define PPC_SET_THREAD_MGMT_REGISTER(tmr, val) \ |
---|
650 | do { \ |
---|
651 | __asm__ volatile (\ |
---|
652 | "mttmr " PPC_STRINGOF(tmr) ", %0" \ |
---|
653 | : \ |
---|
654 | : "r" (val) \ |
---|
655 | ); \ |
---|
656 | } while (0) |
---|
657 | |
---|
658 | /** |
---|
659 | * @brief Returns the value of the Device Control Register with number @a dcr. |
---|
660 | * |
---|
661 | * The PowerPC 4XX family has Device Control Registers. |
---|
662 | * |
---|
663 | * @note This macro uses a GNU C extension. |
---|
664 | */ |
---|
665 | #define PPC_DEVICE_CONTROL_REGISTER(dcr) \ |
---|
666 | ({ \ |
---|
667 | uint32_t val; \ |
---|
668 | __asm__ volatile (\ |
---|
669 | "mfdcr %0, " PPC_STRINGOF(dcr) \ |
---|
670 | : "=r" (val) \ |
---|
671 | ); \ |
---|
672 | val;\ |
---|
673 | } ) |
---|
674 | |
---|
675 | /** |
---|
676 | * @brief Sets the Device Control Register with number @a dcr to the value in |
---|
677 | * @a val. |
---|
678 | * |
---|
679 | * The PowerPC 4XX family has Device Control Registers. |
---|
680 | */ |
---|
681 | #define PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val) \ |
---|
682 | do { \ |
---|
683 | __asm__ volatile (\ |
---|
684 | "mtdcr " PPC_STRINGOF(dcr) ", %0" \ |
---|
685 | : \ |
---|
686 | : "r" (val) \ |
---|
687 | ); \ |
---|
688 | } while (0) |
---|
689 | |
---|
690 | /** |
---|
691 | * @brief Sets in the Device Control Register with number @a dcr all bits |
---|
692 | * which are set in @a bits. |
---|
693 | * |
---|
694 | * Interrupts are disabled throughout this operation. |
---|
695 | */ |
---|
696 | #define PPC_SET_DEVICE_CONTROL_REGISTER_BITS(dcr, bits) \ |
---|
697 | do { \ |
---|
698 | ISR_Level level; \ |
---|
699 | uint32_t val; \ |
---|
700 | uint32_t mybits = bits; \ |
---|
701 | _ISR_Disable_without_giant(level); \ |
---|
702 | val = PPC_DEVICE_CONTROL_REGISTER(dcr); \ |
---|
703 | val |= mybits; \ |
---|
704 | PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val); \ |
---|
705 | _ISR_Enable_without_giant(level); \ |
---|
706 | } while (0) |
---|
707 | |
---|
708 | /** |
---|
709 | * @brief Sets in the Device Control Register with number @a dcr all bits |
---|
710 | * which are set in @a bits. The previous register value will be masked with |
---|
711 | * @a mask. |
---|
712 | * |
---|
713 | * Interrupts are disabled throughout this operation. |
---|
714 | */ |
---|
715 | #define PPC_SET_DEVICE_CONTROL_REGISTER_BITS_MASKED(dcr, bits, mask) \ |
---|
716 | do { \ |
---|
717 | ISR_Level level; \ |
---|
718 | uint32_t val; \ |
---|
719 | uint32_t mybits = bits; \ |
---|
720 | uint32_t mymask = mask; \ |
---|
721 | _ISR_Disable_without_giant(level); \ |
---|
722 | val = PPC_DEVICE_CONTROL_REGISTER(dcr); \ |
---|
723 | val &= ~mymask; \ |
---|
724 | val |= mybits; \ |
---|
725 | PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val); \ |
---|
726 | _ISR_Enable_without_giant(level); \ |
---|
727 | } while (0) |
---|
728 | |
---|
729 | /** |
---|
730 | * @brief Clears in the Device Control Register with number @a dcr all bits |
---|
731 | * which are set in @a bits. |
---|
732 | * |
---|
733 | * Interrupts are disabled throughout this operation. |
---|
734 | */ |
---|
735 | #define PPC_CLEAR_DEVICE_CONTROL_REGISTER_BITS(dcr, bits) \ |
---|
736 | do { \ |
---|
737 | ISR_Level level; \ |
---|
738 | uint32_t val; \ |
---|
739 | uint32_t mybits = bits; \ |
---|
740 | _ISR_Disable_without_giant(level); \ |
---|
741 | val = PPC_DEVICE_CONTROL_REGISTER(dcr); \ |
---|
742 | val &= ~mybits; \ |
---|
743 | PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val); \ |
---|
744 | _ISR_Enable_without_giant(level); \ |
---|
745 | } while (0) |
---|
746 | |
---|
747 | static inline uint32_t ppc_time_base(void) |
---|
748 | { |
---|
749 | uint32_t val; |
---|
750 | |
---|
751 | CPU_Get_timebase_low(val); |
---|
752 | |
---|
753 | return val; |
---|
754 | } |
---|
755 | |
---|
756 | static inline void ppc_set_time_base(uint32_t val) |
---|
757 | { |
---|
758 | PPC_SET_SPECIAL_PURPOSE_REGISTER(TBWL, val); |
---|
759 | } |
---|
760 | |
---|
761 | static inline uint32_t ppc_time_base_upper(void) |
---|
762 | { |
---|
763 | return PPC_SPECIAL_PURPOSE_REGISTER(TBRU); |
---|
764 | } |
---|
765 | |
---|
766 | static inline void ppc_set_time_base_upper(uint32_t val) |
---|
767 | { |
---|
768 | PPC_SET_SPECIAL_PURPOSE_REGISTER(TBWU, val); |
---|
769 | } |
---|
770 | |
---|
771 | static inline uint64_t ppc_time_base_64(void) |
---|
772 | { |
---|
773 | return PPC_Get_timebase_register(); |
---|
774 | } |
---|
775 | |
---|
776 | static inline void ppc_set_time_base_64(uint64_t val) |
---|
777 | { |
---|
778 | PPC_Set_timebase_register(val); |
---|
779 | } |
---|
780 | |
---|
781 | static inline uint32_t ppc_alternate_time_base(void) |
---|
782 | { |
---|
783 | return PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_ATBL); |
---|
784 | } |
---|
785 | |
---|
786 | static inline uint32_t ppc_alternate_time_base_upper(void) |
---|
787 | { |
---|
788 | return PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_ATBU); |
---|
789 | } |
---|
790 | |
---|
791 | static inline uint64_t ppc_alternate_time_base_64(void) |
---|
792 | { |
---|
793 | uint32_t atbl; |
---|
794 | uint32_t atbu_0; |
---|
795 | uint32_t atbu_1; |
---|
796 | |
---|
797 | do { |
---|
798 | atbu_0 = ppc_alternate_time_base_upper(); |
---|
799 | atbl = ppc_alternate_time_base(); |
---|
800 | atbu_1 = ppc_alternate_time_base_upper(); |
---|
801 | } while (atbu_0 != atbu_1); |
---|
802 | |
---|
803 | return (((uint64_t) atbu_1) << 32) | ((uint64_t) atbl); |
---|
804 | } |
---|
805 | |
---|
806 | static inline uint32_t ppc_processor_id(void) |
---|
807 | { |
---|
808 | return PPC_SPECIAL_PURPOSE_REGISTER(BOOKE_PIR); |
---|
809 | } |
---|
810 | |
---|
811 | static inline void ppc_set_processor_id(uint32_t val) |
---|
812 | { |
---|
813 | PPC_SET_SPECIAL_PURPOSE_REGISTER(BOOKE_PIR, val); |
---|
814 | } |
---|
815 | |
---|
816 | static inline uint32_t ppc_fsl_system_version(void) |
---|
817 | { |
---|
818 | return PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_SVR); |
---|
819 | } |
---|
820 | |
---|
821 | static inline uint32_t ppc_fsl_system_version_cid(uint32_t svr) |
---|
822 | { |
---|
823 | return (svr >> 28) & 0xf; |
---|
824 | } |
---|
825 | |
---|
826 | static inline uint32_t ppc_fsl_system_version_sid(uint32_t svr) |
---|
827 | { |
---|
828 | return (svr >> 16) & 0xfff; |
---|
829 | } |
---|
830 | |
---|
831 | static inline uint32_t ppc_fsl_system_version_proc(uint32_t svr) |
---|
832 | { |
---|
833 | return (svr >> 12) & 0xf; |
---|
834 | } |
---|
835 | |
---|
836 | static inline uint32_t ppc_fsl_system_version_mfg(uint32_t svr) |
---|
837 | { |
---|
838 | return (svr >> 8) & 0xf; |
---|
839 | } |
---|
840 | |
---|
841 | static inline uint32_t ppc_fsl_system_version_mjrev(uint32_t svr) |
---|
842 | { |
---|
843 | return (svr >> 4) & 0xf; |
---|
844 | } |
---|
845 | |
---|
846 | static inline uint32_t ppc_fsl_system_version_mnrev(uint32_t svr) |
---|
847 | { |
---|
848 | return (svr >> 0) & 0xf; |
---|
849 | } |
---|
850 | |
---|
851 | void ppc_code_copy(void *dest, const void *src, size_t n); |
---|
852 | |
---|
853 | /* FIXME: Do not use this function */ |
---|
854 | void printBAT(int bat, uint32_t upper, uint32_t lower); |
---|
855 | |
---|
856 | /* FIXME: Do not use this function */ |
---|
857 | void ShowBATS(void); |
---|
858 | |
---|
859 | #endif /* ifndef ASM */ |
---|
860 | |
---|
861 | #if defined(ASM) |
---|
862 | #include <rtems/asm.h> |
---|
863 | |
---|
864 | .macro LA reg, addr |
---|
865 | lis \reg, (\addr)@h |
---|
866 | ori \reg, \reg, (\addr)@l |
---|
867 | .endm |
---|
868 | |
---|
869 | .macro LWI reg, value |
---|
870 | lis \reg, (\value)@h |
---|
871 | ori \reg, \reg, (\value)@l |
---|
872 | .endm |
---|
873 | |
---|
874 | .macro LW reg, addr |
---|
875 | lis \reg, \addr@ha |
---|
876 | lwz \reg, \addr@l(\reg) |
---|
877 | .endm |
---|
878 | |
---|
879 | /* |
---|
880 | * Tests the bits in reg1 against the bits set in mask. A match is indicated |
---|
881 | * by EQ = 0 in CR0. A mismatch is indicated by EQ = 1 in CR0. The register |
---|
882 | * reg2 is used to load the mask. |
---|
883 | */ |
---|
884 | .macro TSTBITS reg1, reg2, mask |
---|
885 | LWI \reg2, \mask |
---|
886 | and \reg1, \reg1, \reg2 |
---|
887 | cmplw \reg1, \reg2 |
---|
888 | .endm |
---|
889 | |
---|
890 | .macro SETBITS reg1, reg2, mask |
---|
891 | LWI \reg2, \mask |
---|
892 | or \reg1, \reg1, \reg2 |
---|
893 | .endm |
---|
894 | |
---|
895 | .macro CLRBITS reg1, reg2, mask |
---|
896 | LWI \reg2, \mask |
---|
897 | andc \reg1, \reg1, \reg2 |
---|
898 | .endm |
---|
899 | |
---|
900 | .macro GLOBAL_FUNCTION name |
---|
901 | .global \name |
---|
902 | .type \name, @function |
---|
903 | \name: |
---|
904 | .endm |
---|
905 | |
---|
906 | /* |
---|
907 | * Obtain interrupt mask |
---|
908 | */ |
---|
909 | .macro GET_INTERRUPT_MASK mask |
---|
910 | lis \mask, _PPC_INTERRUPT_DISABLE_MASK@h |
---|
911 | ori \mask, \mask, _PPC_INTERRUPT_DISABLE_MASK@l |
---|
912 | .endm |
---|
913 | |
---|
914 | /* |
---|
915 | * Disables all asynchronous exeptions (interrupts) which may cause a context |
---|
916 | * switch. |
---|
917 | */ |
---|
918 | .macro INTERRUPT_DISABLE level, mask |
---|
919 | mfmsr \level |
---|
920 | GET_INTERRUPT_MASK mask=\mask |
---|
921 | andc \mask, \level, \mask |
---|
922 | mtmsr \mask |
---|
923 | .endm |
---|
924 | |
---|
925 | /* |
---|
926 | * Restore previous machine state. |
---|
927 | */ |
---|
928 | .macro INTERRUPT_ENABLE level |
---|
929 | mtmsr \level |
---|
930 | .endm |
---|
931 | |
---|
932 | .macro GET_SELF_CPU_CONTROL reg |
---|
933 | #if defined(RTEMS_SMP) |
---|
934 | /* Use Book E Processor ID Register (PIR) */ |
---|
935 | mfspr \reg, 286 |
---|
936 | slwi \reg, \reg, PER_CPU_CONTROL_SIZE_LOG2 |
---|
937 | addis \reg, \reg, _Per_CPU_Information@ha |
---|
938 | addi \reg, \reg, _Per_CPU_Information@l |
---|
939 | #else |
---|
940 | lis \reg, _Per_CPU_Information@h |
---|
941 | ori \reg, \reg, _Per_CPU_Information@l |
---|
942 | #endif |
---|
943 | .endm |
---|
944 | |
---|
945 | #define LINKER_SYMBOL(sym) .extern sym |
---|
946 | |
---|
947 | #endif /* ASM */ |
---|
948 | |
---|
949 | #ifdef __cplusplus |
---|
950 | } |
---|
951 | #endif |
---|
952 | |
---|
953 | #endif /* __LIBCPU_POWERPC_UTILITY_H */ |
---|