1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup powerpc_shared |
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5 | * |
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6 | * @brief General purpose assembler macros, linker command file support and |
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7 | * some inline functions for direct register access. |
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8 | */ |
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9 | |
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10 | /* |
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11 | * Copyright (c) 2008 |
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12 | * Embedded Brains GmbH |
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13 | * Obere Lagerstr. 30 |
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14 | * D-82178 Puchheim |
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15 | * Germany |
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16 | * rtems@embedded-brains.de |
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17 | * |
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18 | * access function for Device Control Registers inspired by "ppc405common.h" |
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19 | * from Michael Hamel ADInstruments May 2008 |
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20 | * |
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21 | * The license and distribution terms for this file may be found in the file |
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22 | * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE. |
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23 | */ |
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24 | |
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25 | /** |
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26 | * @defgroup powerpc_shared Shared PowerPC Code |
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27 | */ |
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28 | |
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29 | #ifndef LIBCPU_POWERPC_UTILITY_H |
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30 | #define LIBCPU_POWERPC_UTILITY_H |
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31 | |
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32 | #ifndef ASM |
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33 | #include <rtems.h> |
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34 | #endif |
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35 | |
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36 | #include <rtems/score/cpu.h> |
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37 | #include <rtems/powerpc/registers.h> |
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38 | #include <rtems/powerpc/powerpc.h> |
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39 | |
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40 | #ifndef ASM |
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41 | |
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42 | #include <rtems/bspIo.h> |
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43 | #include <rtems/system.h> |
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44 | |
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45 | #include <libcpu/cpuIdent.h> |
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46 | |
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47 | #define LINKER_SYMBOL(sym) extern char sym [] |
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48 | |
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49 | /** |
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50 | * @brief Read one byte from @a src. |
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51 | */ |
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52 | static inline uint8_t ppc_read_byte(const volatile void *src) |
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53 | { |
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54 | uint8_t value; |
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55 | |
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56 | asm volatile ( |
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57 | "lbz %0, 0(%1)" |
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58 | : "=r" (value) |
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59 | : "b" (src) |
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60 | ); |
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61 | |
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62 | return value; |
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63 | } |
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64 | |
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65 | /** |
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66 | * @brief Read one half word from @a src. |
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67 | */ |
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68 | static inline uint16_t ppc_read_half_word(const volatile void *src) |
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69 | { |
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70 | uint16_t value; |
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71 | |
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72 | asm volatile ( |
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73 | "lhz %0, 0(%1)" |
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74 | : "=r" (value) |
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75 | : "b" (src) |
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76 | ); |
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77 | |
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78 | return value; |
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79 | } |
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80 | |
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81 | /** |
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82 | * @brief Read one word from @a src. |
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83 | */ |
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84 | static inline uint32_t ppc_read_word(const volatile void *src) |
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85 | { |
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86 | uint32_t value; |
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87 | |
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88 | asm volatile ( |
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89 | "lwz %0, 0(%1)" |
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90 | : "=r" (value) |
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91 | : "b" (src) |
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92 | ); |
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93 | |
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94 | return value; |
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95 | } |
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96 | |
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97 | /** |
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98 | * @brief Write one byte @a value to @a dest. |
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99 | */ |
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100 | static inline void ppc_write_byte(uint8_t value, volatile void *dest) |
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101 | { |
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102 | asm volatile ( |
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103 | "stb %0, 0(%1)" |
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104 | : |
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105 | : "r" (value), "b" (dest) |
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106 | ); |
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107 | } |
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108 | |
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109 | /** |
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110 | * @brief Write one half word @a value to @a dest. |
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111 | */ |
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112 | static inline void ppc_write_half_word(uint16_t value, volatile void *dest) |
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113 | { |
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114 | asm volatile ( |
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115 | "sth %0, 0(%1)" |
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116 | : |
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117 | : "r" (value), "b" (dest) |
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118 | ); |
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119 | } |
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120 | |
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121 | /** |
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122 | * @brief Write one word @a value to @a dest. |
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123 | */ |
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124 | static inline void ppc_write_word(uint32_t value, volatile void *dest) |
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125 | { |
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126 | asm volatile ( |
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127 | "stw %0, 0(%1)" : |
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128 | : "r" (value), "b" (dest) |
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129 | ); |
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130 | } |
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131 | |
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132 | |
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133 | static inline void *ppc_stack_pointer(void) |
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134 | { |
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135 | void *sp; |
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136 | |
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137 | asm volatile ( |
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138 | "mr %0, 1" |
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139 | : "=r" (sp) |
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140 | ); |
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141 | |
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142 | return sp; |
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143 | } |
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144 | |
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145 | static inline void ppc_set_stack_pointer(void *sp) |
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146 | { |
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147 | asm volatile ( |
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148 | "mr 1, %0" |
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149 | : |
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150 | : "r" (sp) |
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151 | ); |
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152 | } |
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153 | |
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154 | static inline void *ppc_link_register(void) |
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155 | { |
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156 | void *lr; |
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157 | |
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158 | asm volatile ( |
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159 | "mflr %0" |
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160 | : "=r" (lr) |
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161 | ); |
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162 | |
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163 | return lr; |
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164 | } |
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165 | |
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166 | static inline void ppc_set_link_register(void *lr) |
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167 | { |
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168 | asm volatile ( |
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169 | "mtlr %0" |
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170 | : |
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171 | : "r" (lr) |
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172 | ); |
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173 | } |
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174 | |
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175 | static inline uint32_t ppc_machine_state_register(void) |
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176 | { |
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177 | uint32_t msr; |
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178 | |
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179 | asm volatile ( |
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180 | "mfmsr %0" |
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181 | : "=r" (msr) |
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182 | ); |
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183 | |
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184 | return msr; |
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185 | } |
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186 | |
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187 | static inline void ppc_set_machine_state_register(uint32_t msr) |
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188 | { |
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189 | asm volatile ( |
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190 | "mtmsr %0" |
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191 | : |
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192 | : "r" (msr) |
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193 | ); |
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194 | } |
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195 | |
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196 | static inline void ppc_synchronize_data(void) |
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197 | { |
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198 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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199 | |
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200 | asm volatile ("sync"); |
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201 | } |
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202 | |
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203 | static inline void ppc_synchronize_instructions(void) |
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204 | { |
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205 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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206 | |
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207 | asm volatile ("isync"); |
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208 | } |
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209 | |
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210 | /** |
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211 | * @brief Enables external exceptions. |
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212 | * |
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213 | * You can use this function to enable the external exceptions and restore the |
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214 | * machine state with ppc_external_exceptions_disable() later. |
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215 | */ |
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216 | static inline uint32_t ppc_external_exceptions_enable(void) |
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217 | { |
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218 | uint32_t current_msr; |
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219 | uint32_t new_msr; |
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220 | |
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221 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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222 | |
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223 | asm volatile ( |
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224 | "mfmsr %0;" |
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225 | "ori %1, %0, 0x8000;" |
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226 | "mtmsr %1" |
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227 | : "=r" (current_msr), "=r" (new_msr) |
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228 | ); |
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229 | |
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230 | return current_msr; |
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231 | } |
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232 | |
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233 | /** |
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234 | * @brief Restores machine state. |
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235 | * |
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236 | * @see ppc_external_exceptions_enable() |
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237 | */ |
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238 | static inline void ppc_external_exceptions_disable(uint32_t msr) |
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239 | { |
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240 | ppc_set_machine_state_register(msr); |
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241 | |
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242 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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243 | } |
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244 | |
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245 | #ifndef ASM |
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246 | /* |
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247 | * Simple spin delay in microsecond units for device drivers. |
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248 | * This is very dependent on the clock speed of the target. |
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249 | */ |
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250 | |
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251 | #if defined(mpx8xx) || defined(mpc860) || defined(mpc821) |
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252 | /* Wonderful bookE doesn't have mftb/mftbu; they only |
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253 | * define the TBRU/TBRL SPRs so we use these. Luckily, |
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254 | * we run in supervisory mode so that should work on |
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255 | * all CPUs. In user mode we'd have a problem... |
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256 | * 2007/11/30, T.S. |
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257 | * |
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258 | * OTOH, PSIM currently lacks support for reading |
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259 | * SPRs 268/269. You need GDB patch sim/2376 to avoid |
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260 | * a crash... |
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261 | * OTOH, the MPC8xx do not allow to read the timebase registers via mfspr. |
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262 | * we NEED a mftb to access the time base. |
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263 | * 2009/10/30 Th. D. |
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264 | */ |
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265 | #define CPU_Get_timebase_low( _value ) \ |
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266 | asm volatile( "mftb %0" : "=r" (_value) ) |
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267 | #else |
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268 | #define CPU_Get_timebase_low( _value ) \ |
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269 | asm volatile( "mfspr %0,268" : "=r" (_value) ) |
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270 | #endif |
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271 | |
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272 | /* Must be provided for rtems_bsp_delay to work */ |
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273 | extern uint32_t bsp_clicks_per_usec; |
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274 | |
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275 | #define rtems_bsp_delay( _microseconds ) \ |
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276 | do { \ |
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277 | uint32_t start, ticks, now; \ |
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278 | CPU_Get_timebase_low( start ) ; \ |
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279 | ticks = (_microseconds) * bsp_clicks_per_usec; \ |
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280 | do \ |
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281 | CPU_Get_timebase_low( now ) ; \ |
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282 | while (now - start < ticks); \ |
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283 | } while (0) |
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284 | |
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285 | #define rtems_bsp_delay_in_bus_cycles( _cycles ) \ |
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286 | do { \ |
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287 | uint32_t start, now; \ |
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288 | CPU_Get_timebase_low( start ); \ |
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289 | do \ |
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290 | CPU_Get_timebase_low( now ); \ |
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291 | while (now - start < (_cycles)); \ |
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292 | } while (0) |
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293 | |
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294 | #endif /* ASM */ |
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295 | |
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296 | #ifndef ASM |
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297 | /* |
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298 | * Routines to access the decrementer register |
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299 | */ |
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300 | |
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301 | #define PPC_Set_decrementer( _clicks ) \ |
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302 | do { \ |
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303 | asm volatile( "mtdec %0" : : "r" ((_clicks)) ); \ |
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304 | } while (0) |
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305 | |
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306 | #define PPC_Get_decrementer( _clicks ) \ |
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307 | asm volatile( "mfdec %0" : "=r" (_clicks) ) |
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308 | |
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309 | #endif /* ASM */ |
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310 | |
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311 | #ifndef ASM |
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312 | /* |
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313 | * Routines to access the time base register |
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314 | */ |
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315 | |
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316 | static inline uint64_t PPC_Get_timebase_register( void ) |
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317 | { |
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318 | uint32_t tbr_low; |
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319 | uint32_t tbr_high; |
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320 | uint32_t tbr_high_old; |
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321 | uint64_t tbr; |
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322 | |
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323 | do { |
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324 | #if defined(mpx8xx) || defined(mpc860) || defined(mpc821) |
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325 | /* See comment above (CPU_Get_timebase_low) */ |
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326 | asm volatile( "mftbu %0" : "=r" (tbr_high_old)); |
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327 | asm volatile( "mftb %0" : "=r" (tbr_low)); |
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328 | asm volatile( "mftbu %0" : "=r" (tbr_high)); |
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329 | #else |
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330 | asm volatile( "mfspr %0, 269" : "=r" (tbr_high_old)); |
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331 | asm volatile( "mfspr %0, 268" : "=r" (tbr_low)); |
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332 | asm volatile( "mfspr %0, 269" : "=r" (tbr_high)); |
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333 | #endif |
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334 | } while ( tbr_high_old != tbr_high ); |
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335 | |
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336 | tbr = tbr_high; |
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337 | tbr <<= 32; |
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338 | tbr |= tbr_low; |
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339 | return tbr; |
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340 | } |
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341 | |
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342 | static inline void PPC_Set_timebase_register (uint64_t tbr) |
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343 | { |
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344 | uint32_t tbr_low; |
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345 | uint32_t tbr_high; |
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346 | |
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347 | tbr_low = (uint32_t) tbr; |
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348 | tbr_high = (uint32_t) (tbr >> 32); |
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349 | asm volatile( "mtspr 284, %0" : : "r" (tbr_low)); |
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350 | asm volatile( "mtspr 285, %0" : : "r" (tbr_high)); |
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351 | |
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352 | } |
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353 | #endif /* ASM */ |
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354 | |
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355 | static inline uint32_t ppc_decrementer_register(void) |
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356 | { |
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357 | uint32_t dec; |
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358 | |
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359 | PPC_Get_decrementer(dec); |
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360 | |
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361 | return dec; |
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362 | } |
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363 | |
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364 | static inline void ppc_set_decrementer_register(uint32_t dec) |
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365 | { |
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366 | PPC_Set_decrementer(dec); |
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367 | } |
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368 | |
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369 | /** |
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370 | * @brief Preprocessor magic for stringification of @a x. |
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371 | */ |
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372 | #define PPC_STRINGOF(x) #x |
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373 | |
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374 | /** |
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375 | * @brief Returns the value of the Special Purpose Register with number @a spr. |
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376 | * |
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377 | * @note This macro uses a GNU C extension. |
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378 | */ |
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379 | #define PPC_SPECIAL_PURPOSE_REGISTER(spr) \ |
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380 | ({ \ |
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381 | uint32_t val; \ |
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382 | asm volatile (\ |
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383 | "mfspr %0, " PPC_STRINGOF(spr) \ |
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384 | : "=r" (val) \ |
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385 | ); \ |
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386 | val;\ |
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387 | } ) |
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388 | |
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389 | /** |
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390 | * @brief Sets the Special Purpose Register with number @a spr to the value in |
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391 | * @a val. |
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392 | */ |
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393 | #define PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val) \ |
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394 | do { \ |
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395 | asm volatile (\ |
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396 | "mtspr " PPC_STRINGOF(spr) ", %0" \ |
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397 | : \ |
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398 | : "r" (val) \ |
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399 | ); \ |
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400 | } while (0) |
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401 | |
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402 | /** |
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403 | * @brief Sets in the Special Purpose Register with number @a spr all bits |
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404 | * which are set in @a bits. |
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405 | * |
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406 | * Interrupts are disabled throughout this operation. |
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407 | */ |
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408 | #define PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS(spr, bits) \ |
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409 | do { \ |
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410 | rtems_interrupt_level level; \ |
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411 | uint32_t val; \ |
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412 | uint32_t mybits = bits; \ |
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413 | rtems_interrupt_disable(level); \ |
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414 | val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \ |
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415 | val |= mybits; \ |
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416 | PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \ |
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417 | rtems_interrupt_enable(level); \ |
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418 | } while (0) |
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419 | |
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420 | /** |
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421 | * @brief Sets in the Special Purpose Register with number @a spr all bits |
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422 | * which are set in @a bits. The previous register value will be masked with |
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423 | * @a mask. |
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424 | * |
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425 | * Interrupts are disabled throughout this operation. |
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426 | */ |
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427 | #define PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS_MASKED(spr, bits, mask) \ |
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428 | do { \ |
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429 | rtems_interrupt_level level; \ |
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430 | uint32_t val; \ |
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431 | uint32_t mybits = bits; \ |
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432 | uint32_t mymask = mask; \ |
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433 | rtems_interrupt_disable(level); \ |
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434 | val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \ |
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435 | val &= ~mymask; \ |
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436 | val |= mybits; \ |
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437 | PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \ |
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438 | rtems_interrupt_enable(level); \ |
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439 | } while (0) |
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440 | |
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441 | /** |
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442 | * @brief Clears in the Special Purpose Register with number @a spr all bits |
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443 | * which are set in @a bits. |
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444 | * |
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445 | * Interrupts are disabled throughout this operation. |
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446 | */ |
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447 | #define PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS(spr, bits) \ |
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448 | do { \ |
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449 | rtems_interrupt_level level; \ |
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450 | uint32_t val; \ |
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451 | uint32_t mybits = bits; \ |
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452 | rtems_interrupt_disable(level); \ |
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453 | val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \ |
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454 | val &= ~mybits; \ |
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455 | PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \ |
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456 | rtems_interrupt_enable(level); \ |
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457 | } while (0) |
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458 | |
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459 | /** |
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460 | * @brief Returns the value of the Device Control Register with number @a dcr. |
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461 | * |
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462 | * The PowerPC 4XX family has Device Control Registers. |
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463 | * |
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464 | * @note This macro uses a GNU C extension. |
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465 | */ |
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466 | #define PPC_DEVICE_CONTROL_REGISTER(dcr) \ |
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467 | ({ \ |
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468 | uint32_t val; \ |
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469 | asm volatile (\ |
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470 | "mfdcr %0, " PPC_STRINGOF(dcr) \ |
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471 | : "=r" (val) \ |
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472 | ); \ |
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473 | val;\ |
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474 | } ) |
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475 | |
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476 | /** |
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477 | * @brief Sets the Device Control Register with number @a dcr to the value in |
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478 | * @a val. |
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479 | * |
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480 | * The PowerPC 4XX family has Device Control Registers. |
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481 | */ |
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482 | #define PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val) \ |
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483 | do { \ |
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484 | asm volatile (\ |
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485 | "mtdcr " PPC_STRINGOF(dcr) ", %0" \ |
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486 | : \ |
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487 | : "r" (val) \ |
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488 | ); \ |
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489 | } while (0) |
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490 | |
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491 | /** |
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492 | * @brief Sets in the Device Control Register with number @a dcr all bits |
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493 | * which are set in @a bits. |
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494 | * |
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495 | * Interrupts are disabled throughout this operation. |
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496 | */ |
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497 | #define PPC_SET_DEVICE_CONTROL_REGISTER_BITS(dcr, bits) \ |
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498 | do { \ |
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499 | rtems_interrupt_level level; \ |
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500 | uint32_t val; \ |
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501 | uint32_t mybits = bits; \ |
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502 | rtems_interrupt_disable(level); \ |
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503 | val = PPC_DEVICE_CONTROL_REGISTER(dcr); \ |
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504 | val |= mybits; \ |
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505 | PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val); \ |
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506 | rtems_interrupt_enable(level); \ |
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507 | } while (0) |
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508 | |
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509 | /** |
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510 | * @brief Sets in the Device Control Register with number @a dcr all bits |
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511 | * which are set in @a bits. The previous register value will be masked with |
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512 | * @a mask. |
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513 | * |
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514 | * Interrupts are disabled throughout this operation. |
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515 | */ |
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516 | #define PPC_SET_DEVICE_CONTROL_REGISTER_BITS_MASKED(dcr, bits, mask) \ |
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517 | do { \ |
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518 | rtems_interrupt_level level; \ |
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519 | uint32_t val; \ |
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520 | uint32_t mybits = bits; \ |
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521 | uint32_t mymask = mask; \ |
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522 | rtems_interrupt_disable(level); \ |
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523 | val = PPC_DEVICE_CONTROL_REGISTER(dcr); \ |
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524 | val &= ~mymask; \ |
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525 | val |= mybits; \ |
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526 | PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val); \ |
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527 | rtems_interrupt_enable(level); \ |
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528 | } while (0) |
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529 | |
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530 | /** |
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531 | * @brief Clears in the Device Control Register with number @a dcr all bits |
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532 | * which are set in @a bits. |
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533 | * |
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534 | * Interrupts are disabled throughout this operation. |
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535 | */ |
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536 | #define PPC_CLEAR_DEVICE_CONTROL_REGISTER_BITS(dcr, bits) \ |
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537 | do { \ |
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538 | rtems_interrupt_level level; \ |
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539 | uint32_t val; \ |
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540 | uint32_t mybits = bits; \ |
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541 | rtems_interrupt_disable(level); \ |
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542 | val = PPC_DEVICE_CONTROL_REGISTER(dcr); \ |
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543 | val &= ~mybits; \ |
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544 | PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val); \ |
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545 | rtems_interrupt_enable(level); \ |
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546 | } while (0) |
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547 | |
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548 | static inline uint32_t ppc_time_base(void) |
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549 | { |
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550 | uint32_t val; |
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551 | |
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552 | CPU_Get_timebase_low(val); |
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553 | |
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554 | return val; |
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555 | } |
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556 | |
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557 | static inline void ppc_set_time_base(uint32_t val) |
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558 | { |
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559 | PPC_SET_SPECIAL_PURPOSE_REGISTER(TBWL, val); |
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560 | } |
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561 | |
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562 | static inline uint32_t ppc_time_base_upper(void) |
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563 | { |
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564 | return PPC_SPECIAL_PURPOSE_REGISTER(TBRU); |
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565 | } |
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566 | |
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567 | static inline void ppc_set_time_base_upper(uint32_t val) |
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568 | { |
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569 | PPC_SET_SPECIAL_PURPOSE_REGISTER(TBWU, val); |
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570 | } |
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571 | |
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572 | static inline uint64_t ppc_time_base_64(void) |
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573 | { |
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574 | return PPC_Get_timebase_register(); |
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575 | } |
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576 | |
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577 | static inline void ppc_set_time_base_64(uint64_t val) |
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578 | { |
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579 | PPC_Set_timebase_register(val); |
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580 | } |
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581 | |
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582 | void ppc_code_copy(void *dest, const void *src, size_t n); |
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583 | |
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584 | #else /* ASM */ |
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585 | |
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586 | #include <rtems/asm.h> |
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587 | |
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588 | .macro LA reg, addr |
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589 | lis \reg, (\addr)@h |
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590 | ori \reg, \reg, (\addr)@l |
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591 | .endm |
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592 | |
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593 | .macro LWI reg, value |
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594 | lis \reg, (\value)@h |
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595 | ori \reg, \reg, (\value)@l |
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596 | .endm |
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597 | |
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598 | .macro LW reg, addr |
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599 | lis \reg, \addr@ha |
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600 | lwz \reg, \addr@l(\reg) |
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601 | .endm |
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602 | |
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603 | /* |
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604 | * Tests the bits in reg1 against the bits set in mask. A match is indicated |
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605 | * by EQ = 0 in CR0. A mismatch is indicated by EQ = 1 in CR0. The register |
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606 | * reg2 is used to load the mask. |
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607 | */ |
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608 | .macro TSTBITS reg1, reg2, mask |
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609 | LWI \reg2, \mask |
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610 | and \reg1, \reg1, \reg2 |
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611 | cmplw \reg1, \reg2 |
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612 | .endm |
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613 | |
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614 | .macro SETBITS reg1, reg2, mask |
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615 | LWI \reg2, \mask |
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616 | or \reg1, \reg1, \reg2 |
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617 | .endm |
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618 | |
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619 | .macro CLRBITS reg1, reg2, mask |
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620 | LWI \reg2, \mask |
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621 | andc \reg1, \reg1, \reg2 |
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622 | .endm |
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623 | |
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624 | .macro GLOBAL_FUNCTION name |
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625 | .global \name |
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626 | .type \name, @function |
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627 | \name: |
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628 | .endm |
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629 | |
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630 | /* |
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631 | * Obtain interrupt mask |
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632 | */ |
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633 | .macro GET_INTERRUPT_MASK mask |
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634 | mfspr \mask, sprg0 |
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635 | .endm |
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636 | |
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637 | /* |
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638 | * Disables all asynchronous exeptions (interrupts) which may cause a context |
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639 | * switch. |
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640 | */ |
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641 | .macro INTERRUPT_DISABLE level, mask |
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642 | mfmsr \level |
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643 | GET_INTERRUPT_MASK mask=\mask |
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644 | andc \mask, \level, \mask |
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645 | mtmsr \mask |
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646 | .endm |
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647 | |
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648 | /* |
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649 | * Restore previous machine state. |
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650 | */ |
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651 | .macro INTERRUPT_ENABLE level |
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652 | mtmsr \level |
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653 | .endm |
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654 | |
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655 | #define LINKER_SYMBOL(sym) .extern sym |
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656 | |
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657 | #endif /* ASM */ |
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658 | |
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659 | #endif /* LIBCPU_POWERPC_UTILITY_H */ |
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