1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup powerpc_shared |
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5 | * |
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6 | * @brief General purpose assembler macros, linker command file support and |
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7 | * some inline functions for direct register access. |
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8 | */ |
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9 | |
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10 | /* |
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11 | * Copyright (c) 2008 |
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12 | * Embedded Brains GmbH |
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13 | * Obere Lagerstr. 30 |
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14 | * D-82178 Puchheim |
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15 | * Germany |
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16 | * rtems@embedded-brains.de |
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17 | * |
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18 | * The license and distribution terms for this file may be found in the file |
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19 | * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE. |
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20 | */ |
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21 | |
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22 | /** |
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23 | * @defgroup powerpc_shared Shared PowerPC Code |
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24 | */ |
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25 | |
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26 | #ifndef LIBCPU_POWERPC_UTILITY_H |
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27 | #define LIBCPU_POWERPC_UTILITY_H |
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28 | |
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29 | #include <rtems/powerpc/registers.h> |
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30 | |
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31 | #ifdef ASM |
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32 | |
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33 | #include <rtems/asm.h> |
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34 | |
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35 | .macro LA reg, addr |
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36 | lis \reg, (\addr)@h |
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37 | ori \reg, \reg, (\addr)@l |
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38 | .endm |
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39 | |
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40 | .macro LWI reg, value |
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41 | lis \reg, (\value)@h |
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42 | ori \reg, \reg, (\value)@l |
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43 | .endm |
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44 | |
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45 | .macro LW reg, addr |
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46 | lis \reg, \addr@ha |
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47 | lwz \reg, \addr@l(\reg) |
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48 | .endm |
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49 | |
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50 | /* |
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51 | * Tests the bits in reg1 against the bits set in mask. A match is indicated |
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52 | * by EQ = 0 in CR0. A mismatch is indicated by EQ = 1 in CR0. The register |
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53 | * reg2 is used to load the mask. |
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54 | */ |
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55 | .macro TSTBITS reg1, reg2, mask |
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56 | LWI \reg2, \mask |
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57 | and \reg1, \reg1, \reg2 |
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58 | cmplw \reg1, \reg2 |
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59 | .endm |
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60 | |
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61 | .macro SETBITS reg1, reg2, mask |
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62 | LWI \reg2, \mask |
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63 | or \reg1, \reg1, \reg2 |
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64 | .endm |
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65 | |
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66 | .macro CLRBITS reg1, reg2, mask |
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67 | LWI \reg2, \mask |
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68 | andc \reg1, \reg1, \reg2 |
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69 | .endm |
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70 | |
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71 | .macro GLOBAL_FUNCTION name |
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72 | .global \name |
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73 | .type \name, @function |
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74 | \name: |
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75 | .endm |
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76 | |
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77 | /* |
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78 | * Disables all asynchronous exeptions (interrupts) which may cause a context |
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79 | * switch. |
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80 | */ |
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81 | .macro INTERRUPT_DISABLE level, mask |
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82 | mfmsr \level |
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83 | mfspr \mask, sprg0 |
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84 | andc \mask, \level, \mask |
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85 | mtmsr \mask |
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86 | .endm |
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87 | |
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88 | /* |
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89 | * Restore previous machine state. |
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90 | */ |
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91 | .macro INTERRUPT_ENABLE level |
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92 | mtmsr \level |
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93 | .endm |
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94 | |
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95 | #define LINKER_SYMBOL( sym) .extern sym |
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96 | |
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97 | #else /* ASM */ |
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98 | |
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99 | #include <stdint.h> |
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100 | |
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101 | #include <rtems/bspIo.h> |
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102 | #include <rtems/system.h> |
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103 | #include <rtems/score/cpu.h> |
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104 | |
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105 | #include <libcpu/cpuIdent.h> |
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106 | |
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107 | #define LINKER_SYMBOL( sym) extern char sym [] |
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108 | |
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109 | /** |
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110 | * @brief Read one byte from @a src. |
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111 | */ |
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112 | static inline uint8_t ppc_read_byte( const volatile void *src) |
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113 | { |
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114 | uint8_t value; |
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115 | |
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116 | asm volatile ( |
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117 | "lbz %0, 0(%1)" |
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118 | : "=r" (value) |
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119 | : "r" (src) |
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120 | ); |
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121 | |
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122 | return value; |
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123 | } |
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124 | |
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125 | /** |
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126 | * @brief Read one half word from @a src. |
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127 | */ |
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128 | static inline uint16_t ppc_read_half_word( const volatile void *src) |
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129 | { |
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130 | uint16_t value; |
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131 | |
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132 | asm volatile ( |
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133 | "lhz %0, 0(%1)" |
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134 | : "=r" (value) |
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135 | : "r" (src) |
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136 | ); |
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137 | |
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138 | return value; |
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139 | } |
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140 | |
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141 | /** |
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142 | * @brief Read one word from @a src. |
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143 | */ |
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144 | static inline uint32_t ppc_read_word( const volatile void *src) |
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145 | { |
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146 | uint32_t value; |
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147 | |
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148 | asm volatile ( |
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149 | "lwz %0, 0(%1)" |
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150 | : "=r" (value) |
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151 | : "r" (src) |
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152 | ); |
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153 | |
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154 | return value; |
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155 | } |
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156 | |
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157 | /** |
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158 | * @brief Write one byte @a value to @a dest. |
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159 | */ |
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160 | static inline void ppc_write_byte( uint8_t value, volatile void *dest) |
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161 | { |
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162 | asm volatile ( |
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163 | "stb %0, 0(%1)" |
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164 | : |
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165 | : "r" (value), "r" (dest) |
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166 | ); |
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167 | } |
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168 | |
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169 | /** |
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170 | * @brief Write one half word @a value to @a dest. |
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171 | */ |
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172 | static inline void ppc_write_half_word( uint16_t value, volatile void *dest) |
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173 | { |
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174 | asm volatile ( |
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175 | "sth %0, 0(%1)" |
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176 | : |
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177 | : "r" (value), "r" (dest) |
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178 | ); |
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179 | } |
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180 | |
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181 | /** |
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182 | * @brief Write one word @a value to @a dest. |
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183 | */ |
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184 | static inline void ppc_write_word( uint32_t value, volatile void *dest) |
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185 | { |
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186 | asm volatile ( |
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187 | "stw %0, 0(%1)" : |
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188 | : "r" (value), "r" (dest) |
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189 | ); |
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190 | } |
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191 | |
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192 | static inline void *ppc_stack_pointer() |
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193 | { |
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194 | void *sp; |
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195 | |
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196 | asm volatile ( |
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197 | "mr %0, 1" |
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198 | : "=r" (sp) |
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199 | ); |
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200 | |
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201 | return sp; |
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202 | } |
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203 | |
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204 | static inline void ppc_set_stack_pointer( void *sp) |
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205 | { |
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206 | asm volatile ( |
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207 | "mr 1, %0" |
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208 | : |
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209 | : "r" (sp) |
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210 | ); |
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211 | } |
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212 | |
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213 | static inline void *ppc_link_register() |
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214 | { |
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215 | void *lr; |
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216 | |
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217 | asm volatile ( |
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218 | "mflr %0" |
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219 | : "=r" (lr) |
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220 | ); |
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221 | |
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222 | return lr; |
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223 | } |
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224 | |
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225 | static inline void ppc_set_link_register( void *lr) |
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226 | { |
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227 | asm volatile ( |
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228 | "mtlr %0" |
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229 | : |
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230 | : "r" (lr) |
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231 | ); |
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232 | } |
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233 | |
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234 | static inline uint32_t ppc_machine_state_register() |
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235 | { |
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236 | uint32_t msr; |
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237 | |
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238 | asm volatile ( |
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239 | "mfmsr %0" |
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240 | : "=r" (msr) |
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241 | ); |
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242 | |
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243 | return msr; |
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244 | } |
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245 | |
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246 | static inline void ppc_set_machine_state_register( uint32_t msr) |
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247 | { |
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248 | asm volatile ( |
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249 | "mtmsr %0" |
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250 | : |
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251 | : "r" (msr) |
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252 | ); |
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253 | } |
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254 | |
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255 | /** |
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256 | * @brief Enables external exceptions. |
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257 | * |
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258 | * You can use this function to enable the external exceptions and restore the |
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259 | * machine state with ppc_external_exceptions_disable() later. |
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260 | */ |
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261 | static inline uint32_t ppc_external_exceptions_enable() |
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262 | { |
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263 | uint32_t current_msr; |
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264 | uint32_t new_msr; |
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265 | |
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266 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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267 | |
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268 | asm volatile ( |
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269 | "mfmsr %0;" |
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270 | "ori %1, %0, 0x8000;" |
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271 | "mtmsr %1" |
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272 | : "=r" (current_msr), "=r" (new_msr) |
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273 | ); |
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274 | |
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275 | return current_msr; |
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276 | } |
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277 | |
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278 | /** |
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279 | * @brief Restores machine state. |
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280 | * |
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281 | * @see ppc_external_exceptions_enable() |
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282 | */ |
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283 | static inline void ppc_external_exceptions_disable( uint32_t msr) |
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284 | { |
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285 | ppc_set_machine_state_register( msr); |
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286 | |
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287 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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288 | } |
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289 | |
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290 | static inline uint32_t ppc_decrementer_register() |
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291 | { |
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292 | uint32_t dec; |
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293 | |
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294 | PPC_Get_decrementer( dec); |
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295 | |
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296 | return dec; |
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297 | } |
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298 | |
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299 | static inline void ppc_set_decrementer_register( uint32_t dec) |
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300 | { |
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301 | PPC_Set_decrementer( dec); |
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302 | } |
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303 | |
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304 | /* Do not use the following macros. Use the inline functions instead. */ |
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305 | |
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306 | #define PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER( spr) \ |
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307 | uint32_t val; \ |
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308 | asm volatile ( \ |
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309 | "mfspr %0, " #spr \ |
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310 | : "=r" (val) \ |
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311 | ); \ |
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312 | return val; |
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313 | |
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314 | #define PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( spr) \ |
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315 | PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER( spr) |
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316 | |
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317 | #define PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER( spr, val) \ |
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318 | asm volatile ( \ |
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319 | "mtspr " #spr ", %0" \ |
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320 | : \ |
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321 | : "r" (val) \ |
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322 | ); |
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323 | |
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324 | #define PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( spr, val) \ |
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325 | PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER( spr, val) |
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326 | |
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327 | static inline uint32_t ppc_special_purpose_register_0() |
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328 | { |
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329 | PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG0); |
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330 | } |
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331 | |
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332 | static inline void ppc_set_special_purpose_register_0( uint32_t val) |
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333 | { |
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334 | PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG0, val); |
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335 | } |
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336 | |
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337 | static inline uint32_t ppc_special_purpose_register_1() |
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338 | { |
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339 | PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG1); |
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340 | } |
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341 | |
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342 | static inline void ppc_set_special_purpose_register_1( uint32_t val) |
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343 | { |
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344 | PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG1, val); |
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345 | } |
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346 | |
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347 | static inline uint32_t ppc_special_purpose_register_2() |
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348 | { |
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349 | PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG2); |
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350 | } |
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351 | |
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352 | static inline void ppc_set_special_purpose_register_2( uint32_t val) |
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353 | { |
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354 | PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG2, val); |
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355 | } |
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356 | |
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357 | static inline uint32_t ppc_special_purpose_register_3() |
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358 | { |
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359 | PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG3); |
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360 | } |
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361 | |
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362 | static inline void ppc_set_special_purpose_register_3( uint32_t val) |
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363 | { |
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364 | PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG3, val); |
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365 | } |
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366 | |
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367 | static inline uint32_t ppc_special_purpose_register_4() |
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368 | { |
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369 | PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG4); |
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370 | } |
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371 | |
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372 | static inline void ppc_set_special_purpose_register_4( uint32_t val) |
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373 | { |
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374 | PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG4, val); |
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375 | } |
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376 | |
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377 | static inline uint32_t ppc_special_purpose_register_5() |
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378 | { |
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379 | PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG5); |
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380 | } |
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381 | |
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382 | static inline void ppc_set_special_purpose_register_5( uint32_t val) |
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383 | { |
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384 | PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG5, val); |
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385 | } |
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386 | |
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387 | static inline uint32_t ppc_special_purpose_register_6() |
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388 | { |
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389 | PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG6); |
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390 | } |
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391 | |
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392 | static inline void ppc_set_special_purpose_register_6( uint32_t val) |
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393 | { |
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394 | PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG6, val); |
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395 | } |
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396 | |
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397 | static inline uint32_t ppc_special_purpose_register_7() |
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398 | { |
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399 | PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG7); |
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400 | } |
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401 | |
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402 | static inline void ppc_set_special_purpose_register_7( uint32_t val) |
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403 | { |
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404 | PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG7, val); |
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405 | } |
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406 | |
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407 | static inline uint32_t ppc_user_special_purpose_register_0() |
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408 | { |
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409 | PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( USPRG0); |
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410 | } |
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411 | |
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412 | static inline void ppc_set_user_special_purpose_register_0( uint32_t val) |
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413 | { |
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414 | PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( USPRG0, val); |
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415 | } |
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416 | |
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417 | static inline uint32_t ppc_timer_control_register() |
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418 | { |
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419 | PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_TCR); |
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420 | } |
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421 | |
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422 | static inline void ppc_set_timer_control_register( uint32_t val) |
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423 | { |
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424 | PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_TCR, val); |
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425 | } |
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426 | |
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427 | static inline uint32_t ppc_timer_status_register() |
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428 | { |
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429 | PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_TSR); |
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430 | } |
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431 | |
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432 | static inline void ppc_set_timer_status_register( uint32_t val) |
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433 | { |
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434 | PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_TSR, val); |
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435 | } |
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436 | |
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437 | static inline uint32_t ppc_decrementer_auto_reload_register() |
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438 | { |
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439 | PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_DECAR); |
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440 | } |
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441 | |
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442 | static inline void ppc_set_decrementer_auto_reload_register( uint32_t val) |
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443 | { |
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444 | PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_DECAR, val); |
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445 | } |
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446 | |
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447 | static inline uint32_t ppc_hardware_implementation_dependent_register_0() |
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448 | { |
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449 | PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( HID0); |
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450 | } |
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451 | |
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452 | static inline void ppc_set_hardware_implementation_dependent_register_0( uint32_t val) |
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453 | { |
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454 | PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( HID0, val); |
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455 | } |
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456 | |
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457 | static inline uint32_t ppc_hardware_implementation_dependent_register_1() |
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458 | { |
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459 | PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( HID1); |
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460 | } |
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461 | |
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462 | static inline void ppc_set_hardware_implementation_dependent_register_1( uint32_t val) |
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463 | { |
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464 | PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( HID1, val); |
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465 | } |
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466 | |
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467 | static inline uint32_t ppc_time_base() |
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468 | { |
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469 | uint32_t val; |
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470 | |
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471 | CPU_Get_timebase_low( val); |
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472 | |
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473 | return val; |
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474 | } |
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475 | |
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476 | static inline void ppc_set_time_base( uint32_t val) |
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477 | { |
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478 | PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( TBWL, val); |
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479 | } |
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480 | |
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481 | static inline uint32_t ppc_time_base_upper() |
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482 | { |
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483 | PPC_INTERNAL_MACRO_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( TBRU); |
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484 | } |
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485 | |
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486 | static inline void ppc_set_time_base_upper( uint32_t val) |
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487 | { |
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488 | PPC_INTERNAL_MACRO_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( TBWU, val); |
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489 | } |
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490 | |
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491 | static inline uint64_t ppc_time_base_64() |
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492 | { |
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493 | return PPC_Get_timebase_register(); |
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494 | } |
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495 | |
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496 | static inline void ppc_set_time_base_64( uint64_t val) |
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497 | { |
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498 | PPC_Set_timebase_register( val); |
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499 | } |
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500 | |
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501 | #endif /* ASM */ |
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502 | |
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503 | #endif /* LIBCPU_POWERPC_UTILITY_H */ |
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