source: rtems/c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h @ 03bed2db

4.104.114.95
Last change on this file since 03bed2db was 03bed2db, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on 07/10/08 at 06:15:58

Includes standard header files,
provides common assembler macros and inline functions for low-level
code.

  • Property mode set to 100644
File size: 9.0 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup powerpc_shared
5 *
6 * @brief General purpose assembler macros, linker command file support and
7 * some inline functions for direct register access.
8 */
9
10/*
11 * Copyright (c) 2008
12 * Embedded Brains GmbH
13 * Obere Lagerstr. 30
14 * D-82178 Puchheim
15 * Germany
16 * rtems@embedded-brains.de
17 *
18 * The license and distribution terms for this file may be found in the file
19 * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
20 */
21
22/**
23 * @defgroup powerpc_shared Shared PowerPC Code
24 */
25
26#ifndef LIBCPU_POWERPC_UTILITY_H
27#define LIBCPU_POWERPC_UTILITY_H
28
29#include <rtems/powerpc/registers.h>
30
31#ifdef ASM
32
33#include <rtems/asm.h>
34
35.macro LA reg, addr
36        lis \reg, (\addr)@h
37        ori \reg, \reg, (\addr)@l
38.endm
39
40.macro LWI reg, value
41        lis \reg, (\value)@h
42        ori \reg, \reg, (\value)@l
43.endm
44
45.macro LW reg, addr
46        lis \reg, \addr@ha
47        lwz \reg, \addr@l(\reg)
48.endm
49
50/*
51 * Tests the bits in reg1 against the bits set in mask.  A match is indicated
52 * by EQ = 0 in CR0.  A mismatch is indicated by EQ = 1 in CR0.  The register
53 * reg2 is used to load the mask.
54 */
55.macro  TSTBITS reg1, reg2, mask
56        LWI     \reg2, \mask
57        and     \reg1, \reg1, \reg2
58        cmplw   \reg1, \reg2
59.endm   
60       
61.macro  SETBITS reg1, reg2, mask
62        LWI     \reg2, \mask
63        or      \reg1, \reg1, \reg2
64.endm
65
66.macro  CLRBITS reg1, reg2, mask
67        LWI     \reg2, \mask
68        andc    \reg1, \reg1, \reg2
69.endm
70
71.macro GLOBAL_FUNCTION name
72        .global \name
73        .type \name, @function
74\name:
75.endm
76
77/*
78 * Disables all asynchronous exeptions (interrupts) which may cause a context
79 * switch.
80 */
81.macro INTERRUPT_DISABLE level, mask
82        mfmsr   \level
83        mfspr   \mask, sprg0
84        andc    \mask, \level, \mask
85        mtmsr   \mask
86.endm
87
88/*
89 * Restore previous machine state.
90 */
91.macro INTERRUPT_ENABLE level
92        mtmsr   \level
93.endm
94
95#define LINKER_SYMBOL( sym) .extern sym
96
97#else /* ASM */
98
99#include <stdint.h>
100
101#include <rtems/bspIo.h>
102#include <rtems/system.h>
103#include <rtems/score/cpu.h>
104
105#include <libcpu/cpuIdent.h>
106
107#define LINKER_SYMBOL( sym) extern char sym []
108
109/**
110 * @brief Read one byte from @a src.
111 */
112static inline uint8_t ppc_read_byte( const volatile void *src)
113{
114        uint8_t value;
115
116        asm volatile (
117                "lbz %0, 0(%1)"
118                : "=r" (value)
119                : "r" (src)
120        );
121
122        return value;
123}
124
125/**
126 * @brief Read one half word from @a src.
127 */
128static inline uint16_t ppc_read_half_word( const volatile void *src)
129{
130        uint16_t value;
131
132        asm volatile (
133                "lhz %0, 0(%1)"
134                : "=r" (value)
135                : "r" (src)
136        );
137
138        return value;
139}
140
141/**
142 * @brief Read one word from @a src.
143 */
144static inline uint32_t ppc_read_word( const volatile void *src)
145{
146        uint32_t value;
147
148        asm volatile (
149                "lwz %0, 0(%1)"
150                : "=r" (value)
151                : "r" (src)
152        );
153
154        return value;
155}
156
157/**
158 * @brief Write one byte @a value to @a dest.
159 */
160static inline void ppc_write_byte( uint8_t value, volatile void *dest)
161{
162        asm volatile (
163                "stb %0, 0(%1)"
164                :
165                : "r" (value), "r" (dest)
166        );
167}
168
169/**
170 * @brief Write one half word @a value to @a dest.
171 */
172static inline void ppc_write_half_word( uint16_t value, volatile void *dest)
173{
174        asm volatile (
175                "sth %0, 0(%1)"
176                :
177                : "r" (value), "r" (dest)
178        );
179}
180
181/**
182 * @brief Write one word @a value to @a dest.
183 */
184static inline void ppc_write_word( uint32_t value, volatile void *dest)
185{
186        asm volatile (
187                "stw %0, 0(%1)" :
188                : "r" (value), "r" (dest)
189        );
190}
191
192static inline void *ppc_stack_pointer()
193{
194        void *sp;
195
196        asm volatile (
197                "mr %0, 1"
198                : "=r" (sp)
199        );
200
201        return sp;
202}
203
204static inline void ppc_set_stack_pointer( void *sp)
205{
206        asm volatile (
207                "mr 1, %0"
208                :
209                : "r" (sp)
210        );
211}
212
213static inline void *ppc_link_register()
214{
215        void *lr;
216
217        asm volatile (
218                "mflr %0"
219                : "=r" (lr)
220        );
221
222        return lr;
223}
224
225static inline void ppc_set_link_register( void *lr)
226{
227        asm volatile (
228                "mtlr %0"
229                :
230                : "r" (lr)
231        );
232}
233
234static inline uint32_t ppc_machine_state_register()
235{
236        uint32_t msr;
237
238        asm volatile (
239                "mfmsr %0"
240                : "=r" (msr)
241        );
242
243        return msr;
244}
245
246static inline void ppc_set_machine_state_register( uint32_t msr)
247{
248        asm volatile (
249                "mtmsr %0"
250                :
251                : "r" (msr)
252        );
253}
254
255static inline uint32_t ppc_external_exceptions_enable()
256{
257        uint32_t current_msr;
258        uint32_t new_msr;
259
260        RTEMS_COMPILER_MEMORY_BARRIER();
261
262        asm volatile (
263                "mfmsr %0;"
264                "ori %1, %0, 0x8000;"
265                "mtmsr %1"
266                : "=r" (current_msr), "=r" (new_msr)
267        );
268
269        return current_msr;
270}
271
272static inline void ppc_external_exceptions_disable( uint32_t msr)
273{
274        ppc_set_machine_state_register( msr);
275
276        RTEMS_COMPILER_MEMORY_BARRIER();
277}
278
279static inline uint32_t ppc_decrementer_register()
280{
281        uint32_t dec;
282
283        PPC_Get_decrementer( dec);
284
285        return dec;
286}
287
288static inline void ppc_set_decrementer_register( uint32_t dec)
289{
290        PPC_Set_decrementer( dec);
291}
292
293#define PPC_RETURN_SPECIAL_PURPOSE_REGISTER( spr) \
294        uint32_t val; \
295        asm volatile ( \
296                "mfspr %0, " #spr \
297                : "=r" (val) \
298        ); \
299        return val;
300
301#define PPC_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( spr) \
302        PPC_RETURN_SPECIAL_PURPOSE_REGISTER( spr)
303
304#define PPC_SET_SPECIAL_PURPOSE_REGISTER( spr, val) \
305        asm volatile ( \
306                "mtspr " #spr ", %0" \
307                : \
308                : "r" (val) \
309        );
310
311#define PPC_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( spr, val) \
312        PPC_SET_SPECIAL_PURPOSE_REGISTER( spr, val)
313
314static inline uint32_t ppc_special_purpose_register_0()
315{
316        PPC_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG0);
317}
318
319static inline void ppc_set_special_purpose_register_0( uint32_t val)
320{
321        PPC_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG0, val);
322}
323
324static inline uint32_t ppc_special_purpose_register_1()
325{
326        PPC_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG1);
327}
328
329static inline void ppc_set_special_purpose_register_1( uint32_t val)
330{
331        PPC_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG1, val);
332}
333
334static inline uint32_t ppc_special_purpose_register_2()
335{
336        PPC_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG2);
337}
338
339static inline void ppc_set_special_purpose_register_2( uint32_t val)
340{
341        PPC_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG2, val);
342}
343
344static inline uint32_t ppc_special_purpose_register_3()
345{
346        PPC_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG3);
347}
348
349static inline void ppc_set_special_purpose_register_3( uint32_t val)
350{
351        PPC_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG3, val);
352}
353
354static inline uint32_t ppc_special_purpose_register_4()
355{
356        PPC_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG4);
357}
358
359static inline void ppc_set_special_purpose_register_4( uint32_t val)
360{
361        PPC_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG4, val);
362}
363
364static inline uint32_t ppc_special_purpose_register_5()
365{
366        PPC_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG5);
367}
368
369static inline void ppc_set_special_purpose_register_5( uint32_t val)
370{
371        PPC_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG5, val);
372}
373
374static inline uint32_t ppc_special_purpose_register_6()
375{
376        PPC_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG6);
377}
378
379static inline void ppc_set_special_purpose_register_6( uint32_t val)
380{
381        PPC_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG6, val);
382}
383
384static inline uint32_t ppc_special_purpose_register_7()
385{
386        PPC_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG7);
387}
388
389static inline void ppc_set_special_purpose_register_7( uint32_t val)
390{
391        PPC_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( SPRG7, val);
392}
393
394static inline uint32_t ppc_user_special_purpose_register_0()
395{
396        PPC_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( USPRG0);
397}
398
399static inline void ppc_set_user_special_purpose_register_0( uint32_t val)
400{
401        PPC_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( USPRG0, val);
402}
403
404static inline uint32_t ppc_timer_control_register()
405{
406        PPC_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_TCR);
407}
408
409static inline void ppc_set_timer_control_register( uint32_t val)
410{
411        PPC_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_TCR, val);
412}
413
414static inline uint32_t ppc_timer_status_register()
415{
416        PPC_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_TSR);
417}
418
419static inline void ppc_set_timer_status_register( uint32_t val)
420{
421        PPC_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_TSR, val);
422}
423
424static inline uint32_t ppc_decrementer_auto_reload_register()
425{
426        PPC_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_DECAR);
427}
428
429static inline void ppc_set_decrementer_auto_reload_register( uint32_t val)
430{
431        PPC_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( BOOKE_DECAR, val);
432}
433
434static inline uint32_t ppc_hardware_implementation_dependent_register_0()
435{
436        PPC_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( HID0);
437}
438
439static inline void ppc_set_hardware_implementation_dependent_register_0( uint32_t val)
440{
441        PPC_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( HID0, val);
442}
443
444static inline uint32_t ppc_hardware_implementation_dependent_register_1()
445{
446        PPC_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( HID1);
447}
448
449static inline void ppc_set_hardware_implementation_dependent_register_1( uint32_t val)
450{
451        PPC_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( HID1, val);
452}
453
454static inline uint32_t ppc_time_base()
455{
456        uint32_t val;
457
458        CPU_Get_timebase_low( val);
459
460        return val;
461}
462
463static inline void ppc_set_time_base( uint32_t val)
464{
465        PPC_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( TBWL, val);
466}
467
468static inline uint32_t ppc_time_base_upper()
469{
470        PPC_RETURN_SPECIAL_PURPOSE_REGISTER_EXPAND( TBRU);
471}
472
473static inline void ppc_set_time_base_upper( uint32_t val)
474{
475        PPC_SET_SPECIAL_PURPOSE_REGISTER_EXPAND( TBWU, val);
476}
477
478static inline uint64_t ppc_time_base_64()
479{
480        return PPC_Get_timebase_register();
481}
482
483static inline void ppc_set_time_base_64( uint64_t val)
484{
485        PPC_Set_timebase_register( val);
486}
487
488#endif /* ASM */
489
490#endif /* LIBCPU_POWERPC_UTILITY_H */
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