[03bed2db] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @ingroup powerpc_shared |
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| 5 | * |
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| 6 | * @brief General purpose assembler macros, linker command file support and |
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| 7 | * some inline functions for direct register access. |
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| 8 | */ |
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| 9 | |
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| 10 | /* |
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| 11 | * Copyright (c) 2008 |
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| 12 | * Embedded Brains GmbH |
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| 13 | * Obere Lagerstr. 30 |
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| 14 | * D-82178 Puchheim |
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| 15 | * Germany |
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| 16 | * rtems@embedded-brains.de |
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[3c6fe2e] | 17 | * |
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| 18 | * access function for Device Control Registers inspired by "ppc405common.h" |
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| 19 | * from Michael Hamel ADInstruments May 2008 |
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[03bed2db] | 20 | * |
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| 21 | * The license and distribution terms for this file may be found in the file |
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| 22 | * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE. |
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| 23 | */ |
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| 24 | |
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| 25 | /** |
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| 26 | * @defgroup powerpc_shared Shared PowerPC Code |
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| 27 | */ |
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| 28 | |
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| 29 | #ifndef LIBCPU_POWERPC_UTILITY_H |
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| 30 | #define LIBCPU_POWERPC_UTILITY_H |
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| 31 | |
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| 32 | #include <rtems/powerpc/registers.h> |
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| 33 | |
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[574fb67] | 34 | #ifndef ASM |
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[03bed2db] | 35 | |
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| 36 | #include <stdint.h> |
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| 37 | |
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| 38 | #include <rtems/bspIo.h> |
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| 39 | #include <rtems/system.h> |
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| 40 | #include <rtems/score/cpu.h> |
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| 41 | |
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| 42 | #include <libcpu/cpuIdent.h> |
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| 43 | |
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| 44 | #define LINKER_SYMBOL( sym) extern char sym [] |
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| 45 | |
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| 46 | /** |
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| 47 | * @brief Read one byte from @a src. |
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| 48 | */ |
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| 49 | static inline uint8_t ppc_read_byte( const volatile void *src) |
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| 50 | { |
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| 51 | uint8_t value; |
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| 52 | |
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| 53 | asm volatile ( |
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| 54 | "lbz %0, 0(%1)" |
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| 55 | : "=r" (value) |
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[602aee20] | 56 | : "b" (src) |
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[03bed2db] | 57 | ); |
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| 58 | |
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| 59 | return value; |
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| 60 | } |
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| 61 | |
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| 62 | /** |
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| 63 | * @brief Read one half word from @a src. |
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| 64 | */ |
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| 65 | static inline uint16_t ppc_read_half_word( const volatile void *src) |
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| 66 | { |
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| 67 | uint16_t value; |
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| 68 | |
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| 69 | asm volatile ( |
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| 70 | "lhz %0, 0(%1)" |
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| 71 | : "=r" (value) |
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[602aee20] | 72 | : "b" (src) |
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[03bed2db] | 73 | ); |
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| 74 | |
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| 75 | return value; |
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| 76 | } |
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| 77 | |
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| 78 | /** |
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| 79 | * @brief Read one word from @a src. |
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| 80 | */ |
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| 81 | static inline uint32_t ppc_read_word( const volatile void *src) |
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| 82 | { |
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| 83 | uint32_t value; |
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| 84 | |
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| 85 | asm volatile ( |
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| 86 | "lwz %0, 0(%1)" |
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| 87 | : "=r" (value) |
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[602aee20] | 88 | : "b" (src) |
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[03bed2db] | 89 | ); |
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| 90 | |
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| 91 | return value; |
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| 92 | } |
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| 93 | |
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| 94 | /** |
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| 95 | * @brief Write one byte @a value to @a dest. |
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| 96 | */ |
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| 97 | static inline void ppc_write_byte( uint8_t value, volatile void *dest) |
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| 98 | { |
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| 99 | asm volatile ( |
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| 100 | "stb %0, 0(%1)" |
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| 101 | : |
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[602aee20] | 102 | : "r" (value), "b" (dest) |
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[03bed2db] | 103 | ); |
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| 104 | } |
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| 105 | |
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| 106 | /** |
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| 107 | * @brief Write one half word @a value to @a dest. |
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| 108 | */ |
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| 109 | static inline void ppc_write_half_word( uint16_t value, volatile void *dest) |
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| 110 | { |
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| 111 | asm volatile ( |
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| 112 | "sth %0, 0(%1)" |
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| 113 | : |
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[602aee20] | 114 | : "r" (value), "b" (dest) |
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[03bed2db] | 115 | ); |
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| 116 | } |
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| 117 | |
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| 118 | /** |
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| 119 | * @brief Write one word @a value to @a dest. |
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| 120 | */ |
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| 121 | static inline void ppc_write_word( uint32_t value, volatile void *dest) |
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| 122 | { |
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| 123 | asm volatile ( |
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| 124 | "stw %0, 0(%1)" : |
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[602aee20] | 125 | : "r" (value), "b" (dest) |
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[03bed2db] | 126 | ); |
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| 127 | } |
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| 128 | |
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[3c6fe2e] | 129 | |
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[03bed2db] | 130 | static inline void *ppc_stack_pointer() |
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| 131 | { |
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| 132 | void *sp; |
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| 133 | |
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| 134 | asm volatile ( |
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| 135 | "mr %0, 1" |
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| 136 | : "=r" (sp) |
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| 137 | ); |
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| 138 | |
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| 139 | return sp; |
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| 140 | } |
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| 141 | |
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| 142 | static inline void ppc_set_stack_pointer( void *sp) |
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| 143 | { |
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| 144 | asm volatile ( |
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| 145 | "mr 1, %0" |
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| 146 | : |
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| 147 | : "r" (sp) |
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| 148 | ); |
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| 149 | } |
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| 150 | |
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| 151 | static inline void *ppc_link_register() |
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| 152 | { |
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| 153 | void *lr; |
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| 154 | |
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| 155 | asm volatile ( |
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| 156 | "mflr %0" |
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| 157 | : "=r" (lr) |
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| 158 | ); |
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| 159 | |
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| 160 | return lr; |
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| 161 | } |
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| 162 | |
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| 163 | static inline void ppc_set_link_register( void *lr) |
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| 164 | { |
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| 165 | asm volatile ( |
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| 166 | "mtlr %0" |
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| 167 | : |
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| 168 | : "r" (lr) |
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| 169 | ); |
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| 170 | } |
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| 171 | |
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| 172 | static inline uint32_t ppc_machine_state_register() |
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| 173 | { |
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| 174 | uint32_t msr; |
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| 175 | |
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| 176 | asm volatile ( |
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| 177 | "mfmsr %0" |
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| 178 | : "=r" (msr) |
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| 179 | ); |
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| 180 | |
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| 181 | return msr; |
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| 182 | } |
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| 183 | |
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| 184 | static inline void ppc_set_machine_state_register( uint32_t msr) |
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| 185 | { |
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| 186 | asm volatile ( |
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| 187 | "mtmsr %0" |
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| 188 | : |
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| 189 | : "r" (msr) |
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| 190 | ); |
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| 191 | } |
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| 192 | |
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[31282767] | 193 | /** |
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| 194 | * @brief Enables external exceptions. |
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| 195 | * |
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| 196 | * You can use this function to enable the external exceptions and restore the |
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| 197 | * machine state with ppc_external_exceptions_disable() later. |
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| 198 | */ |
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[03bed2db] | 199 | static inline uint32_t ppc_external_exceptions_enable() |
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| 200 | { |
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| 201 | uint32_t current_msr; |
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| 202 | uint32_t new_msr; |
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| 203 | |
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| 204 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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| 205 | |
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| 206 | asm volatile ( |
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| 207 | "mfmsr %0;" |
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| 208 | "ori %1, %0, 0x8000;" |
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| 209 | "mtmsr %1" |
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| 210 | : "=r" (current_msr), "=r" (new_msr) |
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| 211 | ); |
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| 212 | |
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| 213 | return current_msr; |
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| 214 | } |
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| 215 | |
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[31282767] | 216 | /** |
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| 217 | * @brief Restores machine state. |
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| 218 | * |
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| 219 | * @see ppc_external_exceptions_enable() |
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| 220 | */ |
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[03bed2db] | 221 | static inline void ppc_external_exceptions_disable( uint32_t msr) |
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| 222 | { |
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| 223 | ppc_set_machine_state_register( msr); |
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| 224 | |
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| 225 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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| 226 | } |
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| 227 | |
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| 228 | static inline uint32_t ppc_decrementer_register() |
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| 229 | { |
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| 230 | uint32_t dec; |
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| 231 | |
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| 232 | PPC_Get_decrementer( dec); |
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| 233 | |
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| 234 | return dec; |
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| 235 | } |
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| 236 | |
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| 237 | static inline void ppc_set_decrementer_register( uint32_t dec) |
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| 238 | { |
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| 239 | PPC_Set_decrementer( dec); |
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| 240 | } |
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| 241 | |
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[d3c32136] | 242 | /** |
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| 243 | * @brief Preprocessor magic for stringification of @a x. |
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[3c6fe2e] | 244 | */ |
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[d3c32136] | 245 | #define PPC_STRINGOF( x) #x |
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[03bed2db] | 246 | |
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[d3c32136] | 247 | /** |
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| 248 | * @brief Returns the value of the Special Purpose Register with number @a spr. |
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| 249 | * |
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| 250 | * @note This macro uses a GNU C extension. |
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| 251 | */ |
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| 252 | #define PPC_SPECIAL_PURPOSE_REGISTER( spr) \ |
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| 253 | ( { \ |
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| 254 | uint32_t val; \ |
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| 255 | asm volatile ( \ |
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| 256 | "mfspr %0, " PPC_STRINGOF( spr) \ |
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| 257 | : "=r" (val) \ |
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| 258 | ); \ |
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| 259 | val;\ |
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| 260 | } ) |
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[03bed2db] | 261 | |
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[d3c32136] | 262 | /** |
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| 263 | * @brief Sets the Special Purpose Register with number @a spr to the value in |
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| 264 | * @a val. |
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| 265 | */ |
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| 266 | #define PPC_SET_SPECIAL_PURPOSE_REGISTER( spr, val) \ |
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| 267 | do { \ |
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| 268 | asm volatile ( \ |
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| 269 | "mtspr " PPC_STRINGOF( spr) ", %0" \ |
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| 270 | : \ |
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| 271 | : "r" (val) \ |
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| 272 | ); \ |
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| 273 | } while (0) |
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[03bed2db] | 274 | |
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[d3c32136] | 275 | /** |
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| 276 | * @brief Sets in the Special Purpose Register with number @a spr all bits |
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| 277 | * which are set in @a bits. |
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| 278 | * |
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| 279 | * Interrupts are disabled throughout this operation. |
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| 280 | */ |
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| 281 | #define PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( spr, bits) \ |
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| 282 | do { \ |
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| 283 | rtems_interrupt_level level; \ |
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| 284 | uint32_t val; \ |
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[a78df7b] | 285 | uint32_t mybits = bits; \ |
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[d3c32136] | 286 | rtems_interrupt_disable( level); \ |
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| 287 | val = PPC_SPECIAL_PURPOSE_REGISTER( spr); \ |
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[a78df7b] | 288 | val |= mybits; \ |
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[d3c32136] | 289 | PPC_SET_SPECIAL_PURPOSE_REGISTER( spr, val); \ |
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| 290 | rtems_interrupt_enable( level); \ |
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| 291 | } while (0) |
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[03bed2db] | 292 | |
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[d3c32136] | 293 | /** |
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| 294 | * @brief Sets in the Special Purpose Register with number @a spr all bits |
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| 295 | * which are set in @a bits. The previous register value will be masked with |
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| 296 | * @a mask. |
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| 297 | * |
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| 298 | * Interrupts are disabled throughout this operation. |
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| 299 | */ |
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| 300 | #define PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS_MASKED( spr, bits, mask) \ |
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| 301 | do { \ |
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| 302 | rtems_interrupt_level level; \ |
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| 303 | uint32_t val; \ |
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[a78df7b] | 304 | uint32_t mybits = bits; \ |
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| 305 | uint32_t mymask = mask; \ |
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[d3c32136] | 306 | rtems_interrupt_disable( level); \ |
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| 307 | val = PPC_SPECIAL_PURPOSE_REGISTER( spr); \ |
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[a78df7b] | 308 | val &= ~mymask; \ |
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| 309 | val |= mybits; \ |
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[d3c32136] | 310 | PPC_SET_SPECIAL_PURPOSE_REGISTER( spr, val); \ |
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| 311 | rtems_interrupt_enable( level); \ |
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| 312 | } while (0) |
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[03bed2db] | 313 | |
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[d3c32136] | 314 | /** |
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| 315 | * @brief Clears in the Special Purpose Register with number @a spr all bits |
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| 316 | * which are set in @a bits. |
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| 317 | * |
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| 318 | * Interrupts are disabled throughout this operation. |
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| 319 | */ |
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| 320 | #define PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS( spr, bits) \ |
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| 321 | do { \ |
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| 322 | rtems_interrupt_level level; \ |
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| 323 | uint32_t val; \ |
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[a78df7b] | 324 | uint32_t mybits = bits; \ |
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[d3c32136] | 325 | rtems_interrupt_disable( level); \ |
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| 326 | val = PPC_SPECIAL_PURPOSE_REGISTER( spr); \ |
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[a78df7b] | 327 | val &= ~mybits; \ |
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[d3c32136] | 328 | PPC_SET_SPECIAL_PURPOSE_REGISTER( spr, val); \ |
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| 329 | rtems_interrupt_enable( level); \ |
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| 330 | } while (0) |
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[03bed2db] | 331 | |
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[d3c32136] | 332 | /** |
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| 333 | * @brief Returns the value of the Device Control Register with number @a dcr. |
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| 334 | * |
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| 335 | * The PowerPC 4XX family has Device Control Registers. |
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| 336 | * |
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| 337 | * @note This macro uses a GNU C extension. |
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| 338 | */ |
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| 339 | #define PPC_DEVICE_CONTROL_REGISTER( dcr) \ |
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| 340 | ( { \ |
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| 341 | uint32_t val; \ |
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| 342 | asm volatile ( \ |
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| 343 | "mfdcr %0, " PPC_STRINGOF( dcr) \ |
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| 344 | : "=r" (val) \ |
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| 345 | ); \ |
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| 346 | val;\ |
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| 347 | } ) |
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[03bed2db] | 348 | |
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[d3c32136] | 349 | /** |
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| 350 | * @brief Sets the Device Control Register with number @a dcr to the value in |
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| 351 | * @a val. |
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| 352 | * |
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| 353 | * The PowerPC 4XX family has Device Control Registers. |
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| 354 | */ |
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| 355 | #define PPC_SET_DEVICE_CONTROL_REGISTER( dcr, val) \ |
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| 356 | do { \ |
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| 357 | asm volatile ( \ |
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| 358 | "mtdcr " PPC_STRINGOF( dcr) ", %0" \ |
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| 359 | : \ |
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| 360 | : "r" (val) \ |
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| 361 | ); \ |
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| 362 | } while (0) |
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[03bed2db] | 363 | |
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[d3c32136] | 364 | /** |
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| 365 | * @brief Sets in the Device Control Register with number @a dcr all bits |
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| 366 | * which are set in @a bits. |
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| 367 | * |
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| 368 | * Interrupts are disabled throughout this operation. |
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| 369 | */ |
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| 370 | #define PPC_SET_DEVICE_CONTROL_REGISTER_BITS( dcr, bits) \ |
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| 371 | do { \ |
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| 372 | rtems_interrupt_level level; \ |
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| 373 | uint32_t val; \ |
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[a78df7b] | 374 | uint32_t mybits = bits; \ |
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[d3c32136] | 375 | rtems_interrupt_disable( level); \ |
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| 376 | val = PPC_DEVICE_CONTROL_REGISTER( dcr); \ |
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[a78df7b] | 377 | val |= mybits; \ |
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[d3c32136] | 378 | PPC_SET_DEVICE_CONTROL_REGISTER( dcr, val); \ |
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| 379 | rtems_interrupt_enable( level); \ |
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| 380 | } while (0) |
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[03bed2db] | 381 | |
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[d3c32136] | 382 | /** |
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| 383 | * @brief Sets in the Device Control Register with number @a dcr all bits |
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| 384 | * which are set in @a bits. The previous register value will be masked with |
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| 385 | * @a mask. |
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| 386 | * |
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| 387 | * Interrupts are disabled throughout this operation. |
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| 388 | */ |
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| 389 | #define PPC_SET_DEVICE_CONTROL_REGISTER_BITS_MASKED( dcr, bits, mask) \ |
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| 390 | do { \ |
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| 391 | rtems_interrupt_level level; \ |
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| 392 | uint32_t val; \ |
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[a78df7b] | 393 | uint32_t mybits = bits; \ |
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| 394 | uint32_t mymask = mask; \ |
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[d3c32136] | 395 | rtems_interrupt_disable( level); \ |
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| 396 | val = PPC_DEVICE_CONTROL_REGISTER( dcr); \ |
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[a78df7b] | 397 | val &= ~mymask; \ |
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| 398 | val |= mybits; \ |
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[d3c32136] | 399 | PPC_SET_DEVICE_CONTROL_REGISTER( dcr, val); \ |
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| 400 | rtems_interrupt_enable( level); \ |
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| 401 | } while (0) |
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[03bed2db] | 402 | |
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[d3c32136] | 403 | /** |
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| 404 | * @brief Clears in the Device Control Register with number @a dcr all bits |
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| 405 | * which are set in @a bits. |
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| 406 | * |
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| 407 | * Interrupts are disabled throughout this operation. |
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| 408 | */ |
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| 409 | #define PPC_CLEAR_DEVICE_CONTROL_REGISTER_BITS( dcr, bits) \ |
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| 410 | do { \ |
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| 411 | rtems_interrupt_level level; \ |
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| 412 | uint32_t val; \ |
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[a78df7b] | 413 | uint32_t mybits = bits; \ |
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[d3c32136] | 414 | rtems_interrupt_disable( level); \ |
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| 415 | val = PPC_DEVICE_CONTROL_REGISTER( dcr); \ |
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[a78df7b] | 416 | val &= ~mybits; \ |
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[d3c32136] | 417 | PPC_SET_DEVICE_CONTROL_REGISTER( dcr, val); \ |
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| 418 | rtems_interrupt_enable( level); \ |
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| 419 | } while (0) |
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[03bed2db] | 420 | |
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| 421 | static inline uint32_t ppc_time_base() |
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| 422 | { |
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| 423 | uint32_t val; |
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| 424 | |
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| 425 | CPU_Get_timebase_low( val); |
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| 426 | |
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| 427 | return val; |
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| 428 | } |
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| 429 | |
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| 430 | static inline void ppc_set_time_base( uint32_t val) |
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| 431 | { |
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[d3c32136] | 432 | PPC_SET_SPECIAL_PURPOSE_REGISTER( TBWL, val); |
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[03bed2db] | 433 | } |
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| 434 | |
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| 435 | static inline uint32_t ppc_time_base_upper() |
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| 436 | { |
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[d3c32136] | 437 | return PPC_SPECIAL_PURPOSE_REGISTER( TBRU); |
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[03bed2db] | 438 | } |
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| 439 | |
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| 440 | static inline void ppc_set_time_base_upper( uint32_t val) |
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| 441 | { |
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[d3c32136] | 442 | PPC_SET_SPECIAL_PURPOSE_REGISTER( TBWU, val); |
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[03bed2db] | 443 | } |
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| 444 | |
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| 445 | static inline uint64_t ppc_time_base_64() |
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| 446 | { |
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| 447 | return PPC_Get_timebase_register(); |
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| 448 | } |
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| 449 | |
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| 450 | static inline void ppc_set_time_base_64( uint64_t val) |
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| 451 | { |
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| 452 | PPC_Set_timebase_register( val); |
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| 453 | } |
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| 454 | |
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[574fb67] | 455 | #else /* ASM */ |
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| 456 | |
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| 457 | #include <rtems/asm.h> |
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| 458 | |
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| 459 | .macro LA reg, addr |
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[d3c32136] | 460 | lis \reg, (\addr)@h |
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| 461 | ori \reg, \reg, (\addr)@l |
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[574fb67] | 462 | .endm |
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| 463 | |
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| 464 | .macro LWI reg, value |
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| 465 | lis \reg, (\value)@h |
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[d3c32136] | 466 | ori \reg, \reg, (\value)@l |
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[574fb67] | 467 | .endm |
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| 468 | |
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| 469 | .macro LW reg, addr |
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[d3c32136] | 470 | lis \reg, \addr@ha |
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| 471 | lwz \reg, \addr@l(\reg) |
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[574fb67] | 472 | .endm |
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| 473 | |
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| 474 | /* |
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| 475 | * Tests the bits in reg1 against the bits set in mask. A match is indicated |
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| 476 | * by EQ = 0 in CR0. A mismatch is indicated by EQ = 1 in CR0. The register |
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| 477 | * reg2 is used to load the mask. |
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| 478 | */ |
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| 479 | .macro TSTBITS reg1, reg2, mask |
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| 480 | LWI \reg2, \mask |
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| 481 | and \reg1, \reg1, \reg2 |
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| 482 | cmplw \reg1, \reg2 |
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| 483 | .endm |
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| 484 | |
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| 485 | .macro SETBITS reg1, reg2, mask |
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| 486 | LWI \reg2, \mask |
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| 487 | or \reg1, \reg1, \reg2 |
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| 488 | .endm |
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| 489 | |
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| 490 | .macro CLRBITS reg1, reg2, mask |
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| 491 | LWI \reg2, \mask |
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| 492 | andc \reg1, \reg1, \reg2 |
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| 493 | .endm |
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| 494 | |
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| 495 | .macro GLOBAL_FUNCTION name |
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| 496 | .global \name |
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| 497 | .type \name, @function |
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| 498 | \name: |
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| 499 | .endm |
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| 500 | |
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[7d453cf] | 501 | /* |
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| 502 | * Obtain interrupt mask |
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| 503 | */ |
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| 504 | .macro GET_INTERRUPT_MASK mask |
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[d3c32136] | 505 | mfspr \mask, sprg0 |
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[7d453cf] | 506 | .endm |
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| 507 | |
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[574fb67] | 508 | /* |
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| 509 | * Disables all asynchronous exeptions (interrupts) which may cause a context |
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| 510 | * switch. |
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| 511 | */ |
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| 512 | .macro INTERRUPT_DISABLE level, mask |
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| 513 | mfmsr \level |
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[7d453cf] | 514 | GET_INTERRUPT_MASK mask=\mask |
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[574fb67] | 515 | andc \mask, \level, \mask |
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| 516 | mtmsr \mask |
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| 517 | .endm |
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| 518 | |
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| 519 | /* |
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| 520 | * Restore previous machine state. |
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| 521 | */ |
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| 522 | .macro INTERRUPT_ENABLE level |
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| 523 | mtmsr \level |
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| 524 | .endm |
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| 525 | |
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| 526 | #define LINKER_SYMBOL( sym) .extern sym |
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| 527 | |
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[03bed2db] | 528 | #endif /* ASM */ |
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| 529 | |
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| 530 | #endif /* LIBCPU_POWERPC_UTILITY_H */ |
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