1 | /* |
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2 | * pgtable.h |
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3 | * |
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4 | * PowerPC memory management structures |
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5 | * |
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6 | * It is a stripped down version of linux ppc file... |
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7 | * |
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8 | * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) |
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9 | * Canon Centre Recherche France. |
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10 | * |
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11 | * The license and distribution terms for this file may be |
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12 | * found in found in the file LICENSE in this distribution or at |
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13 | * http://www.rtems.com/license/LICENSE. |
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14 | * |
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15 | * $Id$ |
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16 | */ |
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17 | |
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18 | #ifndef _PPC_PGTABLE_H |
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19 | #define _PPC_PGTABLE_H |
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20 | |
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21 | /* |
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22 | * The PowerPC MMU uses a hash table containing PTEs, together with |
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23 | * a set of 16 segment registers (on 32-bit implementations), to define |
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24 | * the virtual to physical address mapping. |
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25 | * |
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26 | * We use the hash table as an extended TLB, i.e. a cache of currently |
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27 | * active mappings. We maintain a two-level page table tree, much like |
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28 | * that used by the i386, for the sake of the Linux memory management code. |
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29 | * Low-level assembler code in head.S (procedure hash_page) is responsible |
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30 | * for extracting ptes from the tree and putting them into the hash table |
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31 | * when necessary, and updating the accessed and modified bits in the |
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32 | * page table tree. |
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33 | * |
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34 | * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk. |
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35 | * We also use the two level tables, but we can put the real bits in them |
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36 | * needed for the TLB and tablewalk. These definitions require Mx_CTR.PPM = 0, |
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37 | * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has |
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38 | * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit |
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39 | * based upon user/super access. The TLB does not have accessed nor write |
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40 | * protect. We assume that if the TLB get loaded with an entry it is |
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41 | * accessed, and overload the changed bit for write protect. We use |
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42 | * two bits in the software pte that are supposed to be set to zero in |
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43 | * the TLB entry (24 and 25) for these indicators. Although the level 1 |
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44 | * descriptor contains the guarded and writethrough/copyback bits, we can |
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45 | * set these at the page level since they get copied from the Mx_TWC |
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46 | * register when the TLB entry is loaded. We will use bit 27 for guard, since |
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47 | * that is where it exists in the MD_TWC, and bit 26 for writethrough. |
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48 | * These will get masked from the level 2 descriptor at TLB load time, and |
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49 | * copied to the MD_TWC before it gets loaded. |
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50 | */ |
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51 | |
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52 | /* PMD_SHIFT determines the size of the area mapped by the second-level page tables */ |
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53 | #define PMD_SHIFT 22 |
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54 | #define PMD_SIZE (1UL << PMD_SHIFT) |
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55 | #define PMD_MASK (~(PMD_SIZE-1)) |
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56 | |
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57 | /* PGDIR_SHIFT determines what a third-level page table entry can map */ |
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58 | #define PGDIR_SHIFT 22 |
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59 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) |
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60 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) |
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61 | |
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62 | /* |
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63 | * entries per page directory level: our page-table tree is two-level, so |
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64 | * we don't really have any PMD directory. |
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65 | */ |
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66 | #define PTRS_PER_PTE 1024 |
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67 | #define PTRS_PER_PMD 1 |
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68 | #define PTRS_PER_PGD 1024 |
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69 | #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) |
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70 | |
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71 | /* Just any arbitrary offset to the start of the vmalloc VM area: the |
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72 | * current 64MB value just means that there will be a 64MB "hole" after the |
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73 | * physical memory until the kernel virtual memory starts. That means that |
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74 | * any out-of-bounds memory accesses will hopefully be caught. |
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75 | * The vmalloc() routines leaves a hole of 4kB between each vmalloced |
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76 | * area for the same reason. ;) |
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77 | * |
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78 | * We no longer map larger than phys RAM with the BATs so we don't have |
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79 | * to worry about the VMALLOC_OFFSET causing problems. We do have to worry |
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80 | * about clashes between our early calls to ioremap() that start growing down |
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81 | * from ioremap_base being run into the VM area allocations (growing upwards |
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82 | * from VMALLOC_START). For this reason we have ioremap_bot to check when |
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83 | * we actually run into our mappings setup in the early boot with the VM |
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84 | * system. This really does become a problem for machines with good amounts |
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85 | * of RAM. -- Cort |
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86 | */ |
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87 | #define VMALLOC_OFFSET (0x4000000) /* 64M */ |
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88 | #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))) |
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89 | #define VMALLOC_VMADDR(x) ((unsigned long)(x)) |
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90 | #define VMALLOC_END ioremap_bot |
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91 | |
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92 | /* |
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93 | * Bits in a linux-style PTE. These match the bits in the |
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94 | * (hardware-defined) PowerPC PTE as closely as possible. |
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95 | */ |
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96 | #define _PAGE_PRESENT 0x001 /* software: pte contains a translation */ |
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97 | #define _PAGE_USER 0x002 /* matches one of the PP bits */ |
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98 | #define _PAGE_RW 0x004 /* software: user write access allowed */ |
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99 | #define _PAGE_GUARDED 0x008 |
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100 | #define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */ |
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101 | #define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */ |
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102 | #define _PAGE_WRITETHRU 0x040 /* W: cache write-through */ |
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103 | #define _PAGE_DIRTY 0x080 /* C: page changed */ |
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104 | #define _PAGE_ACCESSED 0x100 /* R: page referenced */ |
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105 | #define _PAGE_HWWRITE 0x200 /* software: _PAGE_RW & _PAGE_DIRTY */ |
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106 | #define _PAGE_SHARED 0 |
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107 | |
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108 | #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) |
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109 | |
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110 | #define _PAGE_BASE _PAGE_PRESENT | _PAGE_ACCESSED |
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111 | #define _PAGE_WRENABLE _PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE |
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112 | |
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113 | #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED) |
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114 | |
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115 | #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER | \ |
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116 | _PAGE_SHARED) |
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117 | #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER) |
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118 | #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER) |
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119 | #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED) |
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120 | #define PAGE_KERNEL_CI __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED | \ |
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121 | _PAGE_NO_CACHE ) |
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122 | |
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123 | /* |
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124 | * The PowerPC can only do execute protection on a segment (256MB) basis, |
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125 | * not on a page basis. So we consider execute permission the same as read. |
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126 | * Also, write permissions imply read permissions. |
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127 | * This is the closest we can get.. |
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128 | */ |
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129 | #define __P000 PAGE_NONE |
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130 | #define __P001 PAGE_READONLY |
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131 | #define __P010 PAGE_COPY |
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132 | #define __P011 PAGE_COPY |
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133 | #define __P100 PAGE_READONLY |
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134 | #define __P101 PAGE_READONLY |
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135 | #define __P110 PAGE_COPY |
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136 | #define __P111 PAGE_COPY |
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137 | |
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138 | #define __S000 PAGE_NONE |
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139 | #define __S001 PAGE_READONLY |
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140 | #define __S010 PAGE_SHARED |
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141 | #define __S011 PAGE_SHARED |
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142 | #define __S100 PAGE_READONLY |
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143 | #define __S101 PAGE_READONLY |
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144 | #define __S110 PAGE_SHARED |
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145 | #define __S111 PAGE_SHARED |
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146 | #endif /* _PPC_PGTABLE_H */ |
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