source: rtems/c/src/lib/libcpu/powerpc/shared/include/mmu.h @ d3d9ef37

4.104.114.84.95
Last change on this file since d3d9ef37 was a859df85, checked in by Ralf Corsepius <ralf.corsepius@…>, on Feb 13, 2005 at 5:00:15 AM

New header guards.

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1/*
2 * mmu.h
3 *
4 *      PowerPC memory management structures
5 *
6 * It is a stripped down version of linux ppc file...
7 *
8 * Copyright (C) 1999  Eric Valette (valette@crf.canon.fr)
9 *                     Canon Centre Recherche France.
10 *
11 *  The license and distribution terms for this file may be
12 *  found in found in the file LICENSE in this distribution or at
13 *  http://www.rtems.com/license/LICENSE.
14 *
15 *  $Id$
16 */
17
18#ifndef _LIBCPU_MMU_H
19#define _LIBCPU_MMU_H
20
21#ifndef ASM
22/* Hardware Page Table Entry */
23typedef struct _PTE {
24        unsigned long v:1;      /* Entry is valid */
25        unsigned long vsid:24;  /* Virtual segment identifier */
26        unsigned long h:1;      /* Hash algorithm indicator */
27        unsigned long api:6;    /* Abbreviated page index */
28        unsigned long rpn:20;   /* Real (physical) page number */
29        unsigned long    :3;    /* Unused */
30        unsigned long r:1;      /* Referenced */
31        unsigned long c:1;      /* Changed */
32        unsigned long w:1;      /* Write-thru cache mode */
33        unsigned long i:1;      /* Cache inhibited */
34        unsigned long m:1;      /* Memory coherence */
35        unsigned long g:1;      /* Guarded */
36        unsigned long  :1;      /* Unused */
37        unsigned long pp:2;     /* Page protection */
38} PTE; 
39
40/* Values for PP (assumes Ks=0, Kp=1) */
41#define PP_RWXX 0       /* Supervisor read/write, User none */
42#define PP_RWRX 1       /* Supervisor read/write, User read */
43#define PP_RWRW 2       /* Supervisor read/write, User read/write */
44#define PP_RXRX 3       /* Supervisor read,       User read */
45
46/* Segment Register */
47typedef struct _SEGREG {
48        unsigned long t:1;      /* Normal or I/O  type */
49        unsigned long ks:1;     /* Supervisor 'key' (normally 0) */
50        unsigned long kp:1;     /* User 'key' (normally 1) */
51        unsigned long n:1;      /* No-execute */
52        unsigned long :4;       /* Unused */
53        unsigned long vsid:24;  /* Virtual Segment Identifier */
54} SEGREG;
55
56/* Block Address Translation (BAT) Registers */
57typedef struct _P601_BATU {     /* Upper part of BAT for 601 processor */
58        unsigned long bepi:15;  /* Effective page index (virtual address) */
59        unsigned long :8;       /* unused */
60        unsigned long w:1;
61        unsigned long i:1;      /* Cache inhibit */
62        unsigned long m:1;      /* Memory coherence */
63        unsigned long ks:1;     /* Supervisor key (normally 0) */
64        unsigned long kp:1;     /* User key (normally 1) */
65        unsigned long pp:2;     /* Page access protections */
66} P601_BATU;
67
68typedef struct _BATU {          /* Upper part of BAT (all except 601) */
69        unsigned long bepi:15;  /* Effective page index (virtual address) */
70        unsigned long :4;       /* Unused */
71        unsigned long bl:11;    /* Block size mask */
72        unsigned long vs:1;     /* Supervisor valid */
73        unsigned long vp:1;     /* User valid */
74} BATU;   
75
76typedef struct _P601_BATL {     /* Lower part of BAT for 601 processor */
77        unsigned long brpn:15;  /* Real page index (physical address) */
78        unsigned long :10;      /* Unused */
79        unsigned long v:1;      /* Valid bit */
80        unsigned long bl:6;     /* Block size mask */
81} P601_BATL;
82
83typedef struct _BATL {          /* Lower part of BAT (all except 601) */
84        unsigned long brpn:15;  /* Real page index (physical address) */
85        unsigned long :10;      /* Unused */
86        unsigned long w:1;      /* Write-thru cache */
87        unsigned long i:1;      /* Cache inhibit */
88        unsigned long m:1;      /* Memory coherence */
89        unsigned long g:1;      /* Guarded (MBZ in IBAT) */
90        unsigned long :1;       /* Unused */
91        unsigned long pp:2;     /* Page access protections */
92} BATL;
93
94typedef struct _BAT {
95        BATU batu;              /* Upper register */
96        BATL batl;              /* Lower register */
97} BAT;
98
99typedef struct _P601_BAT {
100        P601_BATU batu;         /* Upper register */
101        P601_BATL batl;         /* Lower register */
102} P601_BAT;
103
104/* Block size masks */
105#define BL_128K 0x000
106#define BL_256K 0x001
107#define BL_512K 0x003
108#define BL_1M   0x007
109#define BL_2M   0x00F
110#define BL_4M   0x01F
111#define BL_8M   0x03F
112#define BL_16M  0x07F
113#define BL_32M  0x0FF
114#define BL_64M  0x1FF
115#define BL_128M 0x3FF
116#define BL_256M 0x7FF
117
118/* BAT Access Protection */
119#define BPP_XX  0x00            /* No access */
120#define BPP_RX  0x01            /* Read only */
121#define BPP_RW  0x02            /* Read/write */
122
123/*
124 * Simulated two-level MMU.  This structure is used by the kernel
125 * to keep track of MMU mappings and is used to update/maintain
126 * the hardware HASH table which is really a cache of mappings.
127 *
128 * The simulated structures mimic the hardware available on other
129 * platforms, notably the 80x86 and 680x0.
130 */
131
132typedef struct _pte {
133        unsigned long page_num:20;
134        unsigned long flags:12;         /* Page flags (some unused bits) */
135} pte;
136
137#define PD_SHIFT (10+12)                /* Page directory */
138#define PD_MASK  0x03FF
139#define PT_SHIFT (12)                   /* Page Table */
140#define PT_MASK  0x03FF
141#define PG_SHIFT (12)                   /* Page Entry */
142 
143
144/* MMU context */
145
146typedef struct _MMU_context {
147        SEGREG  segs[16];       /* Segment registers */
148        pte     **pmap;         /* Two-level page-map structure */
149} MMU_context;
150
151/* Used to set up SDR1 register */
152#define HASH_TABLE_SIZE_64K     0x00010000
153#define HASH_TABLE_SIZE_128K    0x00020000
154#define HASH_TABLE_SIZE_256K    0x00040000
155#define HASH_TABLE_SIZE_512K    0x00080000
156#define HASH_TABLE_SIZE_1M      0x00100000
157#define HASH_TABLE_SIZE_2M      0x00200000
158#define HASH_TABLE_SIZE_4M      0x00400000
159#define HASH_TABLE_MASK_64K     0x000   
160#define HASH_TABLE_MASK_128K    0x001   
161#define HASH_TABLE_MASK_256K    0x003   
162#define HASH_TABLE_MASK_512K    0x007
163#define HASH_TABLE_MASK_1M      0x00F   
164#define HASH_TABLE_MASK_2M      0x01F   
165#define HASH_TABLE_MASK_4M      0x03F   
166
167/* invalidate a TLB entry */
168extern inline void _tlbie(unsigned long va)
169{
170        asm volatile ("tlbie %0" : : "r"(va));
171}
172
173extern void _tlbia(void);               /* invalidate all TLB entries */
174#endif /* ASM */
175
176/* Control/status registers for the MPC8xx.
177 * A write operation to these registers causes serialized access.
178 * During software tablewalk, the registers used perform mask/shift-add
179 * operations when written/read.  A TLB entry is created when the Mx_RPN
180 * is written, and the contents of several registers are used to
181 * create the entry.
182 */
183#define MI_CTR          784     /* Instruction TLB control register */
184#define MI_GPM          0x80000000      /* Set domain manager mode */
185#define MI_PPM          0x40000000      /* Set subpage protection */
186#define MI_CIDEF        0x20000000      /* Set cache inhibit when MMU dis */
187#define MI_RSV4I        0x08000000      /* Reserve 4 TLB entries */
188#define MI_PPCS         0x02000000      /* Use MI_RPN prob/priv state */
189#define MI_IDXMASK      0x00001f00      /* TLB index to be loaded */
190#define MI_RESETVAL     0x00000000      /* Value of register at reset */
191
192/* These are the Ks and Kp from the PowerPC books.  For proper operation,
193 * Ks = 0, Kp = 1.
194 */
195#define MI_AP           786
196#define MI_Ks           0x80000000      /* Should not be set */
197#define MI_Kp           0x40000000      /* Should always be set */
198
199/* The effective page number register.  When read, contains the information
200 * about the last instruction TLB miss.  When MI_RPN is written, bits in
201 * this register are used to create the TLB entry.
202 */
203#define MI_EPN          787
204#define MI_EPNMASK      0xfffff000      /* Effective page number for entry */
205#define MI_EVALID       0x00000200      /* Entry is valid */
206#define MI_ASIDMASK     0x0000000f      /* ASID match value */
207                                        /* Reset value is undefined */
208
209/* A "level 1" or "segment" or whatever you want to call it register.
210 * For the instruction TLB, it contains bits that get loaded into the
211 * TLB entry when the MI_RPN is written.
212 */
213#define MI_TWC          789
214#define MI_APG          0x000001e0      /* Access protection group (0) */
215#define MI_GUARDED      0x00000010      /* Guarded storage */
216#define MI_PSMASK       0x0000000c      /* Mask of page size bits */
217#define MI_PS8MEG       0x0000000c      /* 8M page size */
218#define MI_PS512K       0x00000004      /* 512K page size */
219#define MI_PS4K_16K     0x00000000      /* 4K or 16K page size */
220#define MI_SVALID       0x00000001      /* Segment entry is valid */
221                                        /* Reset value is undefined */
222
223/* Real page number.  Defined by the pte.  Writing this register
224 * causes a TLB entry to be created for the instruction TLB, using
225 * additional information from the MI_EPN, and MI_TWC registers.
226 */
227#define MI_RPN          790
228
229/* Define an RPN value for mapping kernel memory to large virtual
230 * pages for boot initialization.  This has real page number of 0,
231 * large page size, shared page, cache enabled, and valid.
232 * Also mark all subpages valid and write access.
233 */
234#define MI_BOOTINIT     0x000001fd
235
236#define MD_CTR          792     /* Data TLB control register */
237#define MD_GPM          0x80000000      /* Set domain manager mode */
238#define MD_PPM          0x40000000      /* Set subpage protection */
239#define MD_CIDEF        0x20000000      /* Set cache inhibit when MMU dis */
240#define MD_WTDEF        0x10000000      /* Set writethrough when MMU dis */
241#define MD_RSV4I        0x08000000      /* Reserve 4 TLB entries */
242#define MD_TWAM         0x04000000      /* Use 4K page hardware assist */
243#define MD_PPCS         0x02000000      /* Use MI_RPN prob/priv state */
244#define MD_IDXMASK      0x00001f00      /* TLB index to be loaded */
245#define MD_RESETVAL     0x04000000      /* Value of register at reset */
246
247#define M_CASID         793     /* Address space ID (context) to match */
248#define MC_ASIDMASK     0x0000000f      /* Bits used for ASID value */
249
250
251/* These are the Ks and Kp from the PowerPC books.  For proper operation,
252 * Ks = 0, Kp = 1.
253 */
254#define MD_AP           794
255#define MD_Ks           0x80000000      /* Should not be set */
256#define MD_Kp           0x40000000      /* Should always be set */
257
258/* The effective page number register.  When read, contains the information
259 * about the last instruction TLB miss.  When MD_RPN is written, bits in
260 * this register are used to create the TLB entry.
261 */
262#define MD_EPN          795
263#define MD_EPNMASK      0xfffff000      /* Effective page number for entry */
264#define MD_EVALID       0x00000200      /* Entry is valid */
265#define MD_ASIDMASK     0x0000000f      /* ASID match value */
266                                        /* Reset value is undefined */
267
268/* The pointer to the base address of the first level page table.
269 * During a software tablewalk, reading this register provides the address
270 * of the entry associated with MD_EPN.
271 */
272#define M_TWB           796
273#define M_L1TB          0xfffff000      /* Level 1 table base address */
274#define M_L1INDX        0x00000ffc      /* Level 1 index, when read */
275                                        /* Reset value is undefined */
276
277/* A "level 1" or "segment" or whatever you want to call it register.
278 * For the data TLB, it contains bits that get loaded into the TLB entry
279 * when the MD_RPN is written.  It is also provides the hardware assist
280 * for finding the PTE address during software tablewalk.
281 */
282#define MD_TWC          797
283#define MD_L2TB         0xfffff000      /* Level 2 table base address */
284#define MD_L2INDX       0xfffffe00      /* Level 2 index (*pte), when read */
285#define MD_APG          0x000001e0      /* Access protection group (0) */
286#define MD_GUARDED      0x00000010      /* Guarded storage */
287#define MD_PSMASK       0x0000000c      /* Mask of page size bits */
288#define MD_PS8MEG       0x0000000c      /* 8M page size */
289#define MD_PS512K       0x00000004      /* 512K page size */
290#define MD_PS4K_16K     0x00000000      /* 4K or 16K page size */
291#define MD_WT           0x00000002      /* Use writethrough page attribute */
292#define MD_SVALID       0x00000001      /* Segment entry is valid */
293                                        /* Reset value is undefined */
294
295
296/* Real page number.  Defined by the pte.  Writing this register
297 * causes a TLB entry to be created for the data TLB, using
298 * additional information from the MD_EPN, and MD_TWC registers.
299 */
300#define MD_RPN          798
301
302/* This is a temporary storage register that could be used to save
303 * a processor working register during a tablewalk.
304 */
305#define M_TW            799
306#endif /* _LIBCPU_MMU_H */
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