[abd9401] | 1 | /* |
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| 2 | * io.h |
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| 3 | * |
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| 4 | * This file contains inline implementation of function to |
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| 5 | * deal with IO. |
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| 6 | * |
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| 7 | * It is a stripped down version of linux ppc file... |
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| 8 | * |
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| 9 | * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) |
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| 10 | * Canon Centre Recherche France. |
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| 11 | * |
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| 12 | * The license and distribution terms for this file may be |
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| 13 | * found in found in the file LICENSE in this distribution or at |
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| 14 | * http://www.OARcorp.com/rtems/license.html. |
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| 15 | * |
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| 16 | * $Id$ |
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| 17 | */ |
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| 18 | #ifndef _LIBCPU_IO_H_ |
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| 19 | #define _LIBCPU_IO_H_ |
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| 20 | |
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| 21 | |
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| 22 | #define PREP_ISA_IO_BASE 0x80000000 |
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| 23 | #define PREP_ISA_MEM_BASE 0xc0000000 |
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| 24 | #define PREP_PCI_DRAM_OFFSET 0x80000000 |
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| 25 | |
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| 26 | #define _IO_BASE PREP_ISA_IO_BASE |
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| 27 | #define _ISA_MEM_BASE PREP_ISA_MEM_BASE |
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| 28 | #define PCI_DRAM_OFFSET PREP_PCI_DRAM_OFFSET |
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| 29 | |
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| 30 | #ifndef ASM |
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| 31 | |
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| 32 | #define inb(port) in_8((unsigned char *)((port)+_IO_BASE)) |
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| 33 | #define outb(val, port) out_8((unsigned char *)((port)+_IO_BASE), (val)) |
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| 34 | #define inw(port) in_le16((unsigned short *)((port)+_IO_BASE)) |
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| 35 | #define outw(val, port) out_le16((unsigned short *)((port)+_IO_BASE), (val)) |
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| 36 | #define inl(port) in_le32((unsigned *)((port)+_IO_BASE)) |
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| 37 | #define outl(val, port) out_le32((unsigned *)((port)+_IO_BASE), (val)) |
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| 38 | |
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| 39 | /* |
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| 40 | * Enforce In-order Execution of I/O: |
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| 41 | * Acts as a barrier to ensure all previous I/O accesses have |
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| 42 | * completed before any further ones are issued. |
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| 43 | */ |
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| 44 | extern inline void eieio(void) |
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| 45 | { |
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| 46 | __asm__ __volatile__ ("eieio"); |
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| 47 | } |
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| 48 | |
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| 49 | |
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| 50 | /* Enforce in-order execution of data I/O. |
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| 51 | * No distinction between read/write on PPC; use eieio for all three. |
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| 52 | */ |
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| 53 | #define iobarrier_rw() eieio() |
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| 54 | #define iobarrier_r() eieio() |
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| 55 | #define iobarrier_w() eieio() |
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| 56 | |
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| 57 | /* |
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| 58 | * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. |
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| 59 | */ |
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| 60 | extern inline int in_8(volatile unsigned char *addr) |
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| 61 | { |
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| 62 | int ret; |
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| 63 | |
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| 64 | __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); |
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| 65 | return ret; |
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| 66 | } |
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| 67 | |
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| 68 | extern inline void out_8(volatile unsigned char *addr, int val) |
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| 69 | { |
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| 70 | __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); |
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| 71 | } |
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| 72 | |
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| 73 | extern inline int in_le16(volatile unsigned short *addr) |
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| 74 | { |
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| 75 | int ret; |
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| 76 | |
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| 77 | __asm__ __volatile__("lhbrx %0,0,%1; eieio" : "=r" (ret) : |
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| 78 | "r" (addr), "m" (*addr)); |
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| 79 | return ret; |
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| 80 | } |
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| 81 | |
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| 82 | extern inline int in_be16(volatile unsigned short *addr) |
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| 83 | { |
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| 84 | int ret; |
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| 85 | |
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| 86 | __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); |
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| 87 | return ret; |
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| 88 | } |
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| 89 | |
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| 90 | extern inline void out_le16(volatile unsigned short *addr, int val) |
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| 91 | { |
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| 92 | __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) : |
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| 93 | "r" (val), "r" (addr)); |
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| 94 | } |
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| 95 | |
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| 96 | extern inline void out_be16(volatile unsigned short *addr, int val) |
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| 97 | { |
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| 98 | __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); |
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| 99 | } |
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| 100 | |
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| 101 | extern inline unsigned in_le32(volatile unsigned *addr) |
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| 102 | { |
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| 103 | unsigned ret; |
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| 104 | |
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| 105 | __asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) : |
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| 106 | "r" (addr), "m" (*addr)); |
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| 107 | return ret; |
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| 108 | } |
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| 109 | |
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| 110 | extern inline unsigned in_be32(volatile unsigned *addr) |
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| 111 | { |
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| 112 | unsigned ret; |
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| 113 | |
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| 114 | __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); |
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| 115 | return ret; |
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| 116 | } |
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| 117 | |
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| 118 | extern inline void out_le32(volatile unsigned *addr, int val) |
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| 119 | { |
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| 120 | __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) : |
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| 121 | "r" (val), "r" (addr)); |
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| 122 | } |
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| 123 | |
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| 124 | extern inline void out_be32(volatile unsigned *addr, int val) |
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| 125 | { |
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| 126 | __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); |
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| 127 | } |
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| 128 | |
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| 129 | #endif /* ASM */ |
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| 130 | #endif /* _LIBCPU_IO_H_ */ |
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