[abd9401] | 1 | /* |
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| 2 | * io.h |
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| 3 | * |
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| 4 | * This file contains inline implementation of function to |
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| 5 | * deal with IO. |
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| 6 | * |
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| 7 | * It is a stripped down version of linux ppc file... |
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| 8 | * |
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| 9 | * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) |
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| 10 | * Canon Centre Recherche France. |
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| 11 | * |
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| 12 | * The license and distribution terms for this file may be |
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| 13 | * found in found in the file LICENSE in this distribution or at |
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[21e1c44] | 14 | * http://www.rtems.com/license/LICENSE. |
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[abd9401] | 15 | * |
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| 16 | * $Id$ |
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| 17 | */ |
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[a859df85] | 18 | #ifndef _LIBCPU_IO_H |
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| 19 | #define _LIBCPU_IO_H |
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[abd9401] | 20 | |
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| 21 | |
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| 22 | #define PREP_ISA_IO_BASE 0x80000000 |
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| 23 | #define PREP_ISA_MEM_BASE 0xc0000000 |
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| 24 | #define PREP_PCI_DRAM_OFFSET 0x80000000 |
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| 25 | |
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[438b5388] | 26 | #define CHRP_ISA_IO_BASE 0xfe000000 |
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| 27 | #define CHRP_ISA_MEM_BASE 0xfd000000 |
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| 28 | #define CHRP_PCI_DRAM_OFFSET 0x00000000 |
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| 29 | |
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| 30 | /* _IO_BASE, _ISA_MEM_BASE, PCI_DRAM_OFFSET are now defined by bsp.h */ |
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[abd9401] | 31 | |
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| 32 | #ifndef ASM |
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| 33 | |
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[438b5388] | 34 | #include <bsp.h> /* for _IO_BASE & friends */ |
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| 35 | |
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| 36 | /* NOTE: The use of these macros is DISCOURAGED. |
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| 37 | * you should consider e.g. using in_xxx / out_xxx |
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| 38 | * with a device specific base address that is |
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| 39 | * defined by the BSP. This makes drivers easier |
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| 40 | * to port. |
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| 41 | */ |
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[abd9401] | 42 | #define inb(port) in_8((unsigned char *)((port)+_IO_BASE)) |
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| 43 | #define outb(val, port) out_8((unsigned char *)((port)+_IO_BASE), (val)) |
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| 44 | #define inw(port) in_le16((unsigned short *)((port)+_IO_BASE)) |
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| 45 | #define outw(val, port) out_le16((unsigned short *)((port)+_IO_BASE), (val)) |
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| 46 | #define inl(port) in_le32((unsigned *)((port)+_IO_BASE)) |
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| 47 | #define outl(val, port) out_le32((unsigned *)((port)+_IO_BASE), (val)) |
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| 48 | |
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| 49 | /* |
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| 50 | * Enforce In-order Execution of I/O: |
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| 51 | * Acts as a barrier to ensure all previous I/O accesses have |
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| 52 | * completed before any further ones are issued. |
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| 53 | */ |
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| 54 | extern inline void eieio(void) |
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| 55 | { |
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| 56 | __asm__ __volatile__ ("eieio"); |
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| 57 | } |
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| 58 | |
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| 59 | |
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| 60 | /* Enforce in-order execution of data I/O. |
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| 61 | * No distinction between read/write on PPC; use eieio for all three. |
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| 62 | */ |
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| 63 | #define iobarrier_rw() eieio() |
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| 64 | #define iobarrier_r() eieio() |
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| 65 | #define iobarrier_w() eieio() |
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| 66 | |
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| 67 | /* |
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| 68 | * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. |
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| 69 | */ |
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| 70 | extern inline int in_8(volatile unsigned char *addr) |
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| 71 | { |
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| 72 | int ret; |
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| 73 | |
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| 74 | __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); |
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| 75 | return ret; |
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| 76 | } |
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| 77 | |
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| 78 | extern inline void out_8(volatile unsigned char *addr, int val) |
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| 79 | { |
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| 80 | __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); |
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| 81 | } |
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| 82 | |
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| 83 | extern inline int in_le16(volatile unsigned short *addr) |
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| 84 | { |
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| 85 | int ret; |
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| 86 | |
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| 87 | __asm__ __volatile__("lhbrx %0,0,%1; eieio" : "=r" (ret) : |
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| 88 | "r" (addr), "m" (*addr)); |
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| 89 | return ret; |
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| 90 | } |
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| 91 | |
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| 92 | extern inline int in_be16(volatile unsigned short *addr) |
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| 93 | { |
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| 94 | int ret; |
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| 95 | |
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| 96 | __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); |
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| 97 | return ret; |
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| 98 | } |
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| 99 | |
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| 100 | extern inline void out_le16(volatile unsigned short *addr, int val) |
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| 101 | { |
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| 102 | __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) : |
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| 103 | "r" (val), "r" (addr)); |
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| 104 | } |
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| 105 | |
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| 106 | extern inline void out_be16(volatile unsigned short *addr, int val) |
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| 107 | { |
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| 108 | __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); |
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| 109 | } |
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| 110 | |
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| 111 | extern inline unsigned in_le32(volatile unsigned *addr) |
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| 112 | { |
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| 113 | unsigned ret; |
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| 114 | |
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| 115 | __asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) : |
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| 116 | "r" (addr), "m" (*addr)); |
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| 117 | return ret; |
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| 118 | } |
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| 119 | |
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| 120 | extern inline unsigned in_be32(volatile unsigned *addr) |
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| 121 | { |
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| 122 | unsigned ret; |
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| 123 | |
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| 124 | __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); |
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| 125 | return ret; |
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| 126 | } |
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| 127 | |
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| 128 | extern inline void out_le32(volatile unsigned *addr, int val) |
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| 129 | { |
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| 130 | __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) : |
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| 131 | "r" (val), "r" (addr)); |
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| 132 | } |
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| 133 | |
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| 134 | extern inline void out_be32(volatile unsigned *addr, int val) |
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| 135 | { |
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| 136 | __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); |
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| 137 | } |
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| 138 | |
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| 139 | #endif /* ASM */ |
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[a859df85] | 140 | #endif /* _LIBCPU_IO_H */ |
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