4.104.114.84.95
Last change
on this file since 6fae458 was
0d776cd2,
checked in by Joel Sherrill <joel.sherrill@…>, on 05/14/02 at 16:56:44
|
2001-05-14 Till Straumann <strauman@…>
- rtems/powerpc/registers.h, rtems/score/ppc.h: Per PR213, add
the following:
- support for the MPC74000 (AKA G4); there is no
AltiVec? support yet, however.
- the cache flushing assembly code uses hardware-flush on the G4.
Also, a couple of hardcoded numerical values were replaced
by more readable symbolic constants.
- extended interrupt-disabled code section so enclose the entire
cache flush/invalidate procedure (as recommended by the book).
This is not (latency) critical as it is only used by
init code but prevents possible corruption.
- Trivial page table support as been added.
(1:1 effective-virtual-physical address mapping which is only
useful only on CPUs which feature hardware TLB replacement,
e.g. >604. This allows for write-protecting memory regions,
e.g. text/ro-data which makes catching corruptors a lot easier.
It also frees one DBAT/IBAT and gives more flexibility
for setting up address maps :-)
- setdbat() allows changing BAT0 also (since the BSP may use
a page table, BAT0 could be available...).
- asm_setdbatX() violated the SVR ABI by using
r20 as a scratch register; changed for r0
- according to the book, a context synchronizing instruction is
necessary prior to and after changing a DBAT -> isync added
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-
Property mode set to
100644
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File size:
1.0 KB
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1 | /* |
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2 | * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) |
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3 | * Canon Centre Recherche France. |
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4 | * |
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5 | * Added MPC8260 Andy Dachs <a.dachs@sstl.co.uk> |
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6 | * Surrey Satellite Technology Limited |
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7 | * |
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8 | * |
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9 | * The license and distribution terms for this file may be |
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10 | * found in found in the file LICENSE in this distribution or at |
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11 | * http://www.OARcorp.com/rtems/license.html. |
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12 | * |
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13 | * $Id$ |
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14 | */ |
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15 | |
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16 | #ifndef _libcpu_cpuIdent_h |
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17 | #define _libcpu_cpuIdent_h |
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18 | |
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19 | #ifndef ASM |
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20 | typedef enum |
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21 | { |
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22 | PPC_601 = 0x1, |
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23 | PPC_603 = 0x3, |
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24 | PPC_604 = 0x4, |
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25 | PPC_603e = 0x6, |
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26 | PPC_603ev = 0x7, |
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27 | PPC_750 = 0x8, |
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28 | PPC_604e = 0x9, |
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29 | PPC_604r = 0xA, |
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30 | PPC_7400 = 0xA, |
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31 | PPC_620 = 0x16, |
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32 | PPC_860 = 0x50, |
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33 | PPC_821 = PPC_860, |
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34 | PPC_8260 = 0x81, |
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35 | PPC_UNKNOWN = 0xff |
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36 | } ppc_cpu_id_t; |
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37 | |
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38 | typedef unsigned short ppc_cpu_revision_t; |
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39 | |
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40 | extern ppc_cpu_id_t get_ppc_cpu_type (); |
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41 | extern ppc_cpu_id_t current_ppc_cpu; |
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42 | extern char *get_ppc_cpu_type_name(ppc_cpu_id_t cpu); |
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43 | extern ppc_cpu_revision_t get_ppc_cpu_revision (); |
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44 | extern ppc_cpu_revision_t current_ppc_revision; |
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45 | #endif /* ASM */ |
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46 | |
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47 | #endif |
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