source: rtems/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h @ 0d776cd2

4.104.114.84.95
Last change on this file since 0d776cd2 was 0d776cd2, checked in by Joel Sherrill <joel.sherrill@…>, on May 14, 2002 at 4:56:44 PM

2001-05-14 Till Straumann <strauman@…>

  • rtems/powerpc/registers.h, rtems/score/ppc.h: Per PR213, add the following:
    • support for the MPC74000 (AKA G4); there is no AltiVec? support yet, however.
    • the cache flushing assembly code uses hardware-flush on the G4. Also, a couple of hardcoded numerical values were replaced by more readable symbolic constants.
    • extended interrupt-disabled code section so enclose the entire cache flush/invalidate procedure (as recommended by the book). This is not (latency) critical as it is only used by init code but prevents possible corruption.
    • Trivial page table support as been added. (1:1 effective-virtual-physical address mapping which is only useful only on CPUs which feature hardware TLB replacement, e.g. >604. This allows for write-protecting memory regions, e.g. text/ro-data which makes catching corruptors a lot easier. It also frees one DBAT/IBAT and gives more flexibility for setting up address maps :-)
    • setdbat() allows changing BAT0 also (since the BSP may use a page table, BAT0 could be available...).
    • asm_setdbatX() violated the SVR ABI by using r20 as a scratch register; changed for r0
    • according to the book, a context synchronizing instruction is necessary prior to and after changing a DBAT -> isync added
  • Property mode set to 100644
File size: 1.0 KB
Line 
1/*
2 * Copyright (C) 1999  Eric Valette (valette@crf.canon.fr)
3 *                     Canon Centre Recherche France.
4 *
5 *  Added MPC8260 Andy Dachs <a.dachs@sstl.co.uk>
6 *  Surrey Satellite Technology Limited
7 *
8 *
9 *  The license and distribution terms for this file may be
10 *  found in found in the file LICENSE in this distribution or at
11 *  http://www.OARcorp.com/rtems/license.html.
12 *
13 *  $Id$
14 */
15
16#ifndef _libcpu_cpuIdent_h
17#define _libcpu_cpuIdent_h
18
19#ifndef ASM
20typedef enum
21{
22  PPC_601 = 0x1,
23  PPC_603 = 0x3,
24  PPC_604 = 0x4,
25  PPC_603e = 0x6,
26  PPC_603ev = 0x7,
27  PPC_750 = 0x8,
28  PPC_604e = 0x9,
29  PPC_604r = 0xA,
30  PPC_7400 = 0xA,
31  PPC_620 = 0x16,
32  PPC_860 = 0x50,
33  PPC_821 = PPC_860,
34  PPC_8260 = 0x81,
35  PPC_UNKNOWN = 0xff
36} ppc_cpu_id_t;
37
38typedef unsigned short ppc_cpu_revision_t;
39
40extern ppc_cpu_id_t get_ppc_cpu_type ();
41extern ppc_cpu_id_t current_ppc_cpu;
42extern char *get_ppc_cpu_type_name(ppc_cpu_id_t cpu);
43extern ppc_cpu_revision_t get_ppc_cpu_revision ();
44extern ppc_cpu_revision_t current_ppc_revision;
45#endif /* ASM */
46
47#endif
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