source: rtems/c/src/lib/libcpu/powerpc/shared/include/cpu.h @ b929c2de

4.104.114.84.95
Last change on this file since b929c2de was b929c2de, checked in by Joel Sherrill <joel.sherrill@…>, on Apr 17, 2002 at 7:39:16 PM

2001-04-17 Joel Sherrill <joel@…>

  • shared/include/cpu.h: Added ifndef ASM.
  • Property mode set to 100644
File size: 8.9 KB
Line 
1/*
2 * cpu.h
3 *
4 * This file contains some powerpc MSR and registers access definitions.
5 *
6 * It is a stripped down version of linux ppc processor.h file...
7 *
8 * Copyright (C) 1999  Eric Valette (valette@crf.canon.fr)
9 *                     Canon Centre Recherche France.
10 *
11 *  Added MPC8260 Andy Dachs <a.dachs@sstl.co.uk>
12 *  Surrey Satellite Technology Limited
13 *
14 *
15 *  The license and distribution terms for this file may be
16 *  found in found in the file LICENSE in this distribution or at
17 *  http://www.OARcorp.com/rtems/license.html.
18 *
19 *  $Id$
20 */
21
22#ifndef __PPC_CPU_H
23#define __PPC_CPU_H
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29/* Bit encodings for Machine State Register (MSR) */
30#define MSR_POW         (1<<18)         /* Enable Power Management */
31#define MSR_TGPR        (1<<17)         /* TLB Update registers in use */
32#define MSR_ILE         (1<<16)         /* Interrupt Little-Endian enable */
33#define MSR_EE          (1<<15)         /* External Interrupt enable */
34#define MSR_PR          (1<<14)         /* Supervisor/User privilege */
35#define MSR_FP          (1<<13)         /* Floating Point enable */
36#define MSR_ME          (1<<12)         /* Machine Check enable */
37#define MSR_FE0         (1<<11)         /* Floating Exception mode 0 */
38#define MSR_SE          (1<<10)         /* Single Step */
39#define MSR_BE          (1<<9)          /* Branch Trace */
40#define MSR_FE1         (1<<8)          /* Floating Exception mode 1 */
41#define MSR_IP          (1<<6)          /* Exception prefix 0x000/0xFFF */
42#define MSR_IR          (1<<5)          /* Instruction MMU enable */
43#define MSR_DR          (1<<4)          /* Data MMU enable */
44#define MSR_RI          (1<<1)          /* Recoverable Exception */
45#define MSR_LE          (1<<0)          /* Little-Endian enable */
46
47#define MSR_            MSR_ME|MSR_RI
48#define MSR_KERNEL      MSR_|MSR_IR|MSR_DR
49#define MSR_USER        MSR_KERNEL|MSR_PR|MSR_EE
50
51/* Bit encodings for Hardware Implementation Register (HID0)
52   on PowerPC 603, 604, etc. processors (not 601). */
53#define HID0_EMCP       (1<<31)         /* Enable Machine Check pin */
54#define HID0_EBA        (1<<29)         /* Enable Bus Address Parity */
55#define HID0_EBD        (1<<28)         /* Enable Bus Data Parity */
56#define HID0_SBCLK      (1<<27)
57#define HID0_EICE       (1<<26)
58#define HID0_ECLK       (1<<25)
59#define HID0_PAR        (1<<24)
60#define HID0_DOZE       (1<<23)
61#define HID0_NAP        (1<<22)
62#define HID0_SLEEP      (1<<21)
63#define HID0_DPM        (1<<20)
64#define HID0_ICE        (1<<15)         /* Instruction Cache Enable */
65#define HID0_DCE        (1<<14)         /* Data Cache Enable */
66#define HID0_ILOCK      (1<<13)         /* Instruction Cache Lock */
67#define HID0_DLOCK      (1<<12)         /* Data Cache Lock */
68#define HID0_ICFI       (1<<11)         /* Instruction Cache Flash Invalidate */
69#define HID0_DCI        (1<<10)         /* Data Cache Invalidate */
70#define HID0_SIED       (1<<7)          /* Serial Instruction Execution [Disable] */
71#define HID0_BHTE       (1<<2)          /* Branch History Table Enable */
72#define HID0_BTCD       (1<<1)          /* Branch target cache disable */
73
74/* fpscr settings */
75#define FPSCR_FX        (1<<31)
76#define FPSCR_FEX       (1<<30)
77
78#define _MACH_prep     1
79#define _MACH_Pmac     2 /* pmac or pmac clone (non-chrp) */
80#define _MACH_chrp     4 /* chrp machine */
81#define _MACH_mbx      8 /* Motorola MBX board */
82#define _MACH_apus    16 /* amiga with phase5 powerup */
83#define _MACH_fads    32 /* Motorola FADS board */
84
85/* see residual.h for these */
86#define _PREP_Motorola 0x01  /* motorola prep */
87#define _PREP_Firm     0x02  /* firmworks prep */
88#define _PREP_IBM      0x00  /* ibm prep */
89#define _PREP_Bull     0x03  /* bull prep */
90
91/* these are arbitrary */
92#define _CHRP_Motorola 0x04  /* motorola chrp, the cobra */
93#define _CHRP_IBM     0x05   /* IBM chrp, the longtrail and longtrail 2 */
94
95#define _GLOBAL(n)\
96        .globl n;\
97n:
98
99#define TBRU    269     /* Time base Upper/Lower (Reading) */
100#define TBRL    268
101#define TBWU    284     /* Time base Upper/Lower (Writing) */
102#define TBWL    285
103#define XER     1
104#define LR      8
105#define CTR     9
106#define HID0    1008    /* Hardware Implementation */
107#define PVR     287     /* Processor Version */
108#define IBAT0U  528     /* Instruction BAT #0 Upper/Lower */
109#define IBAT0L  529
110#define IBAT1U  530     /* Instruction BAT #1 Upper/Lower */
111#define IBAT1L  531
112#define IBAT2U  532     /* Instruction BAT #2 Upper/Lower */
113#define IBAT2L  533
114#define IBAT3U  534     /* Instruction BAT #3 Upper/Lower */
115#define IBAT3L  535
116#define DBAT0U  536     /* Data BAT #0 Upper/Lower */
117#define DBAT0L  537
118#define DBAT1U  538     /* Data BAT #1 Upper/Lower */
119#define DBAT1L  539
120#define DBAT2U  540     /* Data BAT #2 Upper/Lower */
121#define DBAT2L  541
122#define DBAT3U  542     /* Data BAT #3 Upper/Lower */
123#define DBAT3L  543
124#define DMISS   976     /* TLB Lookup/Refresh registers */
125#define DCMP    977
126#define HASH1   978
127#define HASH2   979
128#define IMISS   980
129#define ICMP    981
130#define RPA     982
131#define SDR1    25      /* MMU hash base register */
132#define DAR     19      /* Data Address Register */
133#define SPR0    272     /* Supervisor Private Registers */
134#define SPRG0   272
135#define SPR1    273
136#define SPRG1   273
137#define SPR2    274
138#define SPRG2   274
139#define SPR3    275
140#define SPRG3   275
141#define DSISR   18
142#define SRR0    26      /* Saved Registers (exception) */
143#define SRR1    27
144#define IABR    1010    /* Instruction Address Breakpoint */
145#define DEC     22      /* Decrementer */
146#define EAR     282     /* External Address Register */
147#define L2CR    1017    /* PPC 750 L2 control register */
148
149#define THRM1   1020
150#define THRM2   1021
151#define THRM3   1022
152#define THRM1_TIN 0x1
153#define THRM1_TIV 0x2
154#define THRM1_THRES (0x7f<<2)
155#define THRM1_TID (1<<29)
156#define THRM1_TIE (1<<30)
157#define THRM1_V   (1<<31)
158#define THRM3_E   (1<<31)
159
160/* Segment Registers */
161#define SR0     0
162#define SR1     1
163#define SR2     2
164#define SR3     3
165#define SR4     4
166#define SR5     5
167#define SR6     6
168#define SR7     7
169#define SR8     8
170#define SR9     9
171#define SR10    10
172#define SR11    11
173#define SR12    12
174#define SR13    13
175#define SR14    14
176#define SR15    15
177
178/*
179 *  Routines to access the time base register
180 */
181
182#ifndef ASM
183static inline unsigned long long PPC_Get_timebase_register( void )
184{
185  unsigned long tbr_low;
186  unsigned long tbr_high;
187  unsigned long tbr_high_old;
188  unsigned long long tbr;
189
190  do {
191    asm volatile( "mftbu %0" : "=r" (tbr_high_old));
192    asm volatile( "mftb  %0" : "=r" (tbr_low));
193    asm volatile( "mftbu %0" : "=r" (tbr_high));
194  } while ( tbr_high_old != tbr_high );
195
196  tbr = tbr_high;
197  tbr <<= 32;
198  tbr |= tbr_low;
199  return tbr;
200}
201
202static inline  void PPC_Set_timebase_register (unsigned long long tbr)
203{
204  unsigned long tbr_low;
205  unsigned long tbr_high;
206
207  tbr_low = (tbr & 0xffffffff) ;
208  tbr_high = (tbr >> 32) & 0xffffffff;
209  asm volatile( "mtspr 284, %0" : : "r" (tbr_low));
210  asm volatile( "mtspr 285, %0" : : "r" (tbr_high));
211 
212}
213#endif /* ASM */
214
215#define _CPU_MSR_GET( _msr_value ) \
216  do { \
217    _msr_value = 0; \
218    asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
219  } while (0)
220
221#define _CPU_MSR_SET( _msr_value ) \
222{ asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
223
224#define _CPU_ISR_Disable( _isr_cookie ) \
225  { register unsigned int _disable_mask = MSR_EE; \
226    _isr_cookie = 0; \
227    asm volatile ( \
228        "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
229        "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
230        "0" ((_isr_cookie)), "1" ((_disable_mask)) \
231        ); \
232  }
233
234
235/*
236 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
237 *  This indicates the end of an RTEMS critical section.  The parameter
238 *  _isr_cookie is not modified.
239 */
240
241#define _CPU_ISR_Enable( _isr_cookie )  \
242  { \
243     asm volatile ( "mtmsr %0" : \
244                   "=r" ((_isr_cookie)) : \
245                   "0" ((_isr_cookie))); \
246  }
247
248/*
249 *  This temporarily restores the interrupt to _isr_cookie before immediately
250 *  disabling them again.  This is used to divide long RTEMS critical
251 *  sections into two or more parts.  The parameter _isr_cookie is not
252 *  modified.
253 *
254 *  NOTE:  The version being used is not very optimized but it does
255 *         not trip a problem in gcc where the disable mask does not
256 *         get loaded.  Check this for future (post 10/97 gcc versions.
257 */
258
259#define _CPU_ISR_Flash( _isr_cookie ) \
260  { register unsigned int _disable_mask = MSR_EE; \
261    asm volatile ( \
262      "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \
263      "=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \
264      "0" ((_isr_cookie)), "1" ((_disable_mask)) \
265    ); \
266  }
267
268
269/* end of ISR handler macros */
270
271/*
272 *  Simple spin delay in microsecond units for device drivers.
273 *  This is very dependent on the clock speed of the target.
274 */
275
276#define CPU_Get_timebase_low( _value ) \
277    asm volatile( "mftb  %0" : "=r" (_value) )
278
279#define rtems_bsp_delay( _microseconds ) \
280  do { \
281    unsigned32 start, ticks, now; \
282    CPU_Get_timebase_low( start ) ; \
283    ticks = (_microseconds) * rtems_cpu_configuration_get_clicks_per_usec(); \
284    do \
285      CPU_Get_timebase_low( now ) ; \
286    while (now - start < ticks); \
287  } while (0)
288
289#define rtems_bsp_delay_in_bus_cycles( _cycles ) \
290  do { \
291    unsigned32 start, now; \
292    CPU_Get_timebase_low( start ); \
293    do \
294      CPU_Get_timebase_low( now ); \
295    while (now - start < (_cycles)); \
296  } while (0)
297
298#define PPC_Set_decrementer( _clicks ) \
299  do { \
300    asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
301  } while (0)
302
303#define PPC_Get_decrementer( _clicks ) \
304    asm volatile( "mfdec  %0" : "=r" (_clicks) )
305
306#ifdef __cplusplus
307}
308#endif
309
310#endif /* __PPC_CPU_H */
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