source: rtems/c/src/lib/libcpu/powerpc/shared/include/cpu.h @ abd9401

4.104.114.84.95
Last change on this file since abd9401 was abd9401, checked in by Joel Sherrill <joel.sherrill@…>, on Jun 14, 2000 at 3:38:08 PM

Functionality moved from directory above to accomodate building
shared source code.

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File size: 9.1 KB
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1/*
2 * cpu.h
3 *
4 * This file contains some powerpc MSR and registers access definitions.
5 *
6 * It is a stripped down version of linux ppc processor.h file...
7 *
8 * Copyright (C) 1999  Eric Valette (valette@crf.canon.fr)
9 *                     Canon Centre Recherche France.
10 *
11 *  The license and distribution terms for this file may be
12 *  found in found in the file LICENSE in this distribution or at
13 *  http://www.OARcorp.com/rtems/license.html.
14 *
15 *  $Id$
16 */
17
18#ifndef __PPC_CPU_H
19#define __PPC_CPU_H
20
21#ifdef __cplusplus
22extern "C" {
23#endif
24
25/* Bit encodings for Machine State Register (MSR) */
26#define MSR_POW         (1<<18)         /* Enable Power Management */
27#define MSR_TGPR        (1<<17)         /* TLB Update registers in use */
28#define MSR_ILE         (1<<16)         /* Interrupt Little-Endian enable */
29#define MSR_EE          (1<<15)         /* External Interrupt enable */
30#define MSR_PR          (1<<14)         /* Supervisor/User privilege */
31#define MSR_FP          (1<<13)         /* Floating Point enable */
32#define MSR_ME          (1<<12)         /* Machine Check enable */
33#define MSR_FE0         (1<<11)         /* Floating Exception mode 0 */
34#define MSR_SE          (1<<10)         /* Single Step */
35#define MSR_BE          (1<<9)          /* Branch Trace */
36#define MSR_FE1         (1<<8)          /* Floating Exception mode 1 */
37#define MSR_IP          (1<<6)          /* Exception prefix 0x000/0xFFF */
38#define MSR_IR          (1<<5)          /* Instruction MMU enable */
39#define MSR_DR          (1<<4)          /* Data MMU enable */
40#define MSR_RI          (1<<1)          /* Recoverable Exception */
41#define MSR_LE          (1<<0)          /* Little-Endian enable */
42
43#define MSR_            MSR_ME|MSR_RI
44#define MSR_KERNEL      MSR_|MSR_IR|MSR_DR
45#define MSR_USER        MSR_KERNEL|MSR_PR|MSR_EE
46
47/* Bit encodings for Hardware Implementation Register (HID0)
48   on PowerPC 603, 604, etc. processors (not 601). */
49#define HID0_EMCP       (1<<31)         /* Enable Machine Check pin */
50#define HID0_EBA        (1<<29)         /* Enable Bus Address Parity */
51#define HID0_EBD        (1<<28)         /* Enable Bus Data Parity */
52#define HID0_SBCLK      (1<<27)
53#define HID0_EICE       (1<<26)
54#define HID0_ECLK       (1<<25)
55#define HID0_PAR        (1<<24)
56#define HID0_DOZE       (1<<23)
57#define HID0_NAP        (1<<22)
58#define HID0_SLEEP      (1<<21)
59#define HID0_DPM        (1<<20)
60#define HID0_ICE        (1<<15)         /* Instruction Cache Enable */
61#define HID0_DCE        (1<<14)         /* Data Cache Enable */
62#define HID0_ILOCK      (1<<13)         /* Instruction Cache Lock */
63#define HID0_DLOCK      (1<<12)         /* Data Cache Lock */
64#define HID0_ICFI       (1<<11)         /* Instruction Cache Flash Invalidate */
65#define HID0_DCI        (1<<10)         /* Data Cache Invalidate */
66#define HID0_SIED       (1<<7)          /* Serial Instruction Execution [Disable] */
67#define HID0_BHTE       (1<<2)          /* Branch History Table Enable */
68#define HID0_BTCD       (1<<1)          /* Branch target cache disable */
69
70/* fpscr settings */
71#define FPSCR_FX        (1<<31)
72#define FPSCR_FEX       (1<<30)
73
74#define _MACH_prep     1
75#define _MACH_Pmac     2 /* pmac or pmac clone (non-chrp) */
76#define _MACH_chrp     4 /* chrp machine */
77#define _MACH_mbx      8 /* Motorola MBX board */
78#define _MACH_apus    16 /* amiga with phase5 powerup */
79#define _MACH_fads    32 /* Motorola FADS board */
80
81/* see residual.h for these */
82#define _PREP_Motorola 0x01  /* motorola prep */
83#define _PREP_Firm     0x02  /* firmworks prep */
84#define _PREP_IBM      0x00  /* ibm prep */
85#define _PREP_Bull     0x03  /* bull prep */
86
87/* these are arbitrary */
88#define _CHRP_Motorola 0x04  /* motorola chrp, the cobra */
89#define _CHRP_IBM     0x05   /* IBM chrp, the longtrail and longtrail 2 */
90
91#define _GLOBAL(n)\
92        .globl n;\
93n:
94
95#define TBRU    269     /* Time base Upper/Lower (Reading) */
96#define TBRL    268
97#define TBWU    284     /* Time base Upper/Lower (Writing) */
98#define TBWL    285
99#define XER     1
100#define LR      8
101#define CTR     9
102#define HID0    1008    /* Hardware Implementation */
103#define PVR     287     /* Processor Version */
104#define IBAT0U  528     /* Instruction BAT #0 Upper/Lower */
105#define IBAT0L  529
106#define IBAT1U  530     /* Instruction BAT #1 Upper/Lower */
107#define IBAT1L  531
108#define IBAT2U  532     /* Instruction BAT #2 Upper/Lower */
109#define IBAT2L  533
110#define IBAT3U  534     /* Instruction BAT #3 Upper/Lower */
111#define IBAT3L  535
112#define DBAT0U  536     /* Data BAT #0 Upper/Lower */
113#define DBAT0L  537
114#define DBAT1U  538     /* Data BAT #1 Upper/Lower */
115#define DBAT1L  539
116#define DBAT2U  540     /* Data BAT #2 Upper/Lower */
117#define DBAT2L  541
118#define DBAT3U  542     /* Data BAT #3 Upper/Lower */
119#define DBAT3L  543
120#define DMISS   976     /* TLB Lookup/Refresh registers */
121#define DCMP    977
122#define HASH1   978
123#define HASH2   979
124#define IMISS   980
125#define ICMP    981
126#define RPA     982
127#define SDR1    25      /* MMU hash base register */
128#define DAR     19      /* Data Address Register */
129#define SPR0    272     /* Supervisor Private Registers */
130#define SPRG0   272
131#define SPR1    273
132#define SPRG1   273
133#define SPR2    274
134#define SPRG2   274
135#define SPR3    275
136#define SPRG3   275
137#define DSISR   18
138#define SRR0    26      /* Saved Registers (exception) */
139#define SRR1    27
140#define IABR    1010    /* Instruction Address Breakpoint */
141#define DEC     22      /* Decrementer */
142#define EAR     282     /* External Address Register */
143#define L2CR    1017    /* PPC 750 L2 control register */
144
145#define THRM1   1020
146#define THRM2   1021
147#define THRM3   1022
148#define THRM1_TIN 0x1
149#define THRM1_TIV 0x2
150#define THRM1_THRES (0x7f<<2)
151#define THRM1_TID (1<<29)
152#define THRM1_TIE (1<<30)
153#define THRM1_V   (1<<31)
154#define THRM3_E   (1<<31)
155
156/* Segment Registers */
157#define SR0     0
158#define SR1     1
159#define SR2     2
160#define SR3     3
161#define SR4     4
162#define SR5     5
163#define SR6     6
164#define SR7     7
165#define SR8     8
166#define SR9     9
167#define SR10    10
168#define SR11    11
169#define SR12    12
170#define SR13    13
171#define SR14    14
172#define SR15    15
173
174#ifndef ASM
175typedef enum {
176  PPC_601       = 0x1,
177  PPC_603       = 0x3,
178  PPC_604       = 0x4,
179  PPC_603e      = 0x6,
180  PPC_603ev     = 0x7,
181  PPC_750       = 0x8,
182  PPC_604e      = 0x9,
183  PPC_604r      = 0xA,
184  PPC_620       = 0x16,
185  PPC_860       = 0x50,
186  PPC_821       = PPC_860,
187  PPC_UNKNOWN   = 0xff
188} ppc_cpu_id_t;
189
190typedef unsigned short ppc_cpu_revision_t;
191
192extern ppc_cpu_id_t get_ppc_cpu_type();
193extern ppc_cpu_id_t current_ppc_cpu;
194extern ppc_cpu_revision_t get_ppc_cpu_revision();
195extern ppc_cpu_revision_t current_ppc_revision;
196/*
197 *  Routines to access the time base register
198 */
199
200static inline unsigned long long PPC_Get_timebase_register( void )
201{
202  unsigned long tbr_low;
203  unsigned long tbr_high;
204  unsigned long tbr_high_old;
205  unsigned long long tbr;
206
207  do {
208    asm volatile( "mftbu %0" : "=r" (tbr_high_old));
209    asm volatile( "mftb  %0" : "=r" (tbr_low));
210    asm volatile( "mftbu %0" : "=r" (tbr_high));
211  } while ( tbr_high_old != tbr_high );
212
213  tbr = tbr_high;
214  tbr <<= 32;
215  tbr |= tbr_low;
216  return tbr;
217}
218
219static inline  void PPC_Set_timebase_register (unsigned long long tbr)
220{
221  unsigned long tbr_low;
222  unsigned long tbr_high;
223
224  tbr_low = (tbr & 0xffffffff) ;
225  tbr_high = (tbr >> 32) & 0xffffffff;
226  asm volatile( "mtspr 284, %0" : : "r" (tbr_low));
227  asm volatile( "mtspr 285, %0" : : "r" (tbr_high));
228 
229}
230#endif
231
232#define _CPU_MSR_GET( _msr_value ) \
233  do { \
234    _msr_value = 0; \
235    asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
236  } while (0)
237
238#define _CPU_MSR_SET( _msr_value ) \
239{ asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
240
241#define _CPU_ISR_Disable( _isr_cookie ) \
242  { register unsigned int _disable_mask = MSR_EE; \
243    _isr_cookie = 0; \
244    asm volatile ( \
245        "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
246        "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
247        "0" ((_isr_cookie)), "1" ((_disable_mask)) \
248        ); \
249  }
250
251
252/*
253 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
254 *  This indicates the end of an RTEMS critical section.  The parameter
255 *  _isr_cookie is not modified.
256 */
257
258#define _CPU_ISR_Enable( _isr_cookie )  \
259  { \
260     asm volatile ( "mtmsr %0" : \
261                   "=r" ((_isr_cookie)) : \
262                   "0" ((_isr_cookie))); \
263  }
264
265/*
266 *  This temporarily restores the interrupt to _isr_cookie before immediately
267 *  disabling them again.  This is used to divide long RTEMS critical
268 *  sections into two or more parts.  The parameter _isr_cookie is not
269 *  modified.
270 *
271 *  NOTE:  The version being used is not very optimized but it does
272 *         not trip a problem in gcc where the disable mask does not
273 *         get loaded.  Check this for future (post 10/97 gcc versions.
274 */
275
276#define _CPU_ISR_Flash( _isr_cookie ) \
277  { register unsigned int _disable_mask = MSR_EE; \
278    asm volatile ( \
279      "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \
280      "=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \
281      "0" ((_isr_cookie)), "1" ((_disable_mask)) \
282    ); \
283  }
284
285
286/* end of ISR handler macros */
287
288/*
289 *  Simple spin delay in microsecond units for device drivers.
290 *  This is very dependent on the clock speed of the target.
291 */
292
293#define CPU_Get_timebase_low( _value ) \
294    asm volatile( "mftb  %0" : "=r" (_value) )
295
296#define delay( _microseconds ) \
297  do { \
298    unsigned32 start, ticks, now; \
299    CPU_Get_timebase_low( start ) ; \
300    ticks = (_microseconds) * rtems_cpu_configuration_get_clicks_per_usec(); \
301    do \
302      CPU_Get_timebase_low( now ) ; \
303    while (now - start < ticks); \
304  } while (0)
305
306#define delay_in_bus_cycles( _cycles ) \
307  do { \
308    unsigned32 start, now; \
309    CPU_Get_timebase_low( start ); \
310    do \
311      CPU_Get_timebase_low( now ); \
312    while (now - start < (_cycles)); \
313  } while (0)
314
315#define PPC_Set_decrementer( _clicks ) \
316  do { \
317    asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
318  } while (0)
319
320
321#ifdef __cplusplus
322}
323#endif
324
325#endif /* __PPC_CPU_H */
326
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