source: rtems/c/src/lib/libcpu/powerpc/shared/cpu.h @ fcee56c0

4.104.114.84.95
Last change on this file since fcee56c0 was fcee56c0, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 1, 1999 at 11:39:13 PM

Patch from Eric Valette <valette@…> to clean up the
previous submission.

  • Property mode set to 100644
File size: 8.1 KB
Line 
1/*
2 * cpu.h
3 *
4 *          This file contains some powerpc MSR and registers access definitions.
5 *
6 * It is a stripped down version of linux ppc processor.h file...
7 *
8 * Copyright (C) 1999  Eric Valette (valette@crf.canon.fr)
9 *                     Canon Centre Recherche France.
10 *
11 *  The license and distribution terms for this file may be
12 *  found in found in the file LICENSE in this distribution or at
13 *  http://www.OARcorp.com/rtems/license.html.
14 *
15 *  $Id$
16 */
17
18#ifndef __ASM_PPC_PROCESSOR_H
19#define __ASM_PPC_PROCESSOR_H
20
21#include <bsp/residual.h>
22
23/* Bit encodings for Machine State Register (MSR) */
24#define MSR_POW         (1<<18)         /* Enable Power Management */
25#define MSR_TGPR        (1<<17)         /* TLB Update registers in use */
26#define MSR_ILE         (1<<16)         /* Interrupt Little-Endian enable */
27#define MSR_EE          (1<<15)         /* External Interrupt enable */
28#define MSR_PR          (1<<14)         /* Supervisor/User privilege */
29#define MSR_FP          (1<<13)         /* Floating Point enable */
30#define MSR_ME          (1<<12)         /* Machine Check enable */
31#define MSR_FE0         (1<<11)         /* Floating Exception mode 0 */
32#define MSR_SE          (1<<10)         /* Single Step */
33#define MSR_BE          (1<<9)          /* Branch Trace */
34#define MSR_FE1         (1<<8)          /* Floating Exception mode 1 */
35#define MSR_IP          (1<<6)          /* Exception prefix 0x000/0xFFF */
36#define MSR_IR          (1<<5)          /* Instruction MMU enable */
37#define MSR_DR          (1<<4)          /* Data MMU enable */
38#define MSR_RI          (1<<1)          /* Recoverable Exception */
39#define MSR_LE          (1<<0)          /* Little-Endian enable */
40
41#define MSR_            MSR_ME|MSR_RI
42#define MSR_KERNEL      MSR_|MSR_IR|MSR_DR
43#define MSR_USER        MSR_KERNEL|MSR_PR|MSR_EE
44
45/* Bit encodings for Hardware Implementation Register (HID0)
46   on PowerPC 603, 604, etc. processors (not 601). */
47#define HID0_EMCP       (1<<31)         /* Enable Machine Check pin */
48#define HID0_EBA        (1<<29)         /* Enable Bus Address Parity */
49#define HID0_EBD        (1<<28)         /* Enable Bus Data Parity */
50#define HID0_SBCLK      (1<<27)
51#define HID0_EICE       (1<<26)
52#define HID0_ECLK       (1<<25)
53#define HID0_PAR        (1<<24)
54#define HID0_DOZE       (1<<23)
55#define HID0_NAP        (1<<22)
56#define HID0_SLEEP      (1<<21)
57#define HID0_DPM        (1<<20)
58#define HID0_ICE        (1<<15)         /* Instruction Cache Enable */
59#define HID0_DCE        (1<<14)         /* Data Cache Enable */
60#define HID0_ILOCK      (1<<13)         /* Instruction Cache Lock */
61#define HID0_DLOCK      (1<<12)         /* Data Cache Lock */
62#define HID0_ICFI       (1<<11)         /* Instruction Cache Flash Invalidate */
63#define HID0_DCI        (1<<10)         /* Data Cache Invalidate */
64#define HID0_SIED       (1<<7)          /* Serial Instruction Execution [Disable] */
65#define HID0_BHTE       (1<<2)          /* Branch History Table Enable */
66#define HID0_BTCD       (1<<1)          /* Branch target cache disable */
67
68/* fpscr settings */
69#define FPSCR_FX        (1<<31)
70#define FPSCR_FEX       (1<<30)
71
72#define _MACH_prep     1
73#define _MACH_Pmac     2 /* pmac or pmac clone (non-chrp) */
74#define _MACH_chrp     4 /* chrp machine */
75#define _MACH_mbx      8 /* Motorola MBX board */
76#define _MACH_apus    16 /* amiga with phase5 powerup */
77#define _MACH_fads    32 /* Motorola FADS board */
78
79/* see residual.h for these */
80#define _PREP_Motorola 0x01  /* motorola prep */
81#define _PREP_Firm     0x02  /* firmworks prep */
82#define _PREP_IBM      0x00  /* ibm prep */
83#define _PREP_Bull     0x03  /* bull prep */
84
85/* these are arbitrary */
86#define _CHRP_Motorola 0x04  /* motorola chrp, the cobra */
87#define _CHRP_IBM     0x05   /* IBM chrp, the longtrail and longtrail 2 */
88
89#define _GLOBAL(n)\
90        .globl n;\
91n:
92
93#define TBRU    269     /* Time base Upper/Lower (Reading) */
94#define TBRL    268
95#define TBWU    284     /* Time base Upper/Lower (Writing) */
96#define TBWL    285
97#define XER     1
98#define LR      8
99#define CTR     9
100#define HID0    1008    /* Hardware Implementation */
101#define PVR     287     /* Processor Version */
102#define IBAT0U  528     /* Instruction BAT #0 Upper/Lower */
103#define IBAT0L  529
104#define IBAT1U  530     /* Instruction BAT #1 Upper/Lower */
105#define IBAT1L  531
106#define IBAT2U  532     /* Instruction BAT #2 Upper/Lower */
107#define IBAT2L  533
108#define IBAT3U  534     /* Instruction BAT #3 Upper/Lower */
109#define IBAT3L  535
110#define DBAT0U  536     /* Data BAT #0 Upper/Lower */
111#define DBAT0L  537
112#define DBAT1U  538     /* Data BAT #1 Upper/Lower */
113#define DBAT1L  539
114#define DBAT2U  540     /* Data BAT #2 Upper/Lower */
115#define DBAT2L  541
116#define DBAT3U  542     /* Data BAT #3 Upper/Lower */
117#define DBAT3L  543
118#define DMISS   976     /* TLB Lookup/Refresh registers */
119#define DCMP    977
120#define HASH1   978
121#define HASH2   979
122#define IMISS   980
123#define ICMP    981
124#define RPA     982
125#define SDR1    25      /* MMU hash base register */
126#define DAR     19      /* Data Address Register */
127#define SPR0    272     /* Supervisor Private Registers */
128#define SPRG0   272
129#define SPR1    273
130#define SPRG1   273
131#define SPR2    274
132#define SPRG2   274
133#define SPR3    275
134#define SPRG3   275
135#define DSISR   18
136#define SRR0    26      /* Saved Registers (exception) */
137#define SRR1    27
138#define IABR    1010    /* Instruction Address Breakpoint */
139#define DEC     22      /* Decrementer */
140#define EAR     282     /* External Address Register */
141#define L2CR    1017    /* PPC 750 L2 control register */
142
143#define THRM1   1020
144#define THRM2   1021
145#define THRM3   1022
146#define THRM1_TIN 0x1
147#define THRM1_TIV 0x2
148#define THRM1_THRES (0x7f<<2)
149#define THRM1_TID (1<<29)
150#define THRM1_TIE (1<<30)
151#define THRM1_V   (1<<31)
152#define THRM3_E   (1<<31)
153
154/* Segment Registers */
155#define SR0     0
156#define SR1     1
157#define SR2     2
158#define SR3     3
159#define SR4     4
160#define SR5     5
161#define SR6     6
162#define SR7     7
163#define SR8     8
164#define SR9     9
165#define SR10    10
166#define SR11    11
167#define SR12    12
168#define SR13    13
169#define SR14    14
170#define SR15    15
171
172#define _CPU_MSR_GET( _msr_value ) \
173  do { \
174    _msr_value = 0; \
175    asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
176  } while (0)
177
178#define _CPU_MSR_SET( _msr_value ) \
179{ asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
180
181#define _CPU_ISR_Disable( _isr_cookie ) \
182  { register unsigned int _disable_mask = MSR_EE; \
183    _isr_cookie = 0; \
184    asm volatile ( \
185        "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
186        "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
187        "0" ((_isr_cookie)), "1" ((_disable_mask)) \
188        ); \
189  }
190
191
192#define _CPU_Data_Cache_Block_Flush( _address ) \
193  do { register void *__address = (_address); \
194       register unsigned32 _zero = 0; \
195       asm volatile ( "dcbf %0,%1" : \
196                      "=r" (_zero), "=r" (__address) : \
197                      "0" (_zero), "1" (__address) \
198       ); \
199  } while (0)
200
201
202/*
203 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
204 *  This indicates the end of an RTEMS critical section.  The parameter
205 *  _isr_cookie is not modified.
206 */
207
208#define _CPU_ISR_Enable( _isr_cookie )  \
209  { \
210     asm volatile ( "mtmsr %0" : \
211                   "=r" ((_isr_cookie)) : \
212                   "0" ((_isr_cookie))); \
213  }
214
215/*
216 *  This temporarily restores the interrupt to _isr_cookie before immediately
217 *  disabling them again.  This is used to divide long RTEMS critical
218 *  sections into two or more parts.  The parameter _isr_cookie is not
219 *  modified.
220 *
221 *  NOTE:  The version being used is not very optimized but it does
222 *         not trip a problem in gcc where the disable mask does not
223 *         get loaded.  Check this for future (post 10/97 gcc versions.
224 */
225
226#define _CPU_ISR_Flash( _isr_cookie ) \
227  { register unsigned int _disable_mask = MSR_EE; \
228    asm volatile ( \
229      "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \
230      "=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \
231      "0" ((_isr_cookie)), "1" ((_disable_mask)) \
232    ); \
233  }
234
235
236/* end of ISR handler macros */
237
238/*
239 *  Simple spin delay in microsecond units for device drivers.
240 *  This is very dependent on the clock speed of the target.
241 */
242
243#define CPU_Get_timebase_low( _value ) \
244    asm volatile( "mftb  %0" : "=r" (_value) )
245
246#define delay( _microseconds ) \
247  do { \
248    unsigned32 start, ticks, now; \
249    CPU_Get_timebase_low( start ) ; \
250    ticks = (_microseconds) * Cpu_table.clicks_per_usec; \
251    do \
252      CPU_Get_timebase_low( now ) ; \
253    while (now - start < ticks); \
254  } while (0)
255
256#define delay_in_bus_cycles( _cycles ) \
257  do { \
258    unsigned32 start, now; \
259    CPU_Get_timebase_low( start ); \
260    do \
261      CPU_Get_timebase_low( now ); \
262    while (now - start < (_cycles)); \
263  } while (0)
264
265#define PPC_Set_decrementer( _clicks ) \
266  do { \
267    asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
268  } while (0)
269
270#endif /* __ASM_PPC_PROCESSOR_H */
271
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