source: rtems/c/src/lib/libcpu/powerpc/shared/cpu.h @ a4f6b02

4.104.114.84.95
Last change on this file since a4f6b02 was a4f6b02, checked in by Joel Sherrill <joel.sherrill@…>, on Jun 14, 1999 at 5:54:21 PM

This is a large patch from Eric Valette <valette@…> that was
described in the message following this paragraph. This patch also includes
a mcp750 BSP.

From valette@… Mon Jun 14 10:03:08 1999
Date: Tue, 18 May 1999 01:30:14 +0200 (CEST)
From: VALETTE Eric <valette@…>
To: joel@…
Cc: raguet@…, rtems-snapshots@…, valette@…
Subject: Questions/Suggestion? regarding RTEMS PowerPC code (long)

Dear knowledgeable RTEMS powerpc users,

As some of you may know, I'm currently finalizing a port
of RTEMS on a MCP750 Motorola board. I have done most
of it but have some questions to ask before submitting
the port.

In order to understand some of the changes I have made
or would like to make, maybe it is worth describing the
MCP750 Motorola board.

the MCP750 is a COMPACT PCI powerpc board with :

1) a MPC750 233 MHz processor,
2) a raven bus bridge/PCI controller that
implement an OPENPIC compliant interrupt controller,
3) a VIA 82C586 PCI/ISA bridge that offers a PC
compliant IO for keyboard, serial line, IDE, and
the well known PC 8259 cascaded PIC interrupt
architecture model,
4) a DEC 21140 Ethernet controller,
5) the PPCBUG Motorola firmware in flash,
6) A DEC PCI bridge,

This architecture is common to most Motorola 60x/7xx
board except that :

1) on VME board, the DEC PCI bridge is replaced by
a VME chipset,
2) the VIA 82C586 PCI/ISA bridge is replaced by
another bridge that is almost fully compatible
with the via bridge...

So the port should be a rather close basis for many
60x/7xx motorola board...

On this board, I already have ported Linux 2.2.3 and
use it both as a development and target board.

Now the questions/suggestions I have :

1) EXCEPTION CODE


As far as I know exceptions on PPC are handled like
interrupts. I dislike this very much as :

a) Except for the decrementer exception (and
maybe some other on mpc8xx), exceptions are
not recoverable and the handler just need to print
the full context and go to the firmware or debugger...
b) The interrupt switch is only necessary for the
decrementer and external interrupt (at least on
6xx,7xx).
c) The full context for exception is never saved and
thus cannot be used by debugger... I do understand
the most important for interrupts low level code
is to save the minimal context enabling to call C
code for performance reasons. On non recoverable
exception on the other hand, the most important is
to save the maximum information concerning proc status
in order to analyze the reason of the fault. At
least we will need this in order to implement the
port of RGDB on PPC

==> I wrote an API for connecting raw exceptions (and thus
raw interrupts) for mpc750. It should be valid for most
powerpc processors... I hope to find a way to make this coexist
with actual code layout. The code is actually located
in lib/libcpu/powerpc/mpc750 and is thus optional
(provided I write my own version of exec/score/cpu/powerpc/cpu.c ...)

See remark about files/directory layout organization in 4)

2) Current Implementation of ISR low level code


I do not understand why the MSR EE flags is cleared
again in exec/score/cpu/powerpc/irq_stubs.S

#if (PPC_USE_SPRG)

mfmsr r5
mfspr r6, sprg2

#else

lwz r6,msr_initial(r11)
lis r5,~PPC_MSR_DISABLE_MASK@ha
ori r5,r5,~PPC_MSR_DISABLE_MASK@l
and r6,r6,r5
mfmsr r5

#endif

Reading the doc, when a decrementer interrupt or an
external interrupt is active, the MSR EE flag is already
cleared. BTW if exception/interrupt could occur, it would
trash SRR0 and SRR1. In fact the code may be useful to set
MSR[RI] that re-enables exception processing. BTW I will need
to set other value in MSR to handle interrupts :

a) I want the MSR[IR] and MSR[DR] to be set for
performance reasons and also because I need DBAT
support to have access to PCI memory space as the
interrupt controller is in the PCI space.

Reading the code, I see others have the same kind of request :

/* SCE 980217

*

  • We need address translation ON when we call our ISR routine

mtmsr r5

*/

This is just another prof that even the lowest level
IRQ code is fundamentally board dependent and
not simply processor dependent especially when
the processor use external interrupt controller
because it has a single interrupt request line...

Note that if you look at the PPC code high level interrupt
handling code, as the "set_vector" routine that really connects
the interrupt is in the BSP/startup/genpvec.c,
the fact that IRQ handling is BSP specific is DE-FACTO
acknowledged.

I know I have already expressed this and understand that this
would require some heavy change in the code but believe
me you will reach a point where you will not be able
to find a compatible while optimum implementation for low level
interrupt handling code...) In my case this is already true...

So please consider removing low level IRQ handling from
exec/score/cpu/* and only let there exception handling code...
Exceptions are usually only processor dependent and do
not depend on external hardware mechanism to be masked or
acknowledged or re-enabled (there are probably exception but ...)

I have already done this for pc386 bsp but need to make it again.
This time I will even propose an API.

3) R2/R13 manipulation for EABI implementation


I do not understand the handling of r2 and r13 in the
EABI case. The specification for r2 says pointer to sdata2,
sbss2 section => constant. However I do not see -ffixed-r2
passed to any compilation system in make/custom/*
(for info linux does this on PPC).

So either this is a default compiler option when choosing
powerpc-rtems and thus we do not need to do anything with
this register as all the code is compiled with this compiler
and linked together OR this register may be used by rtems code
and then we do not need any special initialization or
handling.

The specification for r13 says pointer to the small data
area. r13 argumentation is the same except that as far
as I know the usage of the small data area requires
specific compiler support so that access to variables is
compiled via loading the LSB in a register and then
using r13 to get full address... It is like a small
memory model and it was present in IBM C compilers.

=> I propose to suppress any specific code for r2 and
r13 in the EABI case.

4) Code layout organization (yes again :-))


I think there are a number of design flaws in the way
the code is for ppc organized and I will try to point them out.
I have been beaten by this again on this new port, and
was beaten last year while modifying code for pc386.

a) exec/score/cpu/* vs lib/libcpu/cpu/*.

I think that too many things are put in exec/score/cpu that
have nothing to do with RTEMS internals but are rather
related to CPU feature.

This include at least :

a) registers access routine (e.g GET_MSR_Value),
b) interrupt masking/unmasking routines,
c) cache_mngt_routine,
d) mmu_mngt_routine,
e) Routines to connect the raw_exception, raw_interrupt
handler,

b) lib/libcpu/cpu/powerpc/*

With a processor family as exuberant as the powerpc family,
and their well known subtle differences (604 vs 750) or
unfortunately majors (8xx vs 60x) the directory structure
is fine (except maybe the names that are not homogeneous)

powerpc

ppc421 mpc821 ...

I only needed to add mpc750. But the fact that libcpu.a was not
produced was a pain and the fact that this organization may
duplicates code is also problematic.

So, except if the support of automake provides a better solution
I would like to propose something like this :

powerpc

mpc421 mpc821 ... mpc750 shared wrapup

with the following rules :

a) "shared" would act as a source container for sources that may
be shared among processors. Needed files would be compiled inside
the processor specific directory using the vpath Makefile
mechanism. "shared" may also contain compilation code
for routine that are really shared and not worth to inline...
(did not found many things so far as registers access routine
ARE WORTH INLINING)... In the case something is compiled there,
it should create libcpushared.a

b) layout under processor specific directory is free provided
that

1)the result of the compilation process exports :

libcpu/powerpc/"PROC"/*.h in $(PROJECT_INCLUDE)/libcpu

2) each processor specific directory creates
a library called libcpuspecific.a

Note that this organization enables to have a file that
is nearly the same than in shared but that must differ
because of processor differences...

c) "wrapup" should create libcpu.a using libcpushared.a
libcpuspecific.a and export it $(PROJECT_INCLUDE)/libcpu

The only thing I have no ideal solution is the way to put shared
definitions in "shared" and only processor specific definition
in "proc". To give a concrete example, most MSR bit definition
are shared among PPC processors and only some differs. if we create
a single msr.h in shared it will have ifdef. If in msr.h we
include libcpu/msr_c.h we will need to have it in each prowerpc
specific directory (even empty). Opinions are welcomed ...

Note that a similar mechanism exist in libbsp/i386 that also
contains a shared directory that is used by several bsp
like pc386 and i386ex and a similar wrapup mechanism...

NB: I have done this for mpc750 and other processors could just use
similar Makefiles...

c) The exec/score/cpu/powerpc directory layout.

I think the directory layout should be the same than the
libcpu/powerpc. As it is not, there are a lot of ifdefs
inside the code... And of course low level interrupt handling
code should be removed...

Besides that I do not understand why

1) things are compiled in the wrap directory,
2) some includes are moved to rtems/score,

I think the "preinstall" mechanism enables to put
everything in the current directory (or better in a per processor
directory),

5) Interrupt handling API


Again :-). But I think that using all the features the PIC
offers is a MUST for RT system. I already explained in the
prologue of this (long and probably boring) mail that the MCP750
boards offers an OPENPIC compliant architecture and that
the VIA 82586 PCI/ISA bridge offers a PC compatible IO and
PIC mapping. Here is a logical view of the RAVEN/VIA 82586
interrupt mapping :


| OPEN | <-----|8259|
| PIC | | | 2 ------
|(RAVEN)| | | <-----|8259|
| | | | | | 11
| | | | | | <----
| | | | | |
| | | | | |


------
| VIA PCI/ISA bridge
| x
-------- PCI interrupts

OPENPIC offers interrupt priorities among PCI interrupts
and interrupt selective masking. The 8259 offers the same kind
of feature. With actual powerpc interrupt code :

1) there is no way to specify priorities among
interrupts handler. This is REALLY a bad thing.
For me it is as importnat as having priorities
for threads...
2) for my implementation, each ISR should
contain the code that acknowledge the RAVEN
and 8259 cascade, modify interrupt mask on both
chips, and reenable interrupt at processor level,
..., restore then on interrupt return,.... This code
is actually similar to code located in some
genpvec.c powerpc files,
3) I must update _ISR_Nesting_level because
irq.inl use it...
4) the libchip code connects the ISR via set_vector
but the libchip handler code does not contain any code to
manipulate external interrupt controller hardware
in order to acknoledge the interrupt or re-enable
them (except for the target hardware of course)
So this code is broken unless set_vector adds an
additionnal prologue/epilogue before calling/returning
from in order to acknoledge/mask the raven and the
8259 PICS... => Anyway already EACH BSP MUST REWRITE
PART OF INTERRUPT HANDLING CODE TO CORRECTLY IMPLEMENT
SET_VECTOR.

I would rather offer an API similar to the one provided
in libbsp/i386/shared/irq/irq.h so that :

1) Once the driver supplied methods is called the
only things the ISR has to do is to worry about the
external hardware that triggered the interrupt.
Everything on openpic/VIA/processor would have been
done by the low levels (same things as set-vector)
2) The caller will need to supply the on/off/isOn
routine that are fundamental to correctly implements
debuggers/performance monitoring is a portable way
3) A globally configurable interrupt priorities
mechanism...

I have nothing against providing a compatible
set_vector just to make libchip happy but
as I have already explained in other
mails (months ago), I really think that the ISR
connection should be handled by the BSP and that no
code containing irq connection should exist the
rtems generic layers... Thus I really dislike
libchip on this aspect because in a long term
it will force to adopt the less reach API
for interrupt handling that exists (set_vector).

Additional note : I think the _ISR_Is_in_progress()
inline routine should be :

1) Put in a processor specific section,
2) Should not rely on a global variable,

As :

a) on symmetric MP, there is one interrupt level
per CPU,
b) On processor that have an ISP (e,g 68040),
this variable is useless (MSR bit testing could
be used)
c) On PPC, instead of using the address of the
variable via CPU_IRQ_info.Nest_level a dedicated
SPR could be used.

NOTE: most of this is also true for _Thread_Dispatch_disable_level

END NOTE


Please do not take what I said in the mail as a criticism for
anyone who submitted ppc code. Any code present helped me
a lot understanding PPC behavior. I just wanted by this
mail to :

1) try to better understand the actual code,
2) propose concrete ways of enhancing current code
by providing an alternative implementation for MCP750. I
will make my best effort to try to brake nothing but this
is actually hard due to the file layout organisation.
3) make understandable some changes I will probably make
if joel let me do them :-)

Any comments/objections are welcomed as usual.

--


/ ` Eric Valette

/-- o _. Canon CRF

(_, / (_(_( Rue de la touche lambert

35517 Cesson-Sevigne Cedex
FRANCE

Tel: +33 (0)2 99 87 68 91 Fax: +33 (0)2 99 84 11 30
E-mail: valette@…

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Line 
1#ifndef __ASM_PPC_PROCESSOR_H
2#define __ASM_PPC_PROCESSOR_H
3
4#include <bsp/residual.h>
5
6/* Bit encodings for Machine State Register (MSR) */
7#define MSR_POW         (1<<18)         /* Enable Power Management */
8#define MSR_TGPR        (1<<17)         /* TLB Update registers in use */
9#define MSR_ILE         (1<<16)         /* Interrupt Little-Endian enable */
10#define MSR_EE          (1<<15)         /* External Interrupt enable */
11#define MSR_PR          (1<<14)         /* Supervisor/User privilege */
12#define MSR_FP          (1<<13)         /* Floating Point enable */
13#define MSR_ME          (1<<12)         /* Machine Check enable */
14#define MSR_FE0         (1<<11)         /* Floating Exception mode 0 */
15#define MSR_SE          (1<<10)         /* Single Step */
16#define MSR_BE          (1<<9)          /* Branch Trace */
17#define MSR_FE1         (1<<8)          /* Floating Exception mode 1 */
18#define MSR_IP          (1<<6)          /* Exception prefix 0x000/0xFFF */
19#define MSR_IR          (1<<5)          /* Instruction MMU enable */
20#define MSR_DR          (1<<4)          /* Data MMU enable */
21#define MSR_RI          (1<<1)          /* Recoverable Exception */
22#define MSR_LE          (1<<0)          /* Little-Endian enable */
23
24#define MSR_            MSR_ME|MSR_RI
25#define MSR_KERNEL      MSR_|MSR_IR|MSR_DR
26#define MSR_USER        MSR_KERNEL|MSR_PR|MSR_EE
27
28/* Bit encodings for Hardware Implementation Register (HID0)
29   on PowerPC 603, 604, etc. processors (not 601). */
30#define HID0_EMCP       (1<<31)         /* Enable Machine Check pin */
31#define HID0_EBA        (1<<29)         /* Enable Bus Address Parity */
32#define HID0_EBD        (1<<28)         /* Enable Bus Data Parity */
33#define HID0_SBCLK      (1<<27)
34#define HID0_EICE       (1<<26)
35#define HID0_ECLK       (1<<25)
36#define HID0_PAR        (1<<24)
37#define HID0_DOZE       (1<<23)
38#define HID0_NAP        (1<<22)
39#define HID0_SLEEP      (1<<21)
40#define HID0_DPM        (1<<20)
41#define HID0_ICE        (1<<15)         /* Instruction Cache Enable */
42#define HID0_DCE        (1<<14)         /* Data Cache Enable */
43#define HID0_ILOCK      (1<<13)         /* Instruction Cache Lock */
44#define HID0_DLOCK      (1<<12)         /* Data Cache Lock */
45#define HID0_ICFI       (1<<11)         /* Instruction Cache Flash Invalidate */
46#define HID0_DCI        (1<<10)         /* Data Cache Invalidate */
47#define HID0_SIED       (1<<7)          /* Serial Instruction Execution [Disable] */
48#define HID0_BHTE       (1<<2)          /* Branch History Table Enable */
49#define HID0_BTCD       (1<<1)          /* Branch target cache disable */
50
51/* fpscr settings */
52#define FPSCR_FX        (1<<31)
53#define FPSCR_FEX       (1<<30)
54
55#define _MACH_prep     1
56#define _MACH_Pmac     2 /* pmac or pmac clone (non-chrp) */
57#define _MACH_chrp     4 /* chrp machine */
58#define _MACH_mbx      8 /* Motorola MBX board */
59#define _MACH_apus    16 /* amiga with phase5 powerup */
60#define _MACH_fads    32 /* Motorola FADS board */
61
62/* see residual.h for these */
63#define _PREP_Motorola 0x01  /* motorola prep */
64#define _PREP_Firm     0x02  /* firmworks prep */
65#define _PREP_IBM      0x00  /* ibm prep */
66#define _PREP_Bull     0x03  /* bull prep */
67
68/* these are arbitrary */
69#define _CHRP_Motorola 0x04  /* motorola chrp, the cobra */
70#define _CHRP_IBM     0x05   /* IBM chrp, the longtrail and longtrail 2 */
71
72#define _GLOBAL(n)\
73        .globl n;\
74n:
75
76#define TBRU    269     /* Time base Upper/Lower (Reading) */
77#define TBRL    268
78#define TBWU    284     /* Time base Upper/Lower (Writing) */
79#define TBWL    285
80#define XER     1
81#define LR      8
82#define CTR     9
83#define HID0    1008    /* Hardware Implementation */
84#define PVR     287     /* Processor Version */
85#define IBAT0U  528     /* Instruction BAT #0 Upper/Lower */
86#define IBAT0L  529
87#define IBAT1U  530     /* Instruction BAT #1 Upper/Lower */
88#define IBAT1L  531
89#define IBAT2U  532     /* Instruction BAT #2 Upper/Lower */
90#define IBAT2L  533
91#define IBAT3U  534     /* Instruction BAT #3 Upper/Lower */
92#define IBAT3L  535
93#define DBAT0U  536     /* Data BAT #0 Upper/Lower */
94#define DBAT0L  537
95#define DBAT1U  538     /* Data BAT #1 Upper/Lower */
96#define DBAT1L  539
97#define DBAT2U  540     /* Data BAT #2 Upper/Lower */
98#define DBAT2L  541
99#define DBAT3U  542     /* Data BAT #3 Upper/Lower */
100#define DBAT3L  543
101#define DMISS   976     /* TLB Lookup/Refresh registers */
102#define DCMP    977
103#define HASH1   978
104#define HASH2   979
105#define IMISS   980
106#define ICMP    981
107#define RPA     982
108#define SDR1    25      /* MMU hash base register */
109#define DAR     19      /* Data Address Register */
110#define SPR0    272     /* Supervisor Private Registers */
111#define SPRG0   272
112#define SPR1    273
113#define SPRG1   273
114#define SPR2    274
115#define SPRG2   274
116#define SPR3    275
117#define SPRG3   275
118#define DSISR   18
119#define SRR0    26      /* Saved Registers (exception) */
120#define SRR1    27
121#define IABR    1010    /* Instruction Address Breakpoint */
122#define DEC     22      /* Decrementer */
123#define EAR     282     /* External Address Register */
124#define L2CR    1017    /* PPC 750 L2 control register */
125
126#define THRM1   1020
127#define THRM2   1021
128#define THRM3   1022
129#define THRM1_TIN 0x1
130#define THRM1_TIV 0x2
131#define THRM1_THRES (0x7f<<2)
132#define THRM1_TID (1<<29)
133#define THRM1_TIE (1<<30)
134#define THRM1_V   (1<<31)
135#define THRM3_E   (1<<31)
136
137/* Segment Registers */
138#define SR0     0
139#define SR1     1
140#define SR2     2
141#define SR3     3
142#define SR4     4
143#define SR5     5
144#define SR6     6
145#define SR7     7
146#define SR8     8
147#define SR9     9
148#define SR10    10
149#define SR11    11
150#define SR12    12
151#define SR13    13
152#define SR14    14
153#define SR15    15
154
155#define _CPU_MSR_GET( _msr_value ) \
156  do { \
157    _msr_value = 0; \
158    asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
159  } while (0)
160
161#define _CPU_MSR_SET( _msr_value ) \
162{ asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
163
164#define _CPU_ISR_Disable( _isr_cookie ) \
165  { register unsigned int _disable_mask = MSR_EE; \
166    _isr_cookie = 0; \
167    asm volatile ( \
168        "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
169        "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
170        "0" ((_isr_cookie)), "1" ((_disable_mask)) \
171        ); \
172  }
173
174
175#define _CPU_Data_Cache_Block_Flush( _address ) \
176  do { register void *__address = (_address); \
177       register unsigned32 _zero = 0; \
178       asm volatile ( "dcbf %0,%1" : \
179                      "=r" (_zero), "=r" (__address) : \
180                      "0" (_zero), "1" (__address) \
181       ); \
182  } while (0)
183
184
185/*
186 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
187 *  This indicates the end of an RTEMS critical section.  The parameter
188 *  _isr_cookie is not modified.
189 */
190
191#define _CPU_ISR_Enable( _isr_cookie )  \
192  { \
193     asm volatile ( "mtmsr %0" : \
194                   "=r" ((_isr_cookie)) : \
195                   "0" ((_isr_cookie))); \
196  }
197
198/*
199 *  This temporarily restores the interrupt to _isr_cookie before immediately
200 *  disabling them again.  This is used to divide long RTEMS critical
201 *  sections into two or more parts.  The parameter _isr_cookie is not
202 *  modified.
203 *
204 *  NOTE:  The version being used is not very optimized but it does
205 *         not trip a problem in gcc where the disable mask does not
206 *         get loaded.  Check this for future (post 10/97 gcc versions.
207 */
208
209#define _CPU_ISR_Flash( _isr_cookie ) \
210  { register unsigned int _disable_mask = MSR_EE; \
211    asm volatile ( \
212      "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \
213      "=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \
214      "0" ((_isr_cookie)), "1" ((_disable_mask)) \
215    ); \
216  }
217
218
219/* end of ISR handler macros */
220
221/*
222 *  Simple spin delay in microsecond units for device drivers.
223 *  This is very dependent on the clock speed of the target.
224 */
225
226#define CPU_Get_timebase_low( _value ) \
227    asm volatile( "mftb  %0" : "=r" (_value) )
228
229#define delay( _microseconds ) \
230  do { \
231    unsigned32 start, ticks, now; \
232    CPU_Get_timebase_low( start ) ; \
233    ticks = (_microseconds) * Cpu_table.clicks_per_usec; \
234    do \
235      CPU_Get_timebase_low( now ) ; \
236    while (now - start < ticks); \
237  } while (0)
238
239#define delay_in_bus_cycles( _cycles ) \
240  do { \
241    unsigned32 start, now; \
242    CPU_Get_timebase_low( start ); \
243    do \
244      CPU_Get_timebase_low( now ); \
245    while (now - start < (_cycles)); \
246  } while (0)
247
248#define PPC_Set_decrementer( _clicks ) \
249  do { \
250    asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
251  } while (0)
252
253#endif /* __ASM_PPC_PROCESSOR_H */
254
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260
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