source: rtems/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h @ f6ed46df

4.104.114.84.9
Last change on this file since f6ed46df was f6ed46df, checked in by Ralf Corsepius <ralf.corsepius@…>, on Feb 4, 2005 at 5:40:52 AM

Header guards cleanup.

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File size: 23.2 KB
Line 
1/**
2 * @file rtems/score/powerpc.h
3 */
4
5/*
6 *  This file contains definitions for the IBM/Motorola PowerPC
7 *  family members.
8 *
9 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
10 *
11 *  COPYRIGHT (c) 1995 by i-cubed ltd.
12 *
13 *  MPC860 support code was added by Jay Monkman <jmonkman@frasca.com>
14 *  MPC8260 support added by Andy Dachs <a.dachs@sstl.co.uk>
15 *  Surrey Satellite Technology Limited
16 *
17 *  To anyone who acknowledges that this file is provided "AS IS"
18 *  without any express or implied warranty:
19 *      permission to use, copy, modify, and distribute this file
20 *      for any purpose is hereby granted without fee, provided that
21 *      the above copyright notice and this notice appears in all
22 *      copies, and that the name of i-cubed limited not be used in
23 *      advertising or publicity pertaining to distribution of the
24 *      software without specific, written prior permission.
25 *      i-cubed limited makes no representations about the suitability
26 *      of this software for any purpose.
27 *
28 *  Derived from c/src/exec/cpu/no_cpu/no_cpu.h:
29 *
30 *  COPYRIGHT (c) 1989-1997.
31 *  On-Line Applications Research Corporation (OAR).
32 *
33 *  The license and distribution terms for this file may in
34 *  the file LICENSE in this distribution or at
35 *  http://www.rtems.com/license/LICENSE.
36 *
37 *
38 * Note:
39 *      This file is included by both C and assembler code ( -DASM )
40 *
41 *  $Id$
42 */
43
44
45#ifndef _RTEMS_SCORE_POWERPC_H
46#define _RTEMS_SCORE_POWERPC_H
47
48#ifdef __cplusplus
49extern "C" {
50#endif
51
52#include <rtems/score/types.h>
53
54/*
55 *  Define the name of the CPU family.
56 */
57
58#define CPU_NAME "PowerPC"
59
60/*
61 *  This file contains the information required to build
62 *  RTEMS for a particular member of the PowerPC family.  It does
63 *  this by setting variables to indicate which implementation
64 *  dependent features are present in a particular member
65 *  of the family.
66 *
67 *  The following architectural feature definitions are defaulted
68 *  unless specifically set by the model definition:
69 *
70 *    + PPC_INTERRUPT_MAX        - 16
71 *    + PPC_CACHE_ALIGNMENT      - 32
72 *    + PPC_LOW_POWER_MODE       - PPC_LOW_POWER_MODE_NONE
73 *    + PPC_HAS_EXCEPTION_PREFIX - 1
74 *    + PPC_HAS_FPU              - 1
75 *    + PPC_HAS_DOUBLE           - 1 if PPC_HAS_FPU,
76 *                               - 0 otherwise
77 *    + PPC_USE_MULTIPLE         - 0
78 */
79 
80/*
81 *  Define the low power mode models
82 *
83 *  Standard:   as defined for 603e
84 *  Nap Mode:   nap mode only (604)
85 *  XXX 403GB, 603, 603e, 604, 821
86 */
87
88#define PPC_LOW_POWER_MODE_NONE      0
89#define PPC_LOW_POWER_MODE_STANDARD  1
90
91/*
92 *  Figure out all CPU Model Feature Flags based upon compiler
93 *  predefines.
94 */
95
96#if defined(ppc403) || defined(ppc405)
97/*
98 *  IBM 403
99 *
100 *  Developed for 403GA.  Book checked for 403GB.
101 *
102 *  Does not have user mode.
103 */
104 
105#if defined(ppc403)
106#define CPU_MODEL_NAME "PowerPC 403"
107#elif defined (ppc405)
108#define CPU_MODEL_NAME "PowerPC 405"
109#endif
110#define PPC_ALIGNMENT           4 
111#define PPC_CACHE_ALIGNMENT     16
112#define PPC_HAS_RFCI            1
113#define PPC_HAS_FPU             0
114#define PPC_USE_MULTIPLE        1
115#define PPC_I_CACHE             2048
116#define PPC_D_CACHE             1024
117
118#define PPC_HAS_EXCEPTION_PREFIX 0
119#define PPC_HAS_EVPR             1
120
121#elif defined(mpc555)
122
123#define CPU_MODEL_NAME  "PowerPC 555"
124
125/* Copied from mpc505 */
126#define PPC_ALIGNMENT           4
127#define PPC_CACHE_ALIGNMENT     16
128
129/* Added by querbach@realtime.bc.ca */
130#define PPC_LOW_POWER_MODE      PPC_LOW_POWER_MODE_STANDARD
131
132/* Based on comments by Sergei Organov <osv@Javad.RU> */
133#define PPC_I_CACHE             0
134#define PPC_D_CACHE             0
135
136#elif defined(mpc505) || defined(mpc509)
137/*
138 *  Submitted by Sergei Organov <osv@Javad.RU> as a patch against
139 *  3.6.0 long after 4.0 was released.   This is just an attempt
140 *  to get the setting correct.
141 */
142
143#define CPU_MODEL_NAME  "PowerPC 505/509"
144
145#define PPC_ALIGNMENT           4
146#define PPC_CACHE_ALIGNMENT     16
147#define PPC_I_CACHE             4096
148#define PPC_D_CACHE             0
149
150
151#elif defined(ppc601)
152
153/*
154 *  Submitted with original port -- book checked only.
155 */
156 
157#define CPU_MODEL_NAME  "PowerPC 601"
158
159#define PPC_ALIGNMENT           8
160#define PPC_USE_MULTIPLE        1
161#define PPC_I_CACHE             0
162#define PPC_D_CACHE             32768
163
164#elif defined(ppc602)
165/*
166 *  Submitted with original port -- book checked only.
167 */
168 
169#define CPU_MODEL_NAME  "PowerPC 602"
170
171#define PPC_ALIGNMENT           4
172#define PPC_HAS_DOUBLE          0
173#define PPC_I_CACHE             4096
174#define PPC_D_CACHE             4096
175
176#elif defined(ppc603)
177/*
178 *  Submitted with original port -- book checked only.
179 */
180 
181#define CPU_MODEL_NAME  "PowerPC 603"
182
183#define PPC_ALIGNMENT           8
184#define PPC_I_CACHE             8192
185#define PPC_D_CACHE             8192
186
187#elif defined(ppc603e)
188 
189#define CPU_MODEL_NAME  "PowerPC 603e"
190/*
191 *  Submitted with original port.
192 *
193 *  Known to work on real hardware.
194 */
195
196#define PPC_ALIGNMENT           8
197#define PPC_I_CACHE             16384
198#define PPC_D_CACHE             16384
199
200#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD
201
202#elif defined(mpc604)
203/*
204 *  Submitted with original port -- book checked only.
205 */
206 
207#define CPU_MODEL_NAME  "PowerPC 604"
208
209#define PPC_ALIGNMENT           8
210#define PPC_I_CACHE             16384
211#define PPC_D_CACHE             16384
212 
213#elif defined(mpc860)
214/*
215 *  Added by Jay Monkman (jmonkman@frasca.com) 6/28/98
216 *  with some changes by Darlene Stewart (Darlene.Stewart@iit.nrc.ca)
217 */ 
218#define CPU_MODEL_NAME  "PowerPC MPC860"
219
220#define PPC_ALIGNMENT           4
221#define PPC_I_CACHE             4096
222#define PPC_D_CACHE             4096
223#define PPC_CACHE_ALIGNMENT     16
224#define PPC_INTERRUPT_MAX       71
225#define PPC_HAS_FPU             0
226#define PPC_HAS_DOUBLE          0
227#define PPC_USE_MULTIPLE        1
228
229#define PPC_MSR_0               0x00009000
230#define PPC_MSR_1               0x00001000
231#define PPC_MSR_2               0x00001000
232#define PPC_MSR_3               0x00000000
233
234#elif defined(mpc821)
235/*
236 *  Added by Andrew Bray <andy@chaos.org.uk> 6/April/1999
237 */ 
238#define CPU_MODEL_NAME  "PowerPC MPC821"
239
240#define PPC_ALIGNMENT           4
241#define PPC_I_CACHE             4096
242#define PPC_D_CACHE             4096
243#define PPC_CACHE_ALIGNMENT     16
244#define PPC_INTERRUPT_MAX       71
245#define PPC_HAS_FPU             0
246#define PPC_HAS_DOUBLE          0
247
248#define PPC_MSR_0               0x00009000
249#define PPC_MSR_1               0x00001000
250#define PPC_MSR_2               0x00001000
251#define PPC_MSR_3               0x00000000
252
253#elif defined(mpc750)
254
255#define CPU_MODEL_NAME  "PowerPC 750"
256
257#define PPC_ALIGNMENT           8
258#define PPC_I_CACHE             16384
259#define PPC_D_CACHE             16384
260
261#elif defined(mpc7400)
262
263#define CPU_MODEL_NAME  "PowerPC 7400"
264
265#define PPC_ALIGNMENT           8
266#define PPC_I_CACHE             32768
267#define PPC_D_CACHE             32768
268
269#elif defined(mpc7455)
270/*
271 *  Added by S.K. Feng <feng1@bnl.gov> 10/03
272 */
273
274#define CPU_MODEL_NAME  "PowerPC 7455"
275
276#define PPC_ALIGNMENT           8
277#define PPC_CACHE_ALIGNMENT     32
278#define PPC_I_CACHE             32768
279#define PPC_D_CACHE             32768
280
281#elif defined(mpc8260)
282/*
283 *  Added by Andy Dachs <a.dachs@sstl.co.uk> 23/11/2000
284 */
285#define CPU_MODEL_NAME  "PowerPC MPC8260"
286
287#define PPC_ALIGNMENT           4
288#define PPC_I_CACHE             16384
289#define PPC_D_CACHE             16384
290#define PPC_CACHE_ALIGNMENT     32
291#define PPC_INTERRUPT_MAX       125
292/*#define PPC_HAS_FPU           0 */    /* my 8260 is one the few with no FPU */
293#define PPC_HAS_FPU             1       /* the rest do have one */
294#define PPC_HAS_DOUBLE          1
295#define PPC_USE_MULTIPLE        1
296#else
297 
298#error "Unsupported CPU Model"
299 
300#endif
301
302/*
303 *  Application binary interfaces.
304 *
305 *  PPC_ABI MUST be defined as one of these.
306 *  Only PPC_ABI_POWEROPEN is currently fully supported.
307 *  Only EABI will be supported in the end when
308 *  the tools are there.
309 *  Only big endian is currently supported.
310 */
311/*
312 *  PowerOpen ABI.  This is Andy's hack of the
313 *  PowerOpen ABI to ELF.  ELF rather than a
314 *  XCOFF assembler is used.  This may work
315 *  if PPC_ASM == PPC_ASM_XCOFF is defined.
316 */
317#define PPC_ABI_POWEROPEN       0
318/*
319 *  GCC 2.7.0 munched version of EABI, with
320 *  PowerOpen calling convention and stack frames,
321 *  but EABI style indirect function calls.
322 */
323#define PPC_ABI_GCC27           1
324/*
325 *  SVR4 ABI
326 */
327#define PPC_ABI_SVR4            2
328/*
329 *  Embedded ABI
330 */
331#define PPC_ABI_EABI            3
332
333/*
334 *  Default to the EABI used by current GNU tools
335 */
336
337#ifndef PPC_ABI
338#define PPC_ABI PPC_ABI_EABI
339#endif
340
341#if (PPC_ABI == PPC_ABI_POWEROPEN)
342#define PPC_STACK_ALIGNMENT     8
343#elif (PPC_ABI == PPC_ABI_GCC27)
344#define PPC_STACK_ALIGNMENT     8
345#elif (PPC_ABI == PPC_ABI_SVR4)
346#define PPC_STACK_ALIGNMENT     16
347#elif (PPC_ABI == PPC_ABI_EABI)
348#define PPC_STACK_ALIGNMENT     8
349#else
350#error  "PPC_ABI is not properly defined"
351#endif
352#ifndef PPC_ABI
353#error  "PPC_ABI is not properly defined"
354#endif
355
356/*
357 *  Assemblers.
358 *  PPC_ASM MUST be defined as one of these.
359 *
360 *  PPC_ASM_ELF:   ELF assembler. Currently used for all ABIs.
361 *  PPC_ASM_XCOFF: XCOFF assembler. May be needed for PowerOpen ABI.
362 *
363 *  NOTE: Only PPC_ABI_ELF is currently fully supported.
364 */
365
366#define PPC_ASM_ELF   0
367#define PPC_ASM_XCOFF 1
368
369/*
370 *  Default to the assembler format used by the current GNU tools.
371 */
372
373#ifndef PPC_ASM
374#define PPC_ASM PPC_ASM_ELF
375#endif
376
377/*
378 *  If the maximum number of exception sources has not been defined,
379 *  then default it to 16.
380 */
381
382#ifndef PPC_INTERRUPT_MAX
383#define PPC_INTERRUPT_MAX       16
384#endif
385
386/*
387 *  Unless specified otherwise, the cache line size is defaulted to 32.
388 *
389 *  The derive the power of 2 the cache line is.
390 */
391
392#ifndef PPC_CACHE_ALIGNMENT
393#define PPC_CACHE_ALIGNMENT 32
394#endif
395
396#if (PPC_CACHE_ALIGNMENT == 16)
397#define PPC_CACHE_ALIGN_POWER 4
398#elif (PPC_CACHE_ALIGNMENT == 32)
399#define PPC_CACHE_ALIGN_POWER 5
400#else
401#error "Undefined power of 2 for PPC_CACHE_ALIGNMENT"
402#endif
403
404/*
405 *  Unless otherwise specified, assume the model has an IP/EP bit to
406 *  set the exception address prefix.
407 */
408
409#ifndef PPC_HAS_EXCEPTION_PREFIX
410#define PPC_HAS_EXCEPTION_PREFIX 1
411#endif
412
413/*
414 *  Unless otherwise specified, assume the model does NOT have
415 *  403 style EVPR register to set the exception address prefix.
416 */
417
418#ifndef PPC_HAS_EVPR
419#define PPC_HAS_EVPR 0
420#endif
421
422/*
423 *  If no low power mode model was specified, then assume there is none.
424 */
425
426#ifndef PPC_LOW_POWER_MODE
427#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_NONE
428#endif
429
430/*
431 *  Unless specified above, then assume the model has FP support.
432 */
433
434#ifndef PPC_HAS_FPU
435#define PPC_HAS_FPU 1
436#endif
437
438/*
439 *  Unless specified above, If the model has FP support, it is assumed to
440 *  support doubles (8-byte floating point numbers).
441 *
442 *  If the model does NOT have FP support, then the model does
443 *  NOT have double length FP registers.
444 */
445
446#ifndef PPC_HAS_DOUBLE
447#if (PPC_HAS_FPU)
448#define PPC_HAS_DOUBLE 1
449#else
450#define PPC_HAS_DOUBLE 0
451#endif
452#endif
453
454/*
455 *  Unless specified above, then assume the model does NOT have critical
456 *  interrupt support.
457 */
458
459#ifndef PPC_HAS_RFCI
460#define PPC_HAS_RFCI 0
461#endif
462
463/*
464 *  Unless specified above, do not use the load/store multiple instructions
465 *  in a context switch.
466 */
467
468#ifndef PPC_USE_MULTIPLE
469#define PPC_USE_MULTIPLE 0
470#endif
471
472/*
473 *  The following exceptions are not maskable, and are not
474 *  necessarily predictable, so cannot be offered to RTEMS:
475 *    Alignment exception - handled by the CPU module
476 *    Data exceptions.
477 *    Instruction exceptions.
478 */
479
480/*
481 *  Base Interrupt vectors supported on all models.
482 */
483#define PPC_IRQ_SYSTEM_RESET     0 /* 0x00100 - System reset.              */
484#define PPC_IRQ_MCHECK           1 /* 0x00200 - Machine check              */
485#define PPC_IRQ_PROTECT          2 /* 0x00300 - Protection violation       */
486#define PPC_IRQ_ISI              3 /* 0x00400 - Instruction Fetch error    */
487#define PPC_IRQ_EXTERNAL         4 /* 0x00500 - External interrupt         */
488#define PPC_IRQ_ALIGNMENT        5 /* 0X00600 - Alignment exception        */
489#define PPC_IRQ_PROGRAM          6 /* 0x00700 - Program exception          */
490#define PPC_IRQ_NOFP             7 /* 0x00800 - Floating point unavailable */
491#define PPC_IRQ_DECREMENTER      8 /* 0x00900 - Decrementer interrupt      */
492#define PPC_IRQ_RESERVED_A       9 /* 0x00a00 - Implementation Reserved    */
493#define PPC_IRQ_RESERVED_B      10 /* 0x00b00 - Implementation Reserved    */
494#define PPC_IRQ_SCALL           11 /* 0x00c00 - System call                */
495#define PPC_IRQ_TRACE           12 /* 0x00d00 - Trace Exception            */
496#define PPC_IRQ_FP_ASST         13 /* ox00e00 - Floating point assist      */
497#define PPC_STD_IRQ_LAST        PPC_IRQ_FP_ASST
498
499#define PPC_IRQ_FIRST           PPC_IRQ_SYSTEM_RESET
500
501#if defined(ppc403) || defined(ppc405)
502                                 
503#define PPC_IRQ_CRIT     PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */
504#define PPC_IRQ_PIT      (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/
505#define PPC_IRQ_FIT      (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer  */
506#define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer    */
507#define PPC_IRQ_DEBUG    (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions  */
508#define PPC_IRQ_LAST     PPC_IRQ_DEBUG
509
510#elif defined(mpc505) || defined(mpc509)
511#define PPC_IRQ_SOFTEMU   (PPC_STD_IRQ_LAST+1)    /* Software emulation. */
512#define PPC_IRQ_DATA_BP   (PPC_STD_IRQ_LAST+ 2)
513#define PPC_IRQ_INST_BP   (PPC_STD_IRQ_LAST+ 3)
514#define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+ 4)
515#define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+ 5)
516
517#elif defined(mpc555)
518#define PPC_IRQ_SOFTEMU   (PPC_STD_IRQ_LAST+1)  /* Software emulation. */
519#define PPC_IRQ_INST_PE   (PPC_STD_IRQ_LAST+2)  /* Insn protection error */
520#define PPC_IRQ_DATA_PE   (PPC_STD_IRQ_LAST+3)  /* Data protection error */
521#define PPC_IRQ_DATA_BP   (PPC_STD_IRQ_LAST+4)  /* Data breakpoint */
522#define PPC_IRQ_INST_BP   (PPC_STD_IRQ_LAST+5)  /* Insn breakpoint */
523#define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+6)  /* Maskable ext bkpt */
524#define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+7)  /* Non-maskable ext bkpt */
525#define PPC_IRQ_LAST      PPC_IRQ_NMEXT_BP
526
527#elif defined(ppc601)
528#define PPC_IRQ_TRACE    (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/
529#define PPC_IRQ_LAST     PPC_IRQ_TRACE       
530
531#elif defined(ppc602)
532#define PPC_IRQ_LAST     (PPC_STD_IRQ_LAST)
533
534#elif defined(ppc603)
535#define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/
536#define PPC_IRQ_DATA_LOAD  (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/
537#define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss     */
538#define PPC_IRQ_ADDR_BRK   (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */
539#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
540#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT   
541
542#elif defined(ppc603e)
543#define PPC_TLB_INST_MISS  (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB Miss*/
544#define PPC_TLB_LOAD_MISS  (PPC_STD_IRQ_LAST+2) /*0x1100-TLB miss on load  */
545#define PPC_TLB_STORE_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-TLB Miss on store */
546#define PPC_IRQ_ADDRBRK    (PPC_STD_IRQ_LAST+4) /*0x1300-Instruct addr break */
547#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
548#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT   
549
550
551#elif defined(mpc604)
552#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break  */
553#define PPC_IRQ_SYS_MGT  (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */
554#define PPC_IRQ_LAST     PPC_IRQ_SYS_MGT 
555
556#elif defined(mpc860) || defined(mpc821)
557#define PPC_IRQ_EMULATE         (PPC_STD_IRQ_LAST+1) /*0x1000-Software emulation  */
558#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Instruction TLB miss*/
559#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB miss */
560#define PPC_IRQ_INST_ERR        (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction TLB err */
561#define PPC_IRQ_DATA_ERR        (PPC_STD_IRQ_LAST+5) /*0x1400-Data TLB error */
562#define PPC_IRQ_DATA_BPNT       (PPC_STD_IRQ_LAST+6) /*0x1C00-Data breakpoint */
563#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+7) /*0x1D00-Inst breakpoint */
564#define PPC_IRQ_IO_BPNT         (PPC_STD_IRQ_LAST+8) /*0x1E00-Peripheral breakpnt */
565#define PPC_IRQ_DEV_PORT        (PPC_STD_IRQ_LAST+9) /*0x1F00-Development port */
566#define PPC_IRQ_IRQ0            (PPC_STD_IRQ_LAST + 10)
567#define PPC_IRQ_LVL0            (PPC_STD_IRQ_LAST + 11)
568#define PPC_IRQ_IRQ1            (PPC_STD_IRQ_LAST + 12)
569#define PPC_IRQ_LVL1            (PPC_STD_IRQ_LAST + 13)
570#define PPC_IRQ_IRQ2            (PPC_STD_IRQ_LAST + 14)
571#define PPC_IRQ_LVL2            (PPC_STD_IRQ_LAST + 15)
572#define PPC_IRQ_IRQ3            (PPC_STD_IRQ_LAST + 16)
573#define PPC_IRQ_LVL3            (PPC_STD_IRQ_LAST + 17)
574#define PPC_IRQ_IRQ4            (PPC_STD_IRQ_LAST + 18)
575#define PPC_IRQ_LVL4            (PPC_STD_IRQ_LAST + 19)
576#define PPC_IRQ_IRQ5            (PPC_STD_IRQ_LAST + 20)
577#define PPC_IRQ_LVL5            (PPC_STD_IRQ_LAST + 21)
578#define PPC_IRQ_IRQ6            (PPC_STD_IRQ_LAST + 22)
579#define PPC_IRQ_LVL6            (PPC_STD_IRQ_LAST + 23)
580#define PPC_IRQ_IRQ7            (PPC_STD_IRQ_LAST + 24)
581#define PPC_IRQ_LVL7            (PPC_STD_IRQ_LAST + 25)
582#define PPC_IRQ_CPM_ERROR       (PPC_STD_IRQ_LAST + 26)
583#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 27)
584#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 28)
585#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 29)
586#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 30)
587#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 31)
588#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 32)
589#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 33)
590#define PPC_IRQ_CPM_RESERVED_8  (PPC_STD_IRQ_LAST + 34)
591#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 35)
592#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 36)
593#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 37)
594#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 38)
595#define PPC_IRQ_CPM_RESERVED_D  (PPC_STD_IRQ_LAST + 39)
596#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 40)
597#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 41)
598#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 42)
599#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 43)
600#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 44)
601#define PPC_IRQ_CPM_RESERVED_13 (PPC_STD_IRQ_LAST + 45)
602#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 46)
603#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 47)
604#define PPC_IRQ_CPM_SDMA_ERROR  (PPC_STD_IRQ_LAST + 48)
605#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 49)
606#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 50)
607#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 51)
608#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 52)
609#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 53)
610#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 54)
611#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 55)
612#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 56)
613#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 57)
614
615#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC15
616
617#elif defined(mpc8260)
618
619#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB miss*/
620#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Data TLB miss */
621#define PPC_IRQ_DATA_L_MISS     (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB load miss */
622#define PPC_IRQ_DATA_S_MISS     (PPC_STD_IRQ_LAST+4) /*0x1300-Data TLB store miss */
623#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+5) /*0x1400-Inst address breakpoint */
624#define PPC_IRQ_SYS_MGT         (PPC_STD_IRQ_LAST+6) /*0x1500-System Management */
625/* 0x1600 - 0x2F00 reserved */
626#define PPC_IRQ_CPM_NONE        (PPC_STD_IRQ_LAST + 50)
627#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 51)
628#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 52)
629#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 53)
630#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 54)
631#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 55)
632#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 56)
633#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 57)
634#define PPC_IRQ_CPM_IDMA3       (PPC_STD_IRQ_LAST + 58)
635#define PPC_IRQ_CPM_IDMA4       (PPC_STD_IRQ_LAST + 59)
636#define PPC_IRQ_CPM_SDMA        (PPC_STD_IRQ_LAST + 60)
637#define PPC_IRQ_CPM_RES_A       (PPC_STD_IRQ_LAST + 61)
638#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 62)
639#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 63)
640#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 64)
641#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 65)
642#define PPC_IRQ_CPM_TMCNT       (PPC_STD_IRQ_LAST + 66)
643#define PPC_IRQ_CPM_PIT         (PPC_STD_IRQ_LAST + 67)
644#define PPC_IRQ_CPM_RES_B       (PPC_STD_IRQ_LAST + 68)
645#define PPC_IRQ_CPM_IRQ1        (PPC_STD_IRQ_LAST + 69)
646#define PPC_IRQ_CPM_IRQ2        (PPC_STD_IRQ_LAST + 70)
647#define PPC_IRQ_CPM_IRQ3        (PPC_STD_IRQ_LAST + 71)
648#define PPC_IRQ_CPM_IRQ4        (PPC_STD_IRQ_LAST + 72)
649#define PPC_IRQ_CPM_IRQ5        (PPC_STD_IRQ_LAST + 73)
650#define PPC_IRQ_CPM_IRQ6        (PPC_STD_IRQ_LAST + 74)
651#define PPC_IRQ_CPM_IRQ7        (PPC_STD_IRQ_LAST + 75)
652#define PPC_IRQ_CPM_RES_C       (PPC_STD_IRQ_LAST + 76)
653#define PPC_IRQ_CPM_RES_D       (PPC_STD_IRQ_LAST + 77)
654#define PPC_IRQ_CPM_RES_E       (PPC_STD_IRQ_LAST + 78)
655#define PPC_IRQ_CPM_RES_F       (PPC_STD_IRQ_LAST + 79)
656#define PPC_IRQ_CPM_RES_G       (PPC_STD_IRQ_LAST + 80)
657#define PPC_IRQ_CPM_RES_H       (PPC_STD_IRQ_LAST + 81)
658#define PPC_IRQ_CPM_FCC1        (PPC_STD_IRQ_LAST + 82)
659#define PPC_IRQ_CPM_FCC2        (PPC_STD_IRQ_LAST + 83)
660#define PPC_IRQ_CPM_FCC3        (PPC_STD_IRQ_LAST + 84)
661#define PPC_IRQ_CPM_RES_I       (PPC_STD_IRQ_LAST + 85)
662#define PPC_IRQ_CPM_MCC1        (PPC_STD_IRQ_LAST + 86)
663#define PPC_IRQ_CPM_MCC2        (PPC_STD_IRQ_LAST + 87)
664#define PPC_IRQ_CPM_RES_J       (PPC_STD_IRQ_LAST + 88)
665#define PPC_IRQ_CPM_RES_K       (PPC_STD_IRQ_LAST + 89)
666#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 90)
667#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 91)
668#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 92)
669#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 93)
670#define PPC_IRQ_CPM_RES_L       (PPC_STD_IRQ_LAST + 94)
671#define PPC_IRQ_CPM_RES_M       (PPC_STD_IRQ_LAST + 95)
672#define PPC_IRQ_CPM_RES_N       (PPC_STD_IRQ_LAST + 96)
673#define PPC_IRQ_CPM_RES_O       (PPC_STD_IRQ_LAST + 97)
674#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 98)
675#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 99)
676#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 100)
677#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 101)
678#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 102)
679#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 103)
680#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 104)
681#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 105)
682#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 106)
683#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 107)
684#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 108)
685#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 109)
686#define PPC_IRQ_CPM_PC3         (PPC_STD_IRQ_LAST + 110)
687#define PPC_IRQ_CPM_PC2         (PPC_STD_IRQ_LAST + 111)
688#define PPC_IRQ_CPM_PC1         (PPC_STD_IRQ_LAST + 112)
689#define PPC_IRQ_CPM_PC0         (PPC_STD_IRQ_LAST + 113)
690
691#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC0
692
693#endif
694
695
696/*
697 *  If the maximum number of exception sources is too low,
698 *  then fix it
699 */
700
701#if PPC_INTERRUPT_MAX <= PPC_IRQ_LAST
702#undef PPC_INTERRUPT_MAX
703#define PPC_INTERRUPT_MAX ((PPC_IRQ_LAST) + 1)
704#endif
705
706/*
707 *  Machine Status Register (MSR) Constants Used by RTEMS
708 */
709
710/*
711 *  Some PPC model manuals refer to the Exception Prefix (EP) bit as
712 *  IP for no apparent reason.
713 */
714
715#define PPC_MSR_RI       0x000000002 /* bit 30 - recoverable exception */
716#define PPC_MSR_DR       0x000000010 /* bit 27 - data address translation */
717#define PPC_MSR_IR       0x000000020 /* bit 26 - instruction addr translation*/
718
719#if (PPC_HAS_EXCEPTION_PREFIX)
720#define PPC_MSR_EP       0x000000040 /* bit 25 - exception prefix */
721#else
722#define PPC_MSR_EP       0x000000000 /* bit 25 - exception prefix */
723#endif
724
725#if (PPC_HAS_FPU)
726#define PPC_MSR_FP       0x000002000 /* bit 18 - floating point enable */
727#else
728#define PPC_MSR_FP       0x000000000 /* bit 18 - floating point enable */
729#endif
730
731#if (PPC_LOW_POWER_MODE == PPC_LOW_POWER_MODE_NONE)
732#define PPC_MSR_POW      0x000000000 /* bit 13 - power management enable */
733#else
734#define PPC_MSR_POW      0x000040000 /* bit 13 - power management enable */
735#endif
736
737#define PPC_MSR_ME       0x000001000 /* bit 19 - machine check enable */
738#define PPC_MSR_EE       0x000008000 /* bit 16 - external interrupt enable */
739
740#if (PPC_HAS_RFCI)
741#define PPC_MSR_CE       0x000020000 /* bit 14 - critical interrupt enable */
742#else
743#define PPC_MSR_CE       0x000000000 /* bit 14 - critical interrupt enable */
744#endif
745
746#define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE)
747
748/*
749 *  Initial value for the FPSCR register
750 */
751
752#define PPC_INIT_FPSCR          0x000000f8
753
754#ifdef __cplusplus
755}
756#endif
757
758#endif /* _RTEMS_SCORE_POWERPC_H */
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