source: rtems/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h @ e1df032

4.104.114.9
Last change on this file since e1df032 was e1df032, checked in by Till Straumann <strauman@…>, on Jul 10, 2008 at 9:51:55 PM

2008-07-10 Till Straumann <strauman@…>

  • ChangeLog?, mpc8xx/clock/clock.c, ppc403/clock/clock.c, ppc403/irq/ictrl.h, rtems/powerpc/powerpc.h: Removed all macro definitions which depended on the compiler defining a PPC CPU-model dependent symbol from files in cpukit. Macros which were not used by cpukit have been moved to libcpu/powerpc/rtems/powerpc/powerpc.h.
  • Property mode set to 100644
File size: 19.6 KB
Line 
1/**
2 * @file rtems/powerpc/powerpc.h
3 */
4
5/*
6 *  This file contains definitions for the IBM/Motorola PowerPC
7 *  family members.
8 *
9 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
10 *
11 *  COPYRIGHT (c) 1995 by i-cubed ltd.
12 *
13 *  MPC860 support code was added by Jay Monkman <jmonkman@frasca.com>
14 *  MPC8260 support added by Andy Dachs <a.dachs@sstl.co.uk>
15 *  Surrey Satellite Technology Limited
16 *
17 *  To anyone who acknowledges that this file is provided "AS IS"
18 *  without any express or implied warranty:
19 *      permission to use, copy, modify, and distribute this file
20 *      for any purpose is hereby granted without fee, provided that
21 *      the above copyright notice and this notice appears in all
22 *      copies, and that the name of i-cubed limited not be used in
23 *      advertising or publicity pertaining to distribution of the
24 *      software without specific, written prior permission.
25 *      i-cubed limited makes no representations about the suitability
26 *      of this software for any purpose.
27 *
28 *  Derived from c/src/exec/cpu/no_cpu/no_cpu.h:
29 *
30 *  COPYRIGHT (c) 1989-1997.
31 *  On-Line Applications Research Corporation (OAR).
32 *
33 *  The license and distribution terms for this file may in
34 *  the file LICENSE in this distribution or at
35 *  http://www.rtems.com/license/LICENSE.
36 *
37 *
38 * Note:
39 *      This file is included by both C and assembler code ( -DASM )
40 *
41 *  $Id$
42 */
43
44
45#ifndef _RTEMS_POWERPC_POWERPC_H
46#define _RTEMS_POWERPC_POWERPC_H
47
48#ifdef __cplusplus
49extern "C" {
50#endif
51
52
53/* Till S. 2008/07/10:
54 *
55 * Using the macros/definitions which depend on a preprocessor
56 * symbol defining the CPU flavor is discouraged.
57 * I recommend to not use definitions from this file and
58 * in particular - not to add more bits and pieces.
59 *
60 * Instead, try to use run-time detection (see e.g. cpuIdent.c/cpuIdent.h)
61 * of features etc.
62 */
63
64#include <rtems/score/powerpc.h>
65
66/*
67 *  This file contains the information required to build
68 *  RTEMS for a particular member of the PowerPC family.  It does
69 *  this by setting variables to indicate which implementation
70 *  dependent features are present in a particular member
71 *  of the family.
72 *
73 *  The following architectural feature definitions are defaulted
74 *  unless specifically set by the model definition:
75 *
76 *    + PPC_INTERRUPT_MAX        - 16
77 *    + PPC_CACHE_ALIGNMENT      - 32
78 *    + PPC_LOW_POWER_MODE       - PPC_LOW_POWER_MODE_NONE
79 *    + PPC_HAS_EXCEPTION_PREFIX - 1
80 *    + PPC_USE_MULTIPLE         - 0
81 */
82 
83/*
84 *  Define the low power mode models
85 *
86 *  Standard:   as defined for 603e
87 *  Nap Mode:   nap mode only (604)
88 *  XXX 403GB, 603, 603e, 604, 821
89 */
90
91#define PPC_LOW_POWER_MODE_NONE      0
92#define PPC_LOW_POWER_MODE_STANDARD  1
93
94/*
95 *  Figure out all CPU Model Feature Flags based upon compiler
96 *  predefines.
97 */
98
99#if defined(ppc403) || defined(ppc405)
100/*
101 *  IBM 403
102 *
103 *  Developed for 403GA.  Book checked for 403GB.
104 *
105 *  Does not have user mode.
106 */
107 
108#define PPC_CACHE_ALIGNMENT     16
109#define PPC_HAS_RI              0
110#define PPC_HAS_RFCI            1
111#define PPC_USE_MULTIPLE        1
112#define PPC_I_CACHE             2048
113#define PPC_D_CACHE             1024
114
115#define PPC_HAS_EXCEPTION_PREFIX 0
116#define PPC_HAS_EVPR             1
117
118#elif defined(mpc555)
119
120/* Copied from mpc505 */
121#define PPC_CACHE_ALIGNMENT     16
122
123/* Added by querbach@realtime.bc.ca */
124#define PPC_LOW_POWER_MODE      PPC_LOW_POWER_MODE_STANDARD
125
126/* Based on comments by Sergei Organov <osv@Javad.RU> */
127#define PPC_I_CACHE             0
128#define PPC_D_CACHE             0
129
130#elif defined(mpc505) || defined(mpc509)
131/*
132 *  Submitted by Sergei Organov <osv@Javad.RU> as a patch against
133 *  3.6.0 long after 4.0 was released.   This is just an attempt
134 *  to get the setting correct.
135 */
136
137#define PPC_CACHE_ALIGNMENT     16
138#define PPC_I_CACHE             4096
139#define PPC_D_CACHE             0
140
141
142#elif defined(ppc601)
143
144/*
145 *  Submitted with original port -- book checked only.
146 */
147 
148#define PPC_USE_MULTIPLE        1
149#define PPC_I_CACHE             0
150#define PPC_D_CACHE             32768
151
152#elif defined(ppc603)
153/*
154 *  Submitted with original port -- book checked only.
155 */
156 
157#define PPC_I_CACHE             8192
158#define PPC_D_CACHE             8192
159
160#elif defined(ppc603e)
161 
162/*
163 *  Submitted with original port.
164 *
165 *  Known to work on real hardware.
166 */
167
168#define PPC_I_CACHE             16384
169#define PPC_D_CACHE             16384
170
171#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD
172
173#elif defined(mpc604)
174/*
175 *  Submitted with original port -- book checked only.
176 */
177 
178#define PPC_I_CACHE             16384
179#define PPC_D_CACHE             16384
180 
181#elif defined(mpc860)
182/*
183 *  Added by Jay Monkman (jmonkman@frasca.com) 6/28/98
184 *  with some changes by Darlene Stewart (Darlene.Stewart@iit.nrc.ca)
185 */ 
186#define PPC_I_CACHE             4096
187#define PPC_D_CACHE             4096
188#define PPC_CACHE_ALIGNMENT     16
189#define PPC_INTERRUPT_MAX       71
190#define PPC_USE_MULTIPLE        1
191
192#define PPC_MSR_0               0x00009000
193#define PPC_MSR_1               0x00001000
194#define PPC_MSR_2               0x00001000
195#define PPC_MSR_3               0x00000000
196
197#elif defined(mpc821)
198/*
199 *  Added by Andrew Bray <andy@chaos.org.uk> 6/April/1999
200 */ 
201#define PPC_I_CACHE             4096
202#define PPC_D_CACHE             4096
203#define PPC_CACHE_ALIGNMENT     16
204#define PPC_INTERRUPT_MAX       71
205
206#define PPC_MSR_0               0x00009000
207#define PPC_MSR_1               0x00001000
208#define PPC_MSR_2               0x00001000
209#define PPC_MSR_3               0x00000000
210
211#elif defined(mpc750)
212
213#define PPC_I_CACHE             16384
214#define PPC_D_CACHE             16384
215
216#elif defined(mpc7400)
217
218#define PPC_I_CACHE             32768
219#define PPC_D_CACHE             32768
220
221#elif defined(mpc7455)
222/*
223 *  Added by S.K. Feng <feng1@bnl.gov> 10/03
224 */
225
226#define PPC_CACHE_ALIGNMENT     32
227#define PPC_I_CACHE             32768
228#define PPC_D_CACHE             32768
229
230#elif defined(mpc8260)
231/*
232 *  Added by Andy Dachs <a.dachs@sstl.co.uk> 23/11/2000
233 */
234#define PPC_I_CACHE             16384
235#define PPC_D_CACHE             16384
236#define PPC_CACHE_ALIGNMENT     32
237#define PPC_INTERRUPT_MAX       125
238#define PPC_USE_MULTIPLE        1
239
240#elif defined(__ppc_generic)
241#define PPC_CACHE_ALIGNMENT 32
242
243#else
244 
245#error "Unsupported CPU Model"
246 
247#endif
248
249/*
250 *  If the maximum number of exception sources has not been defined,
251 *  then default it to 16.
252 */
253
254#ifndef PPC_INTERRUPT_MAX
255#define PPC_INTERRUPT_MAX       16
256#endif
257
258/*
259 *  Unless specified otherwise, the cache line size is defaulted to 32.
260 *
261 *  The derive the power of 2 the cache line is.
262 */
263
264#ifndef PPC_CACHE_ALIGNMENT
265#define PPC_CACHE_ALIGNMENT 32
266#endif
267
268#if (PPC_CACHE_ALIGNMENT == 16)
269#define PPC_CACHE_ALIGN_POWER 4
270#elif (PPC_CACHE_ALIGNMENT == 32)
271#define PPC_CACHE_ALIGN_POWER 5
272#else
273#error "Undefined power of 2 for PPC_CACHE_ALIGNMENT"
274#endif
275
276/*
277 *  Unless otherwise specified, assume the model has an IP/EP bit to
278 *  set the exception address prefix.
279 */
280
281#ifndef PPC_HAS_EXCEPTION_PREFIX
282#define PPC_HAS_EXCEPTION_PREFIX 1
283#endif
284/*
285 *  Unless otherwise specified, assume the model has an RI bit to
286 *  identify non-recoverable interrupts
287 */
288
289#ifndef PPC_HAS_RI
290#define PPC_HAS_RI 1
291#endif
292
293/*
294 *  Unless otherwise specified, assume the model does NOT have
295 *  403 style EVPR register to set the exception address prefix.
296 */
297
298#ifndef PPC_HAS_EVPR
299#define PPC_HAS_EVPR 0
300#endif
301
302/*
303 *  If no low power mode model was specified, then assume there is none.
304 */
305
306#ifndef PPC_LOW_POWER_MODE
307#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_NONE
308#endif
309
310/*
311 *  Unless specified above, then assume the model does NOT have critical
312 *  interrupt support.
313 */
314
315#ifndef PPC_HAS_RFCI
316#define PPC_HAS_RFCI 0
317#endif
318
319/*
320 *  Unless specified above, do not use the load/store multiple instructions
321 *  in a context switch.
322 */
323
324#ifndef PPC_USE_MULTIPLE
325#define PPC_USE_MULTIPLE 0
326#endif
327
328/*
329 *  The following exceptions are not maskable, and are not
330 *  necessarily predictable, so cannot be offered to RTEMS:
331 *    Alignment exception - handled by the CPU module
332 *    Data exceptions.
333 *    Instruction exceptions.
334 */
335
336/*
337 *  Base Interrupt vectors supported on all models.
338 */
339#define PPC_IRQ_SYSTEM_RESET     0 /* 0x00100 - System reset.              */
340#define PPC_IRQ_MCHECK           1 /* 0x00200 - Machine check              */
341#define PPC_IRQ_PROTECT          2 /* 0x00300 - Protection violation       */
342#define PPC_IRQ_ISI              3 /* 0x00400 - Instruction Fetch error    */
343#define PPC_IRQ_EXTERNAL         4 /* 0x00500 - External interrupt         */
344#define PPC_IRQ_ALIGNMENT        5 /* 0X00600 - Alignment exception        */
345#define PPC_IRQ_PROGRAM          6 /* 0x00700 - Program exception          */
346#define PPC_IRQ_NOFP             7 /* 0x00800 - Floating point unavailable */
347#define PPC_IRQ_DECREMENTER      8 /* 0x00900 - Decrementer interrupt      */
348#define PPC_IRQ_RESERVED_A       9 /* 0x00a00 - Implementation Reserved    */
349#define PPC_IRQ_RESERVED_B      10 /* 0x00b00 - Implementation Reserved    */
350#define PPC_IRQ_SCALL           11 /* 0x00c00 - System call                */
351#define PPC_IRQ_TRACE           12 /* 0x00d00 - Trace Exception            */
352#define PPC_IRQ_FP_ASST         13 /* ox00e00 - Floating point assist      */
353#define PPC_STD_IRQ_LAST        PPC_IRQ_FP_ASST
354
355#define PPC_IRQ_FIRST           PPC_IRQ_SYSTEM_RESET
356
357#if defined(ppc403) || defined(ppc405)
358                                 
359#define PPC_IRQ_CRIT     PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */
360#define PPC_IRQ_PIT      (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/
361#define PPC_IRQ_FIT      (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer  */
362#define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer    */
363#define PPC_IRQ_DEBUG    (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions  */
364#define PPC_IRQ_LAST     PPC_IRQ_DEBUG
365
366#elif defined(mpc505) || defined(mpc509)
367#define PPC_IRQ_SOFTEMU   (PPC_STD_IRQ_LAST+1)    /* Software emulation. */
368#define PPC_IRQ_DATA_BP   (PPC_STD_IRQ_LAST+ 2)
369#define PPC_IRQ_INST_BP   (PPC_STD_IRQ_LAST+ 3)
370#define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+ 4)
371#define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+ 5)
372
373#elif defined(mpc555)
374#define PPC_IRQ_SOFTEMU   (PPC_STD_IRQ_LAST+1)  /* Software emulation. */
375#define PPC_IRQ_INST_PE   (PPC_STD_IRQ_LAST+2)  /* Insn protection error */
376#define PPC_IRQ_DATA_PE   (PPC_STD_IRQ_LAST+3)  /* Data protection error */
377#define PPC_IRQ_DATA_BP   (PPC_STD_IRQ_LAST+4)  /* Data breakpoint */
378#define PPC_IRQ_INST_BP   (PPC_STD_IRQ_LAST+5)  /* Insn breakpoint */
379#define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+6)  /* Maskable ext bkpt */
380#define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+7)  /* Non-maskable ext bkpt */
381#define PPC_IRQ_LAST      PPC_IRQ_NMEXT_BP
382
383#elif defined(ppc601)
384#define PPC_IRQ_TRACE    (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/
385#define PPC_IRQ_LAST     PPC_IRQ_TRACE       
386
387#elif defined(ppc602)
388#define PPC_IRQ_LAST     (PPC_STD_IRQ_LAST)
389
390#elif defined(ppc603) || defined(ppc603e)
391#define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/
392#define PPC_IRQ_DATA_LOAD  (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/
393#define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss     */
394#define PPC_IRQ_ADDR_BRK   (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */
395#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
396#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT   
397
398#elif defined(mpc604)
399#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break  */
400#define PPC_IRQ_SYS_MGT  (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */
401#define PPC_IRQ_LAST     PPC_IRQ_SYS_MGT 
402
403#elif defined(mpc860) || defined(mpc821)
404#define PPC_IRQ_EMULATE         (PPC_STD_IRQ_LAST+1) /*0x1000-Software emulation  */
405#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Instruction TLB miss*/
406#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB miss */
407#define PPC_IRQ_INST_ERR        (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction TLB err */
408#define PPC_IRQ_DATA_ERR        (PPC_STD_IRQ_LAST+5) /*0x1400-Data TLB error */
409#define PPC_IRQ_DATA_BPNT       (PPC_STD_IRQ_LAST+6) /*0x1C00-Data breakpoint */
410#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+7) /*0x1D00-Inst breakpoint */
411#define PPC_IRQ_IO_BPNT         (PPC_STD_IRQ_LAST+8) /*0x1E00-Peripheral breakpnt */
412#define PPC_IRQ_DEV_PORT        (PPC_STD_IRQ_LAST+9) /*0x1F00-Development port */
413#define PPC_IRQ_IRQ0            (PPC_STD_IRQ_LAST + 10)
414#define PPC_IRQ_LVL0            (PPC_STD_IRQ_LAST + 11)
415#define PPC_IRQ_IRQ1            (PPC_STD_IRQ_LAST + 12)
416#define PPC_IRQ_LVL1            (PPC_STD_IRQ_LAST + 13)
417#define PPC_IRQ_IRQ2            (PPC_STD_IRQ_LAST + 14)
418#define PPC_IRQ_LVL2            (PPC_STD_IRQ_LAST + 15)
419#define PPC_IRQ_IRQ3            (PPC_STD_IRQ_LAST + 16)
420#define PPC_IRQ_LVL3            (PPC_STD_IRQ_LAST + 17)
421#define PPC_IRQ_IRQ4            (PPC_STD_IRQ_LAST + 18)
422#define PPC_IRQ_LVL4            (PPC_STD_IRQ_LAST + 19)
423#define PPC_IRQ_IRQ5            (PPC_STD_IRQ_LAST + 20)
424#define PPC_IRQ_LVL5            (PPC_STD_IRQ_LAST + 21)
425#define PPC_IRQ_IRQ6            (PPC_STD_IRQ_LAST + 22)
426#define PPC_IRQ_LVL6            (PPC_STD_IRQ_LAST + 23)
427#define PPC_IRQ_IRQ7            (PPC_STD_IRQ_LAST + 24)
428#define PPC_IRQ_LVL7            (PPC_STD_IRQ_LAST + 25)
429#define PPC_IRQ_CPM_ERROR       (PPC_STD_IRQ_LAST + 26)
430#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 27)
431#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 28)
432#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 29)
433#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 30)
434#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 31)
435#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 32)
436#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 33)
437#define PPC_IRQ_CPM_RESERVED_8  (PPC_STD_IRQ_LAST + 34)
438#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 35)
439#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 36)
440#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 37)
441#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 38)
442#define PPC_IRQ_CPM_RESERVED_D  (PPC_STD_IRQ_LAST + 39)
443#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 40)
444#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 41)
445#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 42)
446#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 43)
447#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 44)
448#define PPC_IRQ_CPM_RESERVED_13 (PPC_STD_IRQ_LAST + 45)
449#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 46)
450#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 47)
451#define PPC_IRQ_CPM_SDMA_ERROR  (PPC_STD_IRQ_LAST + 48)
452#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 49)
453#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 50)
454#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 51)
455#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 52)
456#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 53)
457#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 54)
458#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 55)
459#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 56)
460#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 57)
461
462#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC15
463
464#elif defined(mpc8260)
465
466#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB miss*/
467#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Data TLB miss */
468#define PPC_IRQ_DATA_L_MISS     (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB load miss */
469#define PPC_IRQ_DATA_S_MISS     (PPC_STD_IRQ_LAST+4) /*0x1300-Data TLB store miss */
470#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+5) /*0x1400-Inst address breakpoint */
471#define PPC_IRQ_SYS_MGT         (PPC_STD_IRQ_LAST+6) /*0x1500-System Management */
472/* 0x1600 - 0x2F00 reserved */
473#define PPC_IRQ_CPM_NONE        (PPC_STD_IRQ_LAST + 50)
474#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 51)
475#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 52)
476#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 53)
477#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 54)
478#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 55)
479#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 56)
480#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 57)
481#define PPC_IRQ_CPM_IDMA3       (PPC_STD_IRQ_LAST + 58)
482#define PPC_IRQ_CPM_IDMA4       (PPC_STD_IRQ_LAST + 59)
483#define PPC_IRQ_CPM_SDMA        (PPC_STD_IRQ_LAST + 60)
484#define PPC_IRQ_CPM_RES_A       (PPC_STD_IRQ_LAST + 61)
485#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 62)
486#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 63)
487#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 64)
488#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 65)
489#define PPC_IRQ_CPM_TMCNT       (PPC_STD_IRQ_LAST + 66)
490#define PPC_IRQ_CPM_PIT         (PPC_STD_IRQ_LAST + 67)
491#define PPC_IRQ_CPM_RES_B       (PPC_STD_IRQ_LAST + 68)
492#define PPC_IRQ_CPM_IRQ1        (PPC_STD_IRQ_LAST + 69)
493#define PPC_IRQ_CPM_IRQ2        (PPC_STD_IRQ_LAST + 70)
494#define PPC_IRQ_CPM_IRQ3        (PPC_STD_IRQ_LAST + 71)
495#define PPC_IRQ_CPM_IRQ4        (PPC_STD_IRQ_LAST + 72)
496#define PPC_IRQ_CPM_IRQ5        (PPC_STD_IRQ_LAST + 73)
497#define PPC_IRQ_CPM_IRQ6        (PPC_STD_IRQ_LAST + 74)
498#define PPC_IRQ_CPM_IRQ7        (PPC_STD_IRQ_LAST + 75)
499#define PPC_IRQ_CPM_RES_C       (PPC_STD_IRQ_LAST + 76)
500#define PPC_IRQ_CPM_RES_D       (PPC_STD_IRQ_LAST + 77)
501#define PPC_IRQ_CPM_RES_E       (PPC_STD_IRQ_LAST + 78)
502#define PPC_IRQ_CPM_RES_F       (PPC_STD_IRQ_LAST + 79)
503#define PPC_IRQ_CPM_RES_G       (PPC_STD_IRQ_LAST + 80)
504#define PPC_IRQ_CPM_RES_H       (PPC_STD_IRQ_LAST + 81)
505#define PPC_IRQ_CPM_FCC1        (PPC_STD_IRQ_LAST + 82)
506#define PPC_IRQ_CPM_FCC2        (PPC_STD_IRQ_LAST + 83)
507#define PPC_IRQ_CPM_FCC3        (PPC_STD_IRQ_LAST + 84)
508#define PPC_IRQ_CPM_RES_I       (PPC_STD_IRQ_LAST + 85)
509#define PPC_IRQ_CPM_MCC1        (PPC_STD_IRQ_LAST + 86)
510#define PPC_IRQ_CPM_MCC2        (PPC_STD_IRQ_LAST + 87)
511#define PPC_IRQ_CPM_RES_J       (PPC_STD_IRQ_LAST + 88)
512#define PPC_IRQ_CPM_RES_K       (PPC_STD_IRQ_LAST + 89)
513#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 90)
514#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 91)
515#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 92)
516#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 93)
517#define PPC_IRQ_CPM_RES_L       (PPC_STD_IRQ_LAST + 94)
518#define PPC_IRQ_CPM_RES_M       (PPC_STD_IRQ_LAST + 95)
519#define PPC_IRQ_CPM_RES_N       (PPC_STD_IRQ_LAST + 96)
520#define PPC_IRQ_CPM_RES_O       (PPC_STD_IRQ_LAST + 97)
521#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 98)
522#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 99)
523#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 100)
524#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 101)
525#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 102)
526#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 103)
527#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 104)
528#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 105)
529#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 106)
530#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 107)
531#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 108)
532#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 109)
533#define PPC_IRQ_CPM_PC3         (PPC_STD_IRQ_LAST + 110)
534#define PPC_IRQ_CPM_PC2         (PPC_STD_IRQ_LAST + 111)
535#define PPC_IRQ_CPM_PC1         (PPC_STD_IRQ_LAST + 112)
536#define PPC_IRQ_CPM_PC0         (PPC_STD_IRQ_LAST + 113)
537
538#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC0
539
540#endif
541
542
543/*
544 *  If the maximum number of exception sources is too low,
545 *  then fix it
546 */
547
548#if PPC_INTERRUPT_MAX <= PPC_IRQ_LAST
549#undef PPC_INTERRUPT_MAX
550#define PPC_INTERRUPT_MAX ((PPC_IRQ_LAST) + 1)
551#endif
552
553/*
554 *  Machine Status Register (MSR) Constants Used by RTEMS
555 */
556
557#if PPC_HAS_RI
558#define PPC_MSR_RI       0x000000002 /* bit 30 - recoverable exception */
559#endif
560
561#define PPC_MSR_DR       0x000000010 /* bit 27 - data address translation */
562#define PPC_MSR_IR       0x000000020 /* bit 26 - instruction addr translation*/
563
564/*
565 *  Some PPC model manuals refer to the Exception Prefix (EP) bit as
566 *  IP for no apparent reason.
567 */
568#if (PPC_HAS_EXCEPTION_PREFIX)
569#define PPC_MSR_EP       0x000000040 /* bit 25 - exception prefix */
570#else
571#define PPC_MSR_EP       0x000000000 /* bit 25 - exception prefix */
572#endif
573
574#if (PPC_HAS_FPU)
575#define PPC_MSR_FP       0x000002000 /* bit 18 - floating point enable */
576#else
577#define PPC_MSR_FP       0x000000000 /* bit 18 - floating point enable */
578#endif
579
580#if (PPC_LOW_POWER_MODE == PPC_LOW_POWER_MODE_NONE)
581#define PPC_MSR_POW      0x000000000 /* bit 13 - power management enable */
582#else
583#define PPC_MSR_POW      0x000040000 /* bit 13 - power management enable */
584#endif
585
586#define PPC_MSR_ME       0x000001000 /* bit 19 - machine check enable */
587#define PPC_MSR_EE       0x000008000 /* bit 16 - external interrupt enable */
588
589#if (PPC_HAS_RFCI)
590#define PPC_MSR_CE       0x000020000 /* bit 14 - critical interrupt enable */
591#else
592#define PPC_MSR_CE       0x000000000 /* bit 14 - critical interrupt enable */
593#endif
594
595#define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE)
596
597#define PPC_MINIMUM_STACK_FRAME_SIZE PPC_STACK_ALIGNMENT
598
599#ifdef __cplusplus
600}
601#endif
602
603#endif /* _RTEMS_POWERPC_POWERPC_H */
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