source: rtems/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h @ cc043dc

4.104.114.84.9
Last change on this file since cc043dc was cc043dc, checked in by Ralf Corsepius <ralf.corsepius@…>, on Feb 17, 2005 at 4:23:18 AM

2005-02-17 Ralf Corsepius <ralf.corsepius@…>

  • new-exceptions/cpu.c, rtems/powerpc/powerpc.h: Remove CPU_MINIMUM_STACK_FRAME_SIZE. Use PPC_MINIMUM_STACK_FRAME_SIZE instead.
  • rtems/powerpc/powerpc.h: Add PPC_MINIMUM_STACK_FRAME_SIZE.
  • Property mode set to 100644
File size: 21.6 KB
Line 
1/**
2 * @file rtems/score/powerpc.h
3 */
4
5/*
6 *  This file contains definitions for the IBM/Motorola PowerPC
7 *  family members.
8 *
9 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
10 *
11 *  COPYRIGHT (c) 1995 by i-cubed ltd.
12 *
13 *  MPC860 support code was added by Jay Monkman <jmonkman@frasca.com>
14 *  MPC8260 support added by Andy Dachs <a.dachs@sstl.co.uk>
15 *  Surrey Satellite Technology Limited
16 *
17 *  To anyone who acknowledges that this file is provided "AS IS"
18 *  without any express or implied warranty:
19 *      permission to use, copy, modify, and distribute this file
20 *      for any purpose is hereby granted without fee, provided that
21 *      the above copyright notice and this notice appears in all
22 *      copies, and that the name of i-cubed limited not be used in
23 *      advertising or publicity pertaining to distribution of the
24 *      software without specific, written prior permission.
25 *      i-cubed limited makes no representations about the suitability
26 *      of this software for any purpose.
27 *
28 *  Derived from c/src/exec/cpu/no_cpu/no_cpu.h:
29 *
30 *  COPYRIGHT (c) 1989-1997.
31 *  On-Line Applications Research Corporation (OAR).
32 *
33 *  The license and distribution terms for this file may in
34 *  the file LICENSE in this distribution or at
35 *  http://www.rtems.com/license/LICENSE.
36 *
37 *
38 * Note:
39 *      This file is included by both C and assembler code ( -DASM )
40 *
41 *  $Id$
42 */
43
44
45#ifndef _RTEMS_POWERPC_POWERPC_H
46#define _RTEMS_POWERPC_POWERPC_H
47
48#ifdef __cplusplus
49extern "C" {
50#endif
51
52#include <rtems/score/powerpc.h>
53
54/*
55 *  Define the name of the CPU family.
56 */
57
58#define CPU_NAME "PowerPC"
59
60/*
61 *  This file contains the information required to build
62 *  RTEMS for a particular member of the PowerPC family.  It does
63 *  this by setting variables to indicate which implementation
64 *  dependent features are present in a particular member
65 *  of the family.
66 *
67 *  The following architectural feature definitions are defaulted
68 *  unless specifically set by the model definition:
69 *
70 *    + PPC_INTERRUPT_MAX        - 16
71 *    + PPC_CACHE_ALIGNMENT      - 32
72 *    + PPC_LOW_POWER_MODE       - PPC_LOW_POWER_MODE_NONE
73 *    + PPC_HAS_EXCEPTION_PREFIX - 1
74 *    + PPC_HAS_FPU              - 1
75 *    + PPC_HAS_DOUBLE           - 1 if PPC_HAS_FPU,
76 *                               - 0 otherwise
77 *    + PPC_USE_MULTIPLE         - 0
78 */
79 
80/*
81 *  Define the low power mode models
82 *
83 *  Standard:   as defined for 603e
84 *  Nap Mode:   nap mode only (604)
85 *  XXX 403GB, 603, 603e, 604, 821
86 */
87
88#define PPC_LOW_POWER_MODE_NONE      0
89#define PPC_LOW_POWER_MODE_STANDARD  1
90
91/*
92 *  Figure out all CPU Model Feature Flags based upon compiler
93 *  predefines.
94 */
95
96#if defined(ppc403) || defined(ppc405)
97/*
98 *  IBM 403
99 *
100 *  Developed for 403GA.  Book checked for 403GB.
101 *
102 *  Does not have user mode.
103 */
104 
105#if defined(ppc403)
106#define CPU_MODEL_NAME "PowerPC 403"
107#elif defined (ppc405)
108#define CPU_MODEL_NAME "PowerPC 405"
109#endif
110#define PPC_CACHE_ALIGNMENT     16
111#define PPC_HAS_RFCI            1
112#define PPC_USE_MULTIPLE        1
113#define PPC_I_CACHE             2048
114#define PPC_D_CACHE             1024
115
116#define PPC_HAS_EXCEPTION_PREFIX 0
117#define PPC_HAS_EVPR             1
118
119#elif defined(mpc555)
120
121#define CPU_MODEL_NAME  "PowerPC 555"
122
123/* Copied from mpc505 */
124#define PPC_CACHE_ALIGNMENT     16
125
126/* Added by querbach@realtime.bc.ca */
127#define PPC_LOW_POWER_MODE      PPC_LOW_POWER_MODE_STANDARD
128
129/* Based on comments by Sergei Organov <osv@Javad.RU> */
130#define PPC_I_CACHE             0
131#define PPC_D_CACHE             0
132
133#elif defined(mpc505) || defined(mpc509)
134/*
135 *  Submitted by Sergei Organov <osv@Javad.RU> as a patch against
136 *  3.6.0 long after 4.0 was released.   This is just an attempt
137 *  to get the setting correct.
138 */
139
140#define CPU_MODEL_NAME  "PowerPC 505/509"
141
142#define PPC_CACHE_ALIGNMENT     16
143#define PPC_I_CACHE             4096
144#define PPC_D_CACHE             0
145
146
147#elif defined(ppc601)
148
149/*
150 *  Submitted with original port -- book checked only.
151 */
152 
153#define CPU_MODEL_NAME  "PowerPC 601"
154
155#define PPC_USE_MULTIPLE        1
156#define PPC_I_CACHE             0
157#define PPC_D_CACHE             32768
158
159#elif defined(ppc602)
160/*
161 *  Submitted with original port -- book checked only.
162 */
163 
164#define CPU_MODEL_NAME  "PowerPC 602"
165
166#define PPC_HAS_DOUBLE          0
167#define PPC_I_CACHE             4096
168#define PPC_D_CACHE             4096
169
170#elif defined(ppc603)
171/*
172 *  Submitted with original port -- book checked only.
173 */
174 
175#define CPU_MODEL_NAME  "PowerPC 603"
176
177#define PPC_I_CACHE             8192
178#define PPC_D_CACHE             8192
179
180#elif defined(ppc603e)
181 
182#define CPU_MODEL_NAME  "PowerPC 603e"
183/*
184 *  Submitted with original port.
185 *
186 *  Known to work on real hardware.
187 */
188
189#define PPC_I_CACHE             16384
190#define PPC_D_CACHE             16384
191
192#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD
193
194#elif defined(mpc604)
195/*
196 *  Submitted with original port -- book checked only.
197 */
198 
199#define CPU_MODEL_NAME  "PowerPC 604"
200
201#define PPC_I_CACHE             16384
202#define PPC_D_CACHE             16384
203 
204#elif defined(mpc860)
205/*
206 *  Added by Jay Monkman (jmonkman@frasca.com) 6/28/98
207 *  with some changes by Darlene Stewart (Darlene.Stewart@iit.nrc.ca)
208 */ 
209#define CPU_MODEL_NAME  "PowerPC MPC860"
210
211#define PPC_I_CACHE             4096
212#define PPC_D_CACHE             4096
213#define PPC_CACHE_ALIGNMENT     16
214#define PPC_INTERRUPT_MAX       71
215#define PPC_USE_MULTIPLE        1
216
217#define PPC_MSR_0               0x00009000
218#define PPC_MSR_1               0x00001000
219#define PPC_MSR_2               0x00001000
220#define PPC_MSR_3               0x00000000
221
222#elif defined(mpc821)
223/*
224 *  Added by Andrew Bray <andy@chaos.org.uk> 6/April/1999
225 */ 
226#define CPU_MODEL_NAME  "PowerPC MPC821"
227
228#define PPC_I_CACHE             4096
229#define PPC_D_CACHE             4096
230#define PPC_CACHE_ALIGNMENT     16
231#define PPC_INTERRUPT_MAX       71
232
233#define PPC_MSR_0               0x00009000
234#define PPC_MSR_1               0x00001000
235#define PPC_MSR_2               0x00001000
236#define PPC_MSR_3               0x00000000
237
238#elif defined(mpc750)
239
240#define CPU_MODEL_NAME  "PowerPC 750"
241
242#define PPC_I_CACHE             16384
243#define PPC_D_CACHE             16384
244
245#elif defined(mpc7400)
246
247#define CPU_MODEL_NAME  "PowerPC 7400"
248
249#define PPC_I_CACHE             32768
250#define PPC_D_CACHE             32768
251
252#elif defined(mpc7455)
253/*
254 *  Added by S.K. Feng <feng1@bnl.gov> 10/03
255 */
256
257#define CPU_MODEL_NAME  "PowerPC 7455"
258
259#define PPC_CACHE_ALIGNMENT     32
260#define PPC_I_CACHE             32768
261#define PPC_D_CACHE             32768
262
263#elif defined(mpc8260)
264/*
265 *  Added by Andy Dachs <a.dachs@sstl.co.uk> 23/11/2000
266 */
267#define CPU_MODEL_NAME  "PowerPC MPC8260"
268
269#define PPC_I_CACHE             16384
270#define PPC_D_CACHE             16384
271#define PPC_CACHE_ALIGNMENT     32
272#define PPC_INTERRUPT_MAX       125
273#define PPC_USE_MULTIPLE        1
274#else
275 
276#error "Unsupported CPU Model"
277 
278#endif
279
280/*
281 *  Application binary interfaces.
282 *
283 *  PPC_ABI MUST be defined as one of these.
284 *  Only big endian is currently supported.
285 */
286/*
287 *  SVR4 ABI
288 */
289#define PPC_ABI_SVR4            2
290/*
291 *  Embedded ABI
292 */
293#define PPC_ABI_EABI            3
294
295/*
296 *  Default to the EABI used by current GNU tools
297 */
298
299#ifndef PPC_ABI
300#define PPC_ABI PPC_ABI_EABI
301#endif
302
303#if (PPC_ABI == PPC_ABI_SVR4)
304#define PPC_STACK_ALIGNMENT     16
305#elif (PPC_ABI == PPC_ABI_EABI)
306#define PPC_STACK_ALIGNMENT     8
307#else
308#error  "PPC_ABI is not properly defined"
309#endif
310
311/*
312 *  Assemblers.
313 *  PPC_ASM MUST be defined as one of these.
314 *
315 *  PPC_ASM_ELF:   ELF assembler. Currently used for all ABIs.
316 *
317 *  NOTE: Only PPC_ABI_ELF is currently fully supported.
318 */
319
320#define PPC_ASM_ELF   0
321
322/*
323 *  Default to the assembler format used by the current GNU tools.
324 */
325
326#ifndef PPC_ASM
327#define PPC_ASM PPC_ASM_ELF
328#endif
329
330/*
331 *  If the maximum number of exception sources has not been defined,
332 *  then default it to 16.
333 */
334
335#ifndef PPC_INTERRUPT_MAX
336#define PPC_INTERRUPT_MAX       16
337#endif
338
339/*
340 *  Unless specified otherwise, the cache line size is defaulted to 32.
341 *
342 *  The derive the power of 2 the cache line is.
343 */
344
345#ifndef PPC_CACHE_ALIGNMENT
346#define PPC_CACHE_ALIGNMENT 32
347#endif
348
349#if (PPC_CACHE_ALIGNMENT == 16)
350#define PPC_CACHE_ALIGN_POWER 4
351#elif (PPC_CACHE_ALIGNMENT == 32)
352#define PPC_CACHE_ALIGN_POWER 5
353#else
354#error "Undefined power of 2 for PPC_CACHE_ALIGNMENT"
355#endif
356
357/*
358 *  Unless otherwise specified, assume the model has an IP/EP bit to
359 *  set the exception address prefix.
360 */
361
362#ifndef PPC_HAS_EXCEPTION_PREFIX
363#define PPC_HAS_EXCEPTION_PREFIX 1
364#endif
365
366/*
367 *  Unless otherwise specified, assume the model does NOT have
368 *  403 style EVPR register to set the exception address prefix.
369 */
370
371#ifndef PPC_HAS_EVPR
372#define PPC_HAS_EVPR 0
373#endif
374
375/*
376 *  If no low power mode model was specified, then assume there is none.
377 */
378
379#ifndef PPC_LOW_POWER_MODE
380#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_NONE
381#endif
382
383/*
384 *  Unless specified above, assume PPC_HAS_FPU to be a synonym for _SOFT_FLOAT.
385 *  FIXME: Should we tie PPC_HAS_FPU to _SOFT_FLOAT, directly
386 *     and disallow explicitly setting PPC_HAS_FPU?
387 */
388
389#ifndef PPC_HAS_FPU
390#ifdef _SOFT_FLOAT
391#define PPC_HAS_FPU 0
392#else
393#define PPC_HAS_FPU 1
394#endif
395#endif
396
397/*
398 *  Unless specified above, If the model has FP support, it is assumed to
399 *  support doubles (8-byte floating point numbers).
400 *
401 *  If the model does NOT have FP support, then the model does
402 *  NOT have double length FP registers.
403 */
404
405#ifndef PPC_HAS_DOUBLE
406#if (PPC_HAS_FPU)
407#define PPC_HAS_DOUBLE 1
408#else
409#define PPC_HAS_DOUBLE 0
410#endif
411#endif
412
413/*
414 *  Unless specified above, then assume the model does NOT have critical
415 *  interrupt support.
416 */
417
418#ifndef PPC_HAS_RFCI
419#define PPC_HAS_RFCI 0
420#endif
421
422/*
423 *  Unless specified above, do not use the load/store multiple instructions
424 *  in a context switch.
425 */
426
427#ifndef PPC_USE_MULTIPLE
428#define PPC_USE_MULTIPLE 0
429#endif
430
431/*
432 *  The following exceptions are not maskable, and are not
433 *  necessarily predictable, so cannot be offered to RTEMS:
434 *    Alignment exception - handled by the CPU module
435 *    Data exceptions.
436 *    Instruction exceptions.
437 */
438
439/*
440 *  Base Interrupt vectors supported on all models.
441 */
442#define PPC_IRQ_SYSTEM_RESET     0 /* 0x00100 - System reset.              */
443#define PPC_IRQ_MCHECK           1 /* 0x00200 - Machine check              */
444#define PPC_IRQ_PROTECT          2 /* 0x00300 - Protection violation       */
445#define PPC_IRQ_ISI              3 /* 0x00400 - Instruction Fetch error    */
446#define PPC_IRQ_EXTERNAL         4 /* 0x00500 - External interrupt         */
447#define PPC_IRQ_ALIGNMENT        5 /* 0X00600 - Alignment exception        */
448#define PPC_IRQ_PROGRAM          6 /* 0x00700 - Program exception          */
449#define PPC_IRQ_NOFP             7 /* 0x00800 - Floating point unavailable */
450#define PPC_IRQ_DECREMENTER      8 /* 0x00900 - Decrementer interrupt      */
451#define PPC_IRQ_RESERVED_A       9 /* 0x00a00 - Implementation Reserved    */
452#define PPC_IRQ_RESERVED_B      10 /* 0x00b00 - Implementation Reserved    */
453#define PPC_IRQ_SCALL           11 /* 0x00c00 - System call                */
454#define PPC_IRQ_TRACE           12 /* 0x00d00 - Trace Exception            */
455#define PPC_IRQ_FP_ASST         13 /* ox00e00 - Floating point assist      */
456#define PPC_STD_IRQ_LAST        PPC_IRQ_FP_ASST
457
458#define PPC_IRQ_FIRST           PPC_IRQ_SYSTEM_RESET
459
460#if defined(ppc403) || defined(ppc405)
461                                 
462#define PPC_IRQ_CRIT     PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */
463#define PPC_IRQ_PIT      (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/
464#define PPC_IRQ_FIT      (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer  */
465#define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer    */
466#define PPC_IRQ_DEBUG    (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions  */
467#define PPC_IRQ_LAST     PPC_IRQ_DEBUG
468
469#elif defined(mpc505) || defined(mpc509)
470#define PPC_IRQ_SOFTEMU   (PPC_STD_IRQ_LAST+1)    /* Software emulation. */
471#define PPC_IRQ_DATA_BP   (PPC_STD_IRQ_LAST+ 2)
472#define PPC_IRQ_INST_BP   (PPC_STD_IRQ_LAST+ 3)
473#define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+ 4)
474#define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+ 5)
475
476#elif defined(mpc555)
477#define PPC_IRQ_SOFTEMU   (PPC_STD_IRQ_LAST+1)  /* Software emulation. */
478#define PPC_IRQ_INST_PE   (PPC_STD_IRQ_LAST+2)  /* Insn protection error */
479#define PPC_IRQ_DATA_PE   (PPC_STD_IRQ_LAST+3)  /* Data protection error */
480#define PPC_IRQ_DATA_BP   (PPC_STD_IRQ_LAST+4)  /* Data breakpoint */
481#define PPC_IRQ_INST_BP   (PPC_STD_IRQ_LAST+5)  /* Insn breakpoint */
482#define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+6)  /* Maskable ext bkpt */
483#define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+7)  /* Non-maskable ext bkpt */
484#define PPC_IRQ_LAST      PPC_IRQ_NMEXT_BP
485
486#elif defined(ppc601)
487#define PPC_IRQ_TRACE    (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/
488#define PPC_IRQ_LAST     PPC_IRQ_TRACE       
489
490#elif defined(ppc602)
491#define PPC_IRQ_LAST     (PPC_STD_IRQ_LAST)
492
493#elif defined(ppc603) || defined(ppc603e)
494#define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/
495#define PPC_IRQ_DATA_LOAD  (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/
496#define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss     */
497#define PPC_IRQ_ADDR_BRK   (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */
498#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
499#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT   
500
501#elif defined(mpc604)
502#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break  */
503#define PPC_IRQ_SYS_MGT  (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */
504#define PPC_IRQ_LAST     PPC_IRQ_SYS_MGT 
505
506#elif defined(mpc860) || defined(mpc821)
507#define PPC_IRQ_EMULATE         (PPC_STD_IRQ_LAST+1) /*0x1000-Software emulation  */
508#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Instruction TLB miss*/
509#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB miss */
510#define PPC_IRQ_INST_ERR        (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction TLB err */
511#define PPC_IRQ_DATA_ERR        (PPC_STD_IRQ_LAST+5) /*0x1400-Data TLB error */
512#define PPC_IRQ_DATA_BPNT       (PPC_STD_IRQ_LAST+6) /*0x1C00-Data breakpoint */
513#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+7) /*0x1D00-Inst breakpoint */
514#define PPC_IRQ_IO_BPNT         (PPC_STD_IRQ_LAST+8) /*0x1E00-Peripheral breakpnt */
515#define PPC_IRQ_DEV_PORT        (PPC_STD_IRQ_LAST+9) /*0x1F00-Development port */
516#define PPC_IRQ_IRQ0            (PPC_STD_IRQ_LAST + 10)
517#define PPC_IRQ_LVL0            (PPC_STD_IRQ_LAST + 11)
518#define PPC_IRQ_IRQ1            (PPC_STD_IRQ_LAST + 12)
519#define PPC_IRQ_LVL1            (PPC_STD_IRQ_LAST + 13)
520#define PPC_IRQ_IRQ2            (PPC_STD_IRQ_LAST + 14)
521#define PPC_IRQ_LVL2            (PPC_STD_IRQ_LAST + 15)
522#define PPC_IRQ_IRQ3            (PPC_STD_IRQ_LAST + 16)
523#define PPC_IRQ_LVL3            (PPC_STD_IRQ_LAST + 17)
524#define PPC_IRQ_IRQ4            (PPC_STD_IRQ_LAST + 18)
525#define PPC_IRQ_LVL4            (PPC_STD_IRQ_LAST + 19)
526#define PPC_IRQ_IRQ5            (PPC_STD_IRQ_LAST + 20)
527#define PPC_IRQ_LVL5            (PPC_STD_IRQ_LAST + 21)
528#define PPC_IRQ_IRQ6            (PPC_STD_IRQ_LAST + 22)
529#define PPC_IRQ_LVL6            (PPC_STD_IRQ_LAST + 23)
530#define PPC_IRQ_IRQ7            (PPC_STD_IRQ_LAST + 24)
531#define PPC_IRQ_LVL7            (PPC_STD_IRQ_LAST + 25)
532#define PPC_IRQ_CPM_ERROR       (PPC_STD_IRQ_LAST + 26)
533#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 27)
534#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 28)
535#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 29)
536#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 30)
537#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 31)
538#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 32)
539#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 33)
540#define PPC_IRQ_CPM_RESERVED_8  (PPC_STD_IRQ_LAST + 34)
541#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 35)
542#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 36)
543#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 37)
544#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 38)
545#define PPC_IRQ_CPM_RESERVED_D  (PPC_STD_IRQ_LAST + 39)
546#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 40)
547#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 41)
548#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 42)
549#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 43)
550#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 44)
551#define PPC_IRQ_CPM_RESERVED_13 (PPC_STD_IRQ_LAST + 45)
552#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 46)
553#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 47)
554#define PPC_IRQ_CPM_SDMA_ERROR  (PPC_STD_IRQ_LAST + 48)
555#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 49)
556#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 50)
557#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 51)
558#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 52)
559#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 53)
560#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 54)
561#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 55)
562#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 56)
563#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 57)
564
565#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC15
566
567#elif defined(mpc8260)
568
569#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB miss*/
570#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Data TLB miss */
571#define PPC_IRQ_DATA_L_MISS     (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB load miss */
572#define PPC_IRQ_DATA_S_MISS     (PPC_STD_IRQ_LAST+4) /*0x1300-Data TLB store miss */
573#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+5) /*0x1400-Inst address breakpoint */
574#define PPC_IRQ_SYS_MGT         (PPC_STD_IRQ_LAST+6) /*0x1500-System Management */
575/* 0x1600 - 0x2F00 reserved */
576#define PPC_IRQ_CPM_NONE        (PPC_STD_IRQ_LAST + 50)
577#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 51)
578#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 52)
579#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 53)
580#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 54)
581#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 55)
582#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 56)
583#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 57)
584#define PPC_IRQ_CPM_IDMA3       (PPC_STD_IRQ_LAST + 58)
585#define PPC_IRQ_CPM_IDMA4       (PPC_STD_IRQ_LAST + 59)
586#define PPC_IRQ_CPM_SDMA        (PPC_STD_IRQ_LAST + 60)
587#define PPC_IRQ_CPM_RES_A       (PPC_STD_IRQ_LAST + 61)
588#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 62)
589#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 63)
590#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 64)
591#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 65)
592#define PPC_IRQ_CPM_TMCNT       (PPC_STD_IRQ_LAST + 66)
593#define PPC_IRQ_CPM_PIT         (PPC_STD_IRQ_LAST + 67)
594#define PPC_IRQ_CPM_RES_B       (PPC_STD_IRQ_LAST + 68)
595#define PPC_IRQ_CPM_IRQ1        (PPC_STD_IRQ_LAST + 69)
596#define PPC_IRQ_CPM_IRQ2        (PPC_STD_IRQ_LAST + 70)
597#define PPC_IRQ_CPM_IRQ3        (PPC_STD_IRQ_LAST + 71)
598#define PPC_IRQ_CPM_IRQ4        (PPC_STD_IRQ_LAST + 72)
599#define PPC_IRQ_CPM_IRQ5        (PPC_STD_IRQ_LAST + 73)
600#define PPC_IRQ_CPM_IRQ6        (PPC_STD_IRQ_LAST + 74)
601#define PPC_IRQ_CPM_IRQ7        (PPC_STD_IRQ_LAST + 75)
602#define PPC_IRQ_CPM_RES_C       (PPC_STD_IRQ_LAST + 76)
603#define PPC_IRQ_CPM_RES_D       (PPC_STD_IRQ_LAST + 77)
604#define PPC_IRQ_CPM_RES_E       (PPC_STD_IRQ_LAST + 78)
605#define PPC_IRQ_CPM_RES_F       (PPC_STD_IRQ_LAST + 79)
606#define PPC_IRQ_CPM_RES_G       (PPC_STD_IRQ_LAST + 80)
607#define PPC_IRQ_CPM_RES_H       (PPC_STD_IRQ_LAST + 81)
608#define PPC_IRQ_CPM_FCC1        (PPC_STD_IRQ_LAST + 82)
609#define PPC_IRQ_CPM_FCC2        (PPC_STD_IRQ_LAST + 83)
610#define PPC_IRQ_CPM_FCC3        (PPC_STD_IRQ_LAST + 84)
611#define PPC_IRQ_CPM_RES_I       (PPC_STD_IRQ_LAST + 85)
612#define PPC_IRQ_CPM_MCC1        (PPC_STD_IRQ_LAST + 86)
613#define PPC_IRQ_CPM_MCC2        (PPC_STD_IRQ_LAST + 87)
614#define PPC_IRQ_CPM_RES_J       (PPC_STD_IRQ_LAST + 88)
615#define PPC_IRQ_CPM_RES_K       (PPC_STD_IRQ_LAST + 89)
616#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 90)
617#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 91)
618#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 92)
619#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 93)
620#define PPC_IRQ_CPM_RES_L       (PPC_STD_IRQ_LAST + 94)
621#define PPC_IRQ_CPM_RES_M       (PPC_STD_IRQ_LAST + 95)
622#define PPC_IRQ_CPM_RES_N       (PPC_STD_IRQ_LAST + 96)
623#define PPC_IRQ_CPM_RES_O       (PPC_STD_IRQ_LAST + 97)
624#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 98)
625#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 99)
626#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 100)
627#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 101)
628#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 102)
629#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 103)
630#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 104)
631#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 105)
632#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 106)
633#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 107)
634#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 108)
635#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 109)
636#define PPC_IRQ_CPM_PC3         (PPC_STD_IRQ_LAST + 110)
637#define PPC_IRQ_CPM_PC2         (PPC_STD_IRQ_LAST + 111)
638#define PPC_IRQ_CPM_PC1         (PPC_STD_IRQ_LAST + 112)
639#define PPC_IRQ_CPM_PC0         (PPC_STD_IRQ_LAST + 113)
640
641#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC0
642
643#endif
644
645
646/*
647 *  If the maximum number of exception sources is too low,
648 *  then fix it
649 */
650
651#if PPC_INTERRUPT_MAX <= PPC_IRQ_LAST
652#undef PPC_INTERRUPT_MAX
653#define PPC_INTERRUPT_MAX ((PPC_IRQ_LAST) + 1)
654#endif
655
656/*
657 *  Machine Status Register (MSR) Constants Used by RTEMS
658 */
659
660/*
661 *  Some PPC model manuals refer to the Exception Prefix (EP) bit as
662 *  IP for no apparent reason.
663 */
664
665#define PPC_MSR_RI       0x000000002 /* bit 30 - recoverable exception */
666#define PPC_MSR_DR       0x000000010 /* bit 27 - data address translation */
667#define PPC_MSR_IR       0x000000020 /* bit 26 - instruction addr translation*/
668
669#if (PPC_HAS_EXCEPTION_PREFIX)
670#define PPC_MSR_EP       0x000000040 /* bit 25 - exception prefix */
671#else
672#define PPC_MSR_EP       0x000000000 /* bit 25 - exception prefix */
673#endif
674
675#if (PPC_HAS_FPU)
676#define PPC_MSR_FP       0x000002000 /* bit 18 - floating point enable */
677#else
678#define PPC_MSR_FP       0x000000000 /* bit 18 - floating point enable */
679#endif
680
681#if (PPC_LOW_POWER_MODE == PPC_LOW_POWER_MODE_NONE)
682#define PPC_MSR_POW      0x000000000 /* bit 13 - power management enable */
683#else
684#define PPC_MSR_POW      0x000040000 /* bit 13 - power management enable */
685#endif
686
687#define PPC_MSR_ME       0x000001000 /* bit 19 - machine check enable */
688#define PPC_MSR_EE       0x000008000 /* bit 16 - external interrupt enable */
689
690#if (PPC_HAS_RFCI)
691#define PPC_MSR_CE       0x000020000 /* bit 14 - critical interrupt enable */
692#else
693#define PPC_MSR_CE       0x000000000 /* bit 14 - critical interrupt enable */
694#endif
695
696#define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE)
697
698/*
699 *  Initial value for the FPSCR register
700 */
701
702#define PPC_INIT_FPSCR          0x000000f8
703
704
705#define PPC_MINIMUM_STACK_FRAME_SIZE PPC_STACK_ALIGNMENT
706
707#ifdef __cplusplus
708}
709#endif
710
711#endif /* _RTEMS_SCORE_POWERPC_H */
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