source: rtems/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h @ 83d7232

4.104.114.84.95
Last change on this file since 83d7232 was 83d7232, checked in by Eric Norum <WENorum@…>, on Oct 20, 2004 at 3:42:24 PM

Add Kate Feng's MVME5500 BSP.

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1/*  powerpc.h
2 *
3 *  This file contains definitions for the IBM/Motorola PowerPC
4 *  family members.
5 *
6 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
7 *
8 *  COPYRIGHT (c) 1995 by i-cubed ltd.
9 *
10 *  MPC860 support code was added by Jay Monkman <jmonkman@frasca.com>
11 *  MPC8260 support added by Andy Dachs <a.dachs@sstl.co.uk>
12 *  Surrey Satellite Technology Limited
13 *
14 *  To anyone who acknowledges that this file is provided "AS IS"
15 *  without any express or implied warranty:
16 *      permission to use, copy, modify, and distribute this file
17 *      for any purpose is hereby granted without fee, provided that
18 *      the above copyright notice and this notice appears in all
19 *      copies, and that the name of i-cubed limited not be used in
20 *      advertising or publicity pertaining to distribution of the
21 *      software without specific, written prior permission.
22 *      i-cubed limited makes no representations about the suitability
23 *      of this software for any purpose.
24 *
25 *  Derived from c/src/exec/cpu/no_cpu/no_cpu.h:
26 *
27 *  COPYRIGHT (c) 1989-1997.
28 *  On-Line Applications Research Corporation (OAR).
29 *
30 *  The license and distribution terms for this file may in
31 *  the file LICENSE in this distribution or at
32 *  http://www.rtems.com/license/LICENSE.
33 *
34 *
35 * Note:
36 *      This file is included by both C and assembler code ( -DASM )
37 *
38 *  $Id$
39 */
40
41
42#ifndef _INCLUDE_PPC_h
43#define _INCLUDE_PPC_h
44
45#ifdef __cplusplus
46extern "C" {
47#endif
48
49#include <rtems/score/types.h>
50
51/*
52 *  Define the name of the CPU family.
53 */
54
55#define CPU_NAME "PowerPC"
56
57/*
58 *  This file contains the information required to build
59 *  RTEMS for a particular member of the PowerPC family.  It does
60 *  this by setting variables to indicate which implementation
61 *  dependent features are present in a particular member
62 *  of the family.
63 *
64 *  The following architectural feature definitions are defaulted
65 *  unless specifically set by the model definition:
66 *
67 *    + PPC_INTERRUPT_MAX        - 16
68 *    + PPC_CACHE_ALIGNMENT      - 32
69 *    + PPC_LOW_POWER_MODE       - PPC_LOW_POWER_MODE_NONE
70 *    + PPC_HAS_EXCEPTION_PREFIX - 1
71 *    + PPC_HAS_FPU              - 1
72 *    + PPC_HAS_DOUBLE           - 1 if PPC_HAS_FPU,
73 *                               - 0 otherwise
74 *    + PPC_USE_MULTIPLE         - 0
75 */
76 
77/*
78 *  Define the low power mode models
79 *
80 *  Standard:   as defined for 603e
81 *  Nap Mode:   nap mode only (604)
82 *  XXX 403GB, 603, 603e, 604, 821
83 */
84
85#define PPC_LOW_POWER_MODE_NONE      0
86#define PPC_LOW_POWER_MODE_STANDARD  1
87
88/*
89 *  Figure out all CPU Model Feature Flags based upon compiler
90 *  predefines.
91 */
92
93#if defined(ppc403) || defined(ppc405)
94/*
95 *  IBM 403
96 *
97 *  Developed for 403GA.  Book checked for 403GB.
98 *
99 *  Does not have user mode.
100 */
101 
102#if defined(ppc403)
103#define CPU_MODEL_NAME "PowerPC 403"
104#elif defined (ppc405)
105#define CPU_MODEL_NAME "PowerPC 405"
106#endif
107#define PPC_ALIGNMENT           4 
108#define PPC_CACHE_ALIGNMENT     16
109#define PPC_HAS_RFCI            1
110#define PPC_HAS_FPU             0
111#define PPC_USE_MULTIPLE        1
112#define PPC_I_CACHE             2048
113#define PPC_D_CACHE             1024
114
115#define PPC_HAS_EXCEPTION_PREFIX 0
116#define PPC_HAS_EVPR             1
117
118#elif defined(mpc555)
119
120#define CPU_MODEL_NAME  "PowerPC 555"
121
122/* Copied from mpc505 */
123#define PPC_ALIGNMENT           4
124#define PPC_CACHE_ALIGNMENT     16
125
126/* Added by querbach@realtime.bc.ca */
127#define PPC_LOW_POWER_MODE      PPC_LOW_POWER_MODE_STANDARD
128
129/* Based on comments by Sergei Organov <osv@Javad.RU> */
130#define PPC_I_CACHE             0
131#define PPC_D_CACHE             0
132
133#elif defined(mpc505) || defined(mpc509)
134/*
135 *  Submitted by Sergei Organov <osv@Javad.RU> as a patch against
136 *  3.6.0 long after 4.0 was released.   This is just an attempt
137 *  to get the setting correct.
138 */
139
140#define CPU_MODEL_NAME  "PowerPC 505/509"
141
142#define PPC_ALIGNMENT           4
143#define PPC_CACHE_ALIGNMENT     16
144#define PPC_I_CACHE             4096
145#define PPC_D_CACHE             0
146
147
148#elif defined(ppc601)
149
150/*
151 *  Submitted with original port -- book checked only.
152 */
153 
154#define CPU_MODEL_NAME  "PowerPC 601"
155
156#define PPC_ALIGNMENT           8
157#define PPC_USE_MULTIPLE        1
158#define PPC_I_CACHE             0
159#define PPC_D_CACHE             32768
160
161#elif defined(ppc602)
162/*
163 *  Submitted with original port -- book checked only.
164 */
165 
166#define CPU_MODEL_NAME  "PowerPC 602"
167
168#define PPC_ALIGNMENT           4
169#define PPC_HAS_DOUBLE          0
170#define PPC_I_CACHE             4096
171#define PPC_D_CACHE             4096
172
173#elif defined(ppc603)
174/*
175 *  Submitted with original port -- book checked only.
176 */
177 
178#define CPU_MODEL_NAME  "PowerPC 603"
179
180#define PPC_ALIGNMENT           8
181#define PPC_I_CACHE             8192
182#define PPC_D_CACHE             8192
183
184#elif defined(ppc603e)
185 
186#define CPU_MODEL_NAME  "PowerPC 603e"
187/*
188 *  Submitted with original port.
189 *
190 *  Known to work on real hardware.
191 */
192
193#define PPC_ALIGNMENT           8
194#define PPC_I_CACHE             16384
195#define PPC_D_CACHE             16384
196
197#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD
198
199#elif defined(mpc604)
200/*
201 *  Submitted with original port -- book checked only.
202 */
203 
204#define CPU_MODEL_NAME  "PowerPC 604"
205
206#define PPC_ALIGNMENT           8
207#define PPC_I_CACHE             16384
208#define PPC_D_CACHE             16384
209 
210#elif defined(mpc860)
211/*
212 *  Added by Jay Monkman (jmonkman@frasca.com) 6/28/98
213 *  with some changes by Darlene Stewart (Darlene.Stewart@iit.nrc.ca)
214 */ 
215#define CPU_MODEL_NAME  "PowerPC MPC860"
216
217#define PPC_ALIGNMENT           4
218#define PPC_I_CACHE             4096
219#define PPC_D_CACHE             4096
220#define PPC_CACHE_ALIGNMENT     16
221#define PPC_INTERRUPT_MAX       71
222#define PPC_HAS_FPU             0
223#define PPC_HAS_DOUBLE          0
224#define PPC_USE_MULTIPLE        1
225
226#define PPC_MSR_0               0x00009000
227#define PPC_MSR_1               0x00001000
228#define PPC_MSR_2               0x00001000
229#define PPC_MSR_3               0x00000000
230
231#elif defined(mpc821)
232/*
233 *  Added by Andrew Bray <andy@chaos.org.uk> 6/April/1999
234 */ 
235#define CPU_MODEL_NAME  "PowerPC MPC821"
236
237#define PPC_ALIGNMENT           4
238#define PPC_I_CACHE             4096
239#define PPC_D_CACHE             4096
240#define PPC_CACHE_ALIGNMENT     16
241#define PPC_INTERRUPT_MAX       71
242#define PPC_HAS_FPU             0
243#define PPC_HAS_DOUBLE          0
244
245#define PPC_MSR_0               0x00009000
246#define PPC_MSR_1               0x00001000
247#define PPC_MSR_2               0x00001000
248#define PPC_MSR_3               0x00000000
249
250#elif defined(mpc750)
251
252#define CPU_MODEL_NAME  "PowerPC 750"
253
254#define PPC_ALIGNMENT           8
255#define PPC_I_CACHE             16384
256#define PPC_D_CACHE             16384
257
258#elif defined(mpc7400)
259
260#define CPU_MODEL_NAME  "PowerPC 7400"
261
262#define PPC_ALIGNMENT           8
263#define PPC_I_CACHE             32768
264#define PPC_D_CACHE             32768
265
266#elif defined(mpc7455)
267/*
268 *  Added by S.K. Feng <feng1@bnl.gov> 10/03
269 */
270
271#define CPU_MODEL_NAME  "PowerPC 7455"
272
273#define PPC_ALIGNMENT           8
274#define PPC_CACHE_ALIGNMENT     32
275#define PPC_I_CACHE             32768
276#define PPC_D_CACHE             32768
277
278#elif defined(mpc8260)
279/*
280 *  Added by Andy Dachs <a.dachs@sstl.co.uk> 23/11/2000
281 */
282#define CPU_MODEL_NAME  "PowerPC MPC8260"
283
284#define PPC_ALIGNMENT           4
285#define PPC_I_CACHE             16384
286#define PPC_D_CACHE             16384
287#define PPC_CACHE_ALIGNMENT     32
288#define PPC_INTERRUPT_MAX       125
289/*#define PPC_HAS_FPU           0 */    /* my 8260 is one the few with no FPU */
290#define PPC_HAS_FPU             1       /* the rest do have one */
291#define PPC_HAS_DOUBLE          1
292#define PPC_USE_MULTIPLE        1
293#else
294 
295#error "Unsupported CPU Model"
296 
297#endif
298
299/*
300 *  Application binary interfaces.
301 *
302 *  PPC_ABI MUST be defined as one of these.
303 *  Only PPC_ABI_POWEROPEN is currently fully supported.
304 *  Only EABI will be supported in the end when
305 *  the tools are there.
306 *  Only big endian is currently supported.
307 */
308/*
309 *  PowerOpen ABI.  This is Andy's hack of the
310 *  PowerOpen ABI to ELF.  ELF rather than a
311 *  XCOFF assembler is used.  This may work
312 *  if PPC_ASM == PPC_ASM_XCOFF is defined.
313 */
314#define PPC_ABI_POWEROPEN       0
315/*
316 *  GCC 2.7.0 munched version of EABI, with
317 *  PowerOpen calling convention and stack frames,
318 *  but EABI style indirect function calls.
319 */
320#define PPC_ABI_GCC27           1
321/*
322 *  SVR4 ABI
323 */
324#define PPC_ABI_SVR4            2
325/*
326 *  Embedded ABI
327 */
328#define PPC_ABI_EABI            3
329
330/*
331 *  Default to the EABI used by current GNU tools
332 */
333
334#ifndef PPC_ABI
335#define PPC_ABI PPC_ABI_EABI
336#endif
337
338#if (PPC_ABI == PPC_ABI_POWEROPEN)
339#define PPC_STACK_ALIGNMENT     8
340#elif (PPC_ABI == PPC_ABI_GCC27)
341#define PPC_STACK_ALIGNMENT     8
342#elif (PPC_ABI == PPC_ABI_SVR4)
343#define PPC_STACK_ALIGNMENT     16
344#elif (PPC_ABI == PPC_ABI_EABI)
345#define PPC_STACK_ALIGNMENT     8
346#else
347#error  "PPC_ABI is not properly defined"
348#endif
349#ifndef PPC_ABI
350#error  "PPC_ABI is not properly defined"
351#endif
352
353/*
354 *  Assemblers.
355 *  PPC_ASM MUST be defined as one of these.
356 *
357 *  PPC_ASM_ELF:   ELF assembler. Currently used for all ABIs.
358 *  PPC_ASM_XCOFF: XCOFF assembler. May be needed for PowerOpen ABI.
359 *
360 *  NOTE: Only PPC_ABI_ELF is currently fully supported.
361 */
362
363#define PPC_ASM_ELF   0
364#define PPC_ASM_XCOFF 1
365
366/*
367 *  Default to the assembler format used by the current GNU tools.
368 */
369
370#ifndef PPC_ASM
371#define PPC_ASM PPC_ASM_ELF
372#endif
373
374/*
375 *  If the maximum number of exception sources has not been defined,
376 *  then default it to 16.
377 */
378
379#ifndef PPC_INTERRUPT_MAX
380#define PPC_INTERRUPT_MAX       16
381#endif
382
383/*
384 *  Unless specified otherwise, the cache line size is defaulted to 32.
385 *
386 *  The derive the power of 2 the cache line is.
387 */
388
389#ifndef PPC_CACHE_ALIGNMENT
390#define PPC_CACHE_ALIGNMENT 32
391#endif
392
393#if (PPC_CACHE_ALIGNMENT == 16)
394#define PPC_CACHE_ALIGN_POWER 4
395#elif (PPC_CACHE_ALIGNMENT == 32)
396#define PPC_CACHE_ALIGN_POWER 5
397#else
398#error "Undefined power of 2 for PPC_CACHE_ALIGNMENT"
399#endif
400
401/*
402 *  Unless otherwise specified, assume the model has an IP/EP bit to
403 *  set the exception address prefix.
404 */
405
406#ifndef PPC_HAS_EXCEPTION_PREFIX
407#define PPC_HAS_EXCEPTION_PREFIX 1
408#endif
409
410/*
411 *  Unless otherwise specified, assume the model does NOT have
412 *  403 style EVPR register to set the exception address prefix.
413 */
414
415#ifndef PPC_HAS_EVPR
416#define PPC_HAS_EVPR 0
417#endif
418
419/*
420 *  If no low power mode model was specified, then assume there is none.
421 */
422
423#ifndef PPC_LOW_POWER_MODE
424#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_NONE
425#endif
426
427/*
428 *  Unless specified above, then assume the model has FP support.
429 */
430
431#ifndef PPC_HAS_FPU
432#define PPC_HAS_FPU 1
433#endif
434
435/*
436 *  Unless specified above, If the model has FP support, it is assumed to
437 *  support doubles (8-byte floating point numbers).
438 *
439 *  If the model does NOT have FP support, then the model does
440 *  NOT have double length FP registers.
441 */
442
443#ifndef PPC_HAS_DOUBLE
444#if (PPC_HAS_FPU)
445#define PPC_HAS_DOUBLE 1
446#else
447#define PPC_HAS_DOUBLE 0
448#endif
449#endif
450
451/*
452 *  Unless specified above, then assume the model does NOT have critical
453 *  interrupt support.
454 */
455
456#ifndef PPC_HAS_RFCI
457#define PPC_HAS_RFCI 0
458#endif
459
460/*
461 *  Unless specified above, do not use the load/store multiple instructions
462 *  in a context switch.
463 */
464
465#ifndef PPC_USE_MULTIPLE
466#define PPC_USE_MULTIPLE 0
467#endif
468
469/*
470 *  The following exceptions are not maskable, and are not
471 *  necessarily predictable, so cannot be offered to RTEMS:
472 *    Alignment exception - handled by the CPU module
473 *    Data exceptions.
474 *    Instruction exceptions.
475 */
476
477/*
478 *  Base Interrupt vectors supported on all models.
479 */
480#define PPC_IRQ_SYSTEM_RESET     0 /* 0x00100 - System reset.              */
481#define PPC_IRQ_MCHECK           1 /* 0x00200 - Machine check              */
482#define PPC_IRQ_PROTECT          2 /* 0x00300 - Protection violation       */
483#define PPC_IRQ_ISI              3 /* 0x00400 - Instruction Fetch error    */
484#define PPC_IRQ_EXTERNAL         4 /* 0x00500 - External interrupt         */
485#define PPC_IRQ_ALIGNMENT        5 /* 0X00600 - Alignment exception        */
486#define PPC_IRQ_PROGRAM          6 /* 0x00700 - Program exception          */
487#define PPC_IRQ_NOFP             7 /* 0x00800 - Floating point unavailable */
488#define PPC_IRQ_DECREMENTER      8 /* 0x00900 - Decrementer interrupt      */
489#define PPC_IRQ_RESERVED_A       9 /* 0x00a00 - Implementation Reserved    */
490#define PPC_IRQ_RESERVED_B      10 /* 0x00b00 - Implementation Reserved    */
491#define PPC_IRQ_SCALL           11 /* 0x00c00 - System call                */
492#define PPC_IRQ_TRACE           12 /* 0x00d00 - Trace Exception            */
493#define PPC_IRQ_FP_ASST         13 /* ox00e00 - Floating point assist      */
494#define PPC_STD_IRQ_LAST        PPC_IRQ_FP_ASST
495
496#define PPC_IRQ_FIRST           PPC_IRQ_SYSTEM_RESET
497
498#if defined(ppc403) || defined(ppc405)
499                                 
500#define PPC_IRQ_CRIT     PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */
501#define PPC_IRQ_PIT      (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/
502#define PPC_IRQ_FIT      (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer  */
503#define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer    */
504#define PPC_IRQ_DEBUG    (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions  */
505#define PPC_IRQ_LAST     PPC_IRQ_DEBUG
506
507#elif defined(mpc505) || defined(mpc509)
508#define PPC_IRQ_SOFTEMU   (PPC_STD_IRQ_LAST+1)    /* Software emulation. */
509#define PPC_IRQ_DATA_BP   (PPC_STD_IRQ_LAST+ 2)
510#define PPC_IRQ_INST_BP   (PPC_STD_IRQ_LAST+ 3)
511#define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+ 4)
512#define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+ 5)
513
514#elif defined(mpc555)
515#define PPC_IRQ_SOFTEMU   (PPC_STD_IRQ_LAST+1)  /* Software emulation. */
516#define PPC_IRQ_INST_PE   (PPC_STD_IRQ_LAST+2)  /* Insn protection error */
517#define PPC_IRQ_DATA_PE   (PPC_STD_IRQ_LAST+3)  /* Data protection error */
518#define PPC_IRQ_DATA_BP   (PPC_STD_IRQ_LAST+4)  /* Data breakpoint */
519#define PPC_IRQ_INST_BP   (PPC_STD_IRQ_LAST+5)  /* Insn breakpoint */
520#define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+6)  /* Maskable ext bkpt */
521#define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+7)  /* Non-maskable ext bkpt */
522#define PPC_IRQ_LAST      PPC_IRQ_NMEXT_BP
523
524#elif defined(ppc601)
525#define PPC_IRQ_TRACE    (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/
526#define PPC_IRQ_LAST     PPC_IRQ_TRACE       
527
528#elif defined(ppc602)
529#define PPC_IRQ_LAST     (PPC_STD_IRQ_LAST)
530
531#elif defined(ppc603)
532#define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/
533#define PPC_IRQ_DATA_LOAD  (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/
534#define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss     */
535#define PPC_IRQ_ADDR_BRK   (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */
536#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
537#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT   
538
539#elif defined(ppc603e)
540#define PPC_TLB_INST_MISS  (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB Miss*/
541#define PPC_TLB_LOAD_MISS  (PPC_STD_IRQ_LAST+2) /*0x1100-TLB miss on load  */
542#define PPC_TLB_STORE_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-TLB Miss on store */
543#define PPC_IRQ_ADDRBRK    (PPC_STD_IRQ_LAST+4) /*0x1300-Instruct addr break */
544#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
545#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT   
546
547
548#elif defined(mpc604)
549#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break  */
550#define PPC_IRQ_SYS_MGT  (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */
551#define PPC_IRQ_LAST     PPC_IRQ_SYS_MGT 
552
553#elif defined(mpc860) || defined(mpc821)
554#define PPC_IRQ_EMULATE         (PPC_STD_IRQ_LAST+1) /*0x1000-Software emulation  */
555#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Instruction TLB miss*/
556#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB miss */
557#define PPC_IRQ_INST_ERR        (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction TLB err */
558#define PPC_IRQ_DATA_ERR        (PPC_STD_IRQ_LAST+5) /*0x1400-Data TLB error */
559#define PPC_IRQ_DATA_BPNT       (PPC_STD_IRQ_LAST+6) /*0x1C00-Data breakpoint */
560#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+7) /*0x1D00-Inst breakpoint */
561#define PPC_IRQ_IO_BPNT         (PPC_STD_IRQ_LAST+8) /*0x1E00-Peripheral breakpnt */
562#define PPC_IRQ_DEV_PORT        (PPC_STD_IRQ_LAST+9) /*0x1F00-Development port */
563#define PPC_IRQ_IRQ0            (PPC_STD_IRQ_LAST + 10)
564#define PPC_IRQ_LVL0            (PPC_STD_IRQ_LAST + 11)
565#define PPC_IRQ_IRQ1            (PPC_STD_IRQ_LAST + 12)
566#define PPC_IRQ_LVL1            (PPC_STD_IRQ_LAST + 13)
567#define PPC_IRQ_IRQ2            (PPC_STD_IRQ_LAST + 14)
568#define PPC_IRQ_LVL2            (PPC_STD_IRQ_LAST + 15)
569#define PPC_IRQ_IRQ3            (PPC_STD_IRQ_LAST + 16)
570#define PPC_IRQ_LVL3            (PPC_STD_IRQ_LAST + 17)
571#define PPC_IRQ_IRQ4            (PPC_STD_IRQ_LAST + 18)
572#define PPC_IRQ_LVL4            (PPC_STD_IRQ_LAST + 19)
573#define PPC_IRQ_IRQ5            (PPC_STD_IRQ_LAST + 20)
574#define PPC_IRQ_LVL5            (PPC_STD_IRQ_LAST + 21)
575#define PPC_IRQ_IRQ6            (PPC_STD_IRQ_LAST + 22)
576#define PPC_IRQ_LVL6            (PPC_STD_IRQ_LAST + 23)
577#define PPC_IRQ_IRQ7            (PPC_STD_IRQ_LAST + 24)
578#define PPC_IRQ_LVL7            (PPC_STD_IRQ_LAST + 25)
579#define PPC_IRQ_CPM_ERROR       (PPC_STD_IRQ_LAST + 26)
580#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 27)
581#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 28)
582#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 29)
583#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 30)
584#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 31)
585#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 32)
586#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 33)
587#define PPC_IRQ_CPM_RESERVED_8  (PPC_STD_IRQ_LAST + 34)
588#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 35)
589#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 36)
590#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 37)
591#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 38)
592#define PPC_IRQ_CPM_RESERVED_D  (PPC_STD_IRQ_LAST + 39)
593#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 40)
594#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 41)
595#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 42)
596#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 43)
597#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 44)
598#define PPC_IRQ_CPM_RESERVED_13 (PPC_STD_IRQ_LAST + 45)
599#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 46)
600#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 47)
601#define PPC_IRQ_CPM_SDMA_ERROR  (PPC_STD_IRQ_LAST + 48)
602#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 49)
603#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 50)
604#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 51)
605#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 52)
606#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 53)
607#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 54)
608#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 55)
609#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 56)
610#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 57)
611
612#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC15
613
614#elif defined(mpc8260)
615
616#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB miss*/
617#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Data TLB miss */
618#define PPC_IRQ_DATA_L_MISS     (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB load miss */
619#define PPC_IRQ_DATA_S_MISS     (PPC_STD_IRQ_LAST+4) /*0x1300-Data TLB store miss */
620#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+5) /*0x1400-Inst address breakpoint */
621#define PPC_IRQ_SYS_MGT         (PPC_STD_IRQ_LAST+6) /*0x1500-System Management */
622/* 0x1600 - 0x2F00 reserved */
623#define PPC_IRQ_CPM_NONE        (PPC_STD_IRQ_LAST + 50)
624#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 51)
625#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 52)
626#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 53)
627#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 54)
628#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 55)
629#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 56)
630#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 57)
631#define PPC_IRQ_CPM_IDMA3       (PPC_STD_IRQ_LAST + 58)
632#define PPC_IRQ_CPM_IDMA4       (PPC_STD_IRQ_LAST + 59)
633#define PPC_IRQ_CPM_SDMA        (PPC_STD_IRQ_LAST + 60)
634#define PPC_IRQ_CPM_RES_A       (PPC_STD_IRQ_LAST + 61)
635#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 62)
636#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 63)
637#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 64)
638#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 65)
639#define PPC_IRQ_CPM_TMCNT       (PPC_STD_IRQ_LAST + 66)
640#define PPC_IRQ_CPM_PIT         (PPC_STD_IRQ_LAST + 67)
641#define PPC_IRQ_CPM_RES_B       (PPC_STD_IRQ_LAST + 68)
642#define PPC_IRQ_CPM_IRQ1        (PPC_STD_IRQ_LAST + 69)
643#define PPC_IRQ_CPM_IRQ2        (PPC_STD_IRQ_LAST + 70)
644#define PPC_IRQ_CPM_IRQ3        (PPC_STD_IRQ_LAST + 71)
645#define PPC_IRQ_CPM_IRQ4        (PPC_STD_IRQ_LAST + 72)
646#define PPC_IRQ_CPM_IRQ5        (PPC_STD_IRQ_LAST + 73)
647#define PPC_IRQ_CPM_IRQ6        (PPC_STD_IRQ_LAST + 74)
648#define PPC_IRQ_CPM_IRQ7        (PPC_STD_IRQ_LAST + 75)
649#define PPC_IRQ_CPM_RES_C       (PPC_STD_IRQ_LAST + 76)
650#define PPC_IRQ_CPM_RES_D       (PPC_STD_IRQ_LAST + 77)
651#define PPC_IRQ_CPM_RES_E       (PPC_STD_IRQ_LAST + 78)
652#define PPC_IRQ_CPM_RES_F       (PPC_STD_IRQ_LAST + 79)
653#define PPC_IRQ_CPM_RES_G       (PPC_STD_IRQ_LAST + 80)
654#define PPC_IRQ_CPM_RES_H       (PPC_STD_IRQ_LAST + 81)
655#define PPC_IRQ_CPM_FCC1        (PPC_STD_IRQ_LAST + 82)
656#define PPC_IRQ_CPM_FCC2        (PPC_STD_IRQ_LAST + 83)
657#define PPC_IRQ_CPM_FCC3        (PPC_STD_IRQ_LAST + 84)
658#define PPC_IRQ_CPM_RES_I       (PPC_STD_IRQ_LAST + 85)
659#define PPC_IRQ_CPM_MCC1        (PPC_STD_IRQ_LAST + 86)
660#define PPC_IRQ_CPM_MCC2        (PPC_STD_IRQ_LAST + 87)
661#define PPC_IRQ_CPM_RES_J       (PPC_STD_IRQ_LAST + 88)
662#define PPC_IRQ_CPM_RES_K       (PPC_STD_IRQ_LAST + 89)
663#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 90)
664#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 91)
665#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 92)
666#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 93)
667#define PPC_IRQ_CPM_RES_L       (PPC_STD_IRQ_LAST + 94)
668#define PPC_IRQ_CPM_RES_M       (PPC_STD_IRQ_LAST + 95)
669#define PPC_IRQ_CPM_RES_N       (PPC_STD_IRQ_LAST + 96)
670#define PPC_IRQ_CPM_RES_O       (PPC_STD_IRQ_LAST + 97)
671#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 98)
672#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 99)
673#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 100)
674#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 101)
675#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 102)
676#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 103)
677#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 104)
678#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 105)
679#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 106)
680#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 107)
681#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 108)
682#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 109)
683#define PPC_IRQ_CPM_PC3         (PPC_STD_IRQ_LAST + 110)
684#define PPC_IRQ_CPM_PC2         (PPC_STD_IRQ_LAST + 111)
685#define PPC_IRQ_CPM_PC1         (PPC_STD_IRQ_LAST + 112)
686#define PPC_IRQ_CPM_PC0         (PPC_STD_IRQ_LAST + 113)
687
688#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC0
689
690#endif
691
692
693/*
694 *  If the maximum number of exception sources is too low,
695 *  then fix it
696 */
697
698#if PPC_INTERRUPT_MAX <= PPC_IRQ_LAST
699#undef PPC_INTERRUPT_MAX
700#define PPC_INTERRUPT_MAX ((PPC_IRQ_LAST) + 1)
701#endif
702
703/*
704 *  Machine Status Register (MSR) Constants Used by RTEMS
705 */
706
707/*
708 *  Some PPC model manuals refer to the Exception Prefix (EP) bit as
709 *  IP for no apparent reason.
710 */
711
712#define PPC_MSR_RI       0x000000002 /* bit 30 - recoverable exception */
713#define PPC_MSR_DR       0x000000010 /* bit 27 - data address translation */
714#define PPC_MSR_IR       0x000000020 /* bit 26 - instruction addr translation*/
715
716#if (PPC_HAS_EXCEPTION_PREFIX)
717#define PPC_MSR_EP       0x000000040 /* bit 25 - exception prefix */
718#else
719#define PPC_MSR_EP       0x000000000 /* bit 25 - exception prefix */
720#endif
721
722#if (PPC_HAS_FPU)
723#define PPC_MSR_FP       0x000002000 /* bit 18 - floating point enable */
724#else
725#define PPC_MSR_FP       0x000000000 /* bit 18 - floating point enable */
726#endif
727
728#if (PPC_LOW_POWER_MODE == PPC_LOW_POWER_MODE_NONE)
729#define PPC_MSR_POW      0x000000000 /* bit 13 - power management enable */
730#else
731#define PPC_MSR_POW      0x000040000 /* bit 13 - power management enable */
732#endif
733
734#define PPC_MSR_ME       0x000001000 /* bit 19 - machine check enable */
735#define PPC_MSR_EE       0x000008000 /* bit 16 - external interrupt enable */
736
737#if (PPC_HAS_RFCI)
738#define PPC_MSR_CE       0x000020000 /* bit 14 - critical interrupt enable */
739#else
740#define PPC_MSR_CE       0x000000000 /* bit 14 - critical interrupt enable */
741#endif
742
743#define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE)
744
745/*
746 *  Initial value for the FPSCR register
747 */
748
749#define PPC_INIT_FPSCR          0x000000f8
750
751#ifdef __cplusplus
752}
753#endif
754
755#endif /* ! _INCLUDE_PPC_h */
756/* end of include file */
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