source: rtems/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h @ 73cdeb6

4.104.114.84.95
Last change on this file since 73cdeb6 was 73cdeb6, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on 07/04/07 at 12:25:49

merged individual exception handler code to a common one.
  • Property mode set to 100644
File size: 21.8 KB
Line 
1/**
2 * @file rtems/score/powerpc.h
3 */
4
5/*
6 *  This file contains definitions for the IBM/Motorola PowerPC
7 *  family members.
8 *
9 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
10 *
11 *  COPYRIGHT (c) 1995 by i-cubed ltd.
12 *
13 *  MPC860 support code was added by Jay Monkman <jmonkman@frasca.com>
14 *  MPC8260 support added by Andy Dachs <a.dachs@sstl.co.uk>
15 *  Surrey Satellite Technology Limited
16 *
17 *  To anyone who acknowledges that this file is provided "AS IS"
18 *  without any express or implied warranty:
19 *      permission to use, copy, modify, and distribute this file
20 *      for any purpose is hereby granted without fee, provided that
21 *      the above copyright notice and this notice appears in all
22 *      copies, and that the name of i-cubed limited not be used in
23 *      advertising or publicity pertaining to distribution of the
24 *      software without specific, written prior permission.
25 *      i-cubed limited makes no representations about the suitability
26 *      of this software for any purpose.
27 *
28 *  Derived from c/src/exec/cpu/no_cpu/no_cpu.h:
29 *
30 *  COPYRIGHT (c) 1989-1997.
31 *  On-Line Applications Research Corporation (OAR).
32 *
33 *  The license and distribution terms for this file may in
34 *  the file LICENSE in this distribution or at
35 *  http://www.rtems.com/license/LICENSE.
36 *
37 *
38 * Note:
39 *      This file is included by both C and assembler code ( -DASM )
40 *
41 *  $Id$
42 */
43
44
45#ifndef _RTEMS_POWERPC_POWERPC_H
46#define _RTEMS_POWERPC_POWERPC_H
47
48#ifdef __cplusplus
49extern "C" {
50#endif
51
52#include <rtems/score/powerpc.h>
53
54/*
55 *  Define the name of the CPU family.
56 */
57
58#define CPU_NAME "PowerPC"
59
60/*
61 *  This file contains the information required to build
62 *  RTEMS for a particular member of the PowerPC family.  It does
63 *  this by setting variables to indicate which implementation
64 *  dependent features are present in a particular member
65 *  of the family.
66 *
67 *  The following architectural feature definitions are defaulted
68 *  unless specifically set by the model definition:
69 *
70 *    + PPC_INTERRUPT_MAX        - 16
71 *    + PPC_CACHE_ALIGNMENT      - 32
72 *    + PPC_LOW_POWER_MODE       - PPC_LOW_POWER_MODE_NONE
73 *    + PPC_HAS_EXCEPTION_PREFIX - 1
74 *    + PPC_HAS_FPU              - 1
75 *    + PPC_HAS_DOUBLE           - 1 if PPC_HAS_FPU,
76 *                               - 0 otherwise
77 *    + PPC_USE_MULTIPLE         - 0
78 */
79 
80/*
81 *  Define the low power mode models
82 *
83 *  Standard:   as defined for 603e
84 *  Nap Mode:   nap mode only (604)
85 *  XXX 403GB, 603, 603e, 604, 821
86 */
87
88#define PPC_LOW_POWER_MODE_NONE      0
89#define PPC_LOW_POWER_MODE_STANDARD  1
90
91/*
92 *  Figure out all CPU Model Feature Flags based upon compiler
93 *  predefines.
94 */
95
96#if defined(ppc403) || defined(ppc405)
97/*
98 *  IBM 403
99 *
100 *  Developed for 403GA.  Book checked for 403GB.
101 *
102 *  Does not have user mode.
103 */
104 
105#if defined(ppc403)
106#define CPU_MODEL_NAME "PowerPC 403"
107#elif defined (ppc405)
108#define CPU_MODEL_NAME "PowerPC 405"
109#endif
110#define PPC_CACHE_ALIGNMENT     16
111#define PPC_HAS_RI              0
112#define PPC_HAS_RFCI            1
113#define PPC_USE_MULTIPLE        1
114#define PPC_I_CACHE             2048
115#define PPC_D_CACHE             1024
116
117#define PPC_HAS_EXCEPTION_PREFIX 0
118#define PPC_HAS_EVPR             1
119
120#elif defined(mpc555)
121
122#define CPU_MODEL_NAME  "PowerPC 555"
123
124/* Copied from mpc505 */
125#define PPC_CACHE_ALIGNMENT     16
126
127/* Added by querbach@realtime.bc.ca */
128#define PPC_LOW_POWER_MODE      PPC_LOW_POWER_MODE_STANDARD
129
130/* Based on comments by Sergei Organov <osv@Javad.RU> */
131#define PPC_I_CACHE             0
132#define PPC_D_CACHE             0
133
134#elif defined(mpc505) || defined(mpc509)
135/*
136 *  Submitted by Sergei Organov <osv@Javad.RU> as a patch against
137 *  3.6.0 long after 4.0 was released.   This is just an attempt
138 *  to get the setting correct.
139 */
140
141#define CPU_MODEL_NAME  "PowerPC 505/509"
142
143#define PPC_CACHE_ALIGNMENT     16
144#define PPC_I_CACHE             4096
145#define PPC_D_CACHE             0
146
147
148#elif defined(ppc601)
149
150/*
151 *  Submitted with original port -- book checked only.
152 */
153 
154#define CPU_MODEL_NAME  "PowerPC 601"
155
156#define PPC_USE_MULTIPLE        1
157#define PPC_I_CACHE             0
158#define PPC_D_CACHE             32768
159
160#elif defined(ppc602)
161/*
162 *  Submitted with original port -- book checked only.
163 */
164 
165#define CPU_MODEL_NAME  "PowerPC 602"
166
167#define PPC_HAS_DOUBLE          0
168#define PPC_I_CACHE             4096
169#define PPC_D_CACHE             4096
170
171#elif defined(ppc603)
172/*
173 *  Submitted with original port -- book checked only.
174 */
175 
176#define CPU_MODEL_NAME  "PowerPC 603"
177
178#define PPC_I_CACHE             8192
179#define PPC_D_CACHE             8192
180
181#elif defined(ppc603e)
182 
183#define CPU_MODEL_NAME  "PowerPC 603e"
184/*
185 *  Submitted with original port.
186 *
187 *  Known to work on real hardware.
188 */
189
190#define PPC_I_CACHE             16384
191#define PPC_D_CACHE             16384
192
193#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD
194
195#elif defined(mpc604)
196/*
197 *  Submitted with original port -- book checked only.
198 */
199 
200#define CPU_MODEL_NAME  "PowerPC 604"
201
202#define PPC_I_CACHE             16384
203#define PPC_D_CACHE             16384
204 
205#elif defined(mpc860)
206/*
207 *  Added by Jay Monkman (jmonkman@frasca.com) 6/28/98
208 *  with some changes by Darlene Stewart (Darlene.Stewart@iit.nrc.ca)
209 */
210#define CPU_MODEL_NAME  "PowerPC MPC860"
211
212#define PPC_I_CACHE             4096
213#define PPC_D_CACHE             4096
214#define PPC_CACHE_ALIGNMENT     16
215#define PPC_INTERRUPT_MAX       71
216#define PPC_USE_MULTIPLE        1
217
218#define PPC_MSR_0               0x00009000
219#define PPC_MSR_1               0x00001000
220#define PPC_MSR_2               0x00001000
221#define PPC_MSR_3               0x00000000
222
223#elif defined(mpc821)
224/*
225 *  Added by Andrew Bray <andy@chaos.org.uk> 6/April/1999
226 */
227#define CPU_MODEL_NAME  "PowerPC MPC821"
228
229#define PPC_I_CACHE             4096
230#define PPC_D_CACHE             4096
231#define PPC_CACHE_ALIGNMENT     16
232#define PPC_INTERRUPT_MAX       71
233
234#define PPC_MSR_0               0x00009000
235#define PPC_MSR_1               0x00001000
236#define PPC_MSR_2               0x00001000
237#define PPC_MSR_3               0x00000000
238
239#elif defined(mpc750)
240
241#define CPU_MODEL_NAME  "PowerPC 750"
242
243#define PPC_I_CACHE             16384
244#define PPC_D_CACHE             16384
245
246#elif defined(mpc7400)
247
248#define CPU_MODEL_NAME  "PowerPC 7400"
249
250#define PPC_I_CACHE             32768
251#define PPC_D_CACHE             32768
252
253#elif defined(mpc7455)
254/*
255 *  Added by S.K. Feng <feng1@bnl.gov> 10/03
256 */
257
258#define CPU_MODEL_NAME  "PowerPC 7455"
259
260#define PPC_CACHE_ALIGNMENT     32
261#define PPC_I_CACHE             32768
262#define PPC_D_CACHE             32768
263
264#elif defined(mpc8260)
265/*
266 *  Added by Andy Dachs <a.dachs@sstl.co.uk> 23/11/2000
267 */
268#define CPU_MODEL_NAME  "PowerPC MPC8260"
269
270#define PPC_I_CACHE             16384
271#define PPC_D_CACHE             16384
272#define PPC_CACHE_ALIGNMENT     32
273#define PPC_INTERRUPT_MAX       125
274#define PPC_USE_MULTIPLE        1
275#else
276 
277#error "Unsupported CPU Model"
278 
279#endif
280
281/*
282 *  Application binary interfaces.
283 *
284 *  PPC_ABI MUST be defined as one of these.
285 *  Only big endian is currently supported.
286 */
287/*
288 *  SVR4 ABI
289 */
290#define PPC_ABI_SVR4            2
291/*
292 *  Embedded ABI
293 */
294#define PPC_ABI_EABI            3
295
296/*
297 *  Default to the EABI used by current GNU tools
298 */
299
300#ifndef PPC_ABI
301#define PPC_ABI PPC_ABI_EABI
302#endif
303
304#if (PPC_ABI == PPC_ABI_SVR4)
305#define PPC_STACK_ALIGNMENT     16
306#elif (PPC_ABI == PPC_ABI_EABI)
307#define PPC_STACK_ALIGNMENT     8
308#else
309#error  "PPC_ABI is not properly defined"
310#endif
311
312/*
313 *  Assemblers.
314 *  PPC_ASM MUST be defined as one of these.
315 *
316 *  PPC_ASM_ELF:   ELF assembler. Currently used for all ABIs.
317 *
318 *  NOTE: Only PPC_ABI_ELF is currently fully supported.
319 */
320
321#define PPC_ASM_ELF   0
322
323/*
324 *  Default to the assembler format used by the current GNU tools.
325 */
326
327#ifndef PPC_ASM
328#define PPC_ASM PPC_ASM_ELF
329#endif
330
331/*
332 *  If the maximum number of exception sources has not been defined,
333 *  then default it to 16.
334 */
335
336#ifndef PPC_INTERRUPT_MAX
337#define PPC_INTERRUPT_MAX       16
338#endif
339
340/*
341 *  Unless specified otherwise, the cache line size is defaulted to 32.
342 *
343 *  The derive the power of 2 the cache line is.
344 */
345
346#ifndef PPC_CACHE_ALIGNMENT
347#define PPC_CACHE_ALIGNMENT 32
348#endif
349
350#if (PPC_CACHE_ALIGNMENT == 16)
351#define PPC_CACHE_ALIGN_POWER 4
352#elif (PPC_CACHE_ALIGNMENT == 32)
353#define PPC_CACHE_ALIGN_POWER 5
354#else
355#error "Undefined power of 2 for PPC_CACHE_ALIGNMENT"
356#endif
357
358/*
359 *  Unless otherwise specified, assume the model has an IP/EP bit to
360 *  set the exception address prefix.
361 */
362
363#ifndef PPC_HAS_EXCEPTION_PREFIX
364#define PPC_HAS_EXCEPTION_PREFIX 1
365#endif
366/*
367 *  Unless otherwise specified, assume the model has an RI bit to
368 *  identify non-recoverable interrupts
369 */
370
371#ifndef PPC_HAS_RI
372#define PPC_HAS_RI 1
373#endif
374
375/*
376 *  Unless otherwise specified, assume the model does NOT have
377 *  403 style EVPR register to set the exception address prefix.
378 */
379
380#ifndef PPC_HAS_EVPR
381#define PPC_HAS_EVPR 0
382#endif
383
384/*
385 *  If no low power mode model was specified, then assume there is none.
386 */
387
388#ifndef PPC_LOW_POWER_MODE
389#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_NONE
390#endif
391
392/*
393 *  Unless specified above, assume PPC_HAS_FPU to be a synonym for _SOFT_FLOAT.
394 *  FIXME: Should we tie PPC_HAS_FPU to _SOFT_FLOAT, directly
395 *     and disallow explicitly setting PPC_HAS_FPU?
396 */
397
398#ifndef PPC_HAS_FPU
399#ifdef _SOFT_FLOAT
400#define PPC_HAS_FPU 0
401#else
402#define PPC_HAS_FPU 1
403#endif
404#endif
405
406/*
407 *  Unless specified above, If the model has FP support, it is assumed to
408 *  support doubles (8-byte floating point numbers).
409 *
410 *  If the model does NOT have FP support, then the model does
411 *  NOT have double length FP registers.
412 */
413
414#ifndef PPC_HAS_DOUBLE
415#if (PPC_HAS_FPU)
416#define PPC_HAS_DOUBLE 1
417#else
418#define PPC_HAS_DOUBLE 0
419#endif
420#endif
421
422/*
423 *  Unless specified above, then assume the model does NOT have critical
424 *  interrupt support.
425 */
426
427#ifndef PPC_HAS_RFCI
428#define PPC_HAS_RFCI 0
429#endif
430
431/*
432 *  Unless specified above, do not use the load/store multiple instructions
433 *  in a context switch.
434 */
435
436#ifndef PPC_USE_MULTIPLE
437#define PPC_USE_MULTIPLE 0
438#endif
439
440/*
441 *  The following exceptions are not maskable, and are not
442 *  necessarily predictable, so cannot be offered to RTEMS:
443 *    Alignment exception - handled by the CPU module
444 *    Data exceptions.
445 *    Instruction exceptions.
446 */
447
448/*
449 *  Base Interrupt vectors supported on all models.
450 */
451#define PPC_IRQ_SYSTEM_RESET     0 /* 0x00100 - System reset.              */
452#define PPC_IRQ_MCHECK           1 /* 0x00200 - Machine check              */
453#define PPC_IRQ_PROTECT          2 /* 0x00300 - Protection violation       */
454#define PPC_IRQ_ISI              3 /* 0x00400 - Instruction Fetch error    */
455#define PPC_IRQ_EXTERNAL         4 /* 0x00500 - External interrupt         */
456#define PPC_IRQ_ALIGNMENT        5 /* 0X00600 - Alignment exception        */
457#define PPC_IRQ_PROGRAM          6 /* 0x00700 - Program exception          */
458#define PPC_IRQ_NOFP             7 /* 0x00800 - Floating point unavailable */
459#define PPC_IRQ_DECREMENTER      8 /* 0x00900 - Decrementer interrupt      */
460#define PPC_IRQ_RESERVED_A       9 /* 0x00a00 - Implementation Reserved    */
461#define PPC_IRQ_RESERVED_B      10 /* 0x00b00 - Implementation Reserved    */
462#define PPC_IRQ_SCALL           11 /* 0x00c00 - System call                */
463#define PPC_IRQ_TRACE           12 /* 0x00d00 - Trace Exception            */
464#define PPC_IRQ_FP_ASST         13 /* ox00e00 - Floating point assist      */
465#define PPC_STD_IRQ_LAST        PPC_IRQ_FP_ASST
466
467#define PPC_IRQ_FIRST           PPC_IRQ_SYSTEM_RESET
468
469#if defined(ppc403) || defined(ppc405)
470                                 
471#define PPC_IRQ_CRIT     PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */
472#define PPC_IRQ_PIT      (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/
473#define PPC_IRQ_FIT      (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer  */
474#define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer    */
475#define PPC_IRQ_DEBUG    (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions  */
476#define PPC_IRQ_LAST     PPC_IRQ_DEBUG
477
478#elif defined(mpc505) || defined(mpc509)
479#define PPC_IRQ_SOFTEMU   (PPC_STD_IRQ_LAST+1)    /* Software emulation. */
480#define PPC_IRQ_DATA_BP   (PPC_STD_IRQ_LAST+ 2)
481#define PPC_IRQ_INST_BP   (PPC_STD_IRQ_LAST+ 3)
482#define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+ 4)
483#define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+ 5)
484
485#elif defined(mpc555)
486#define PPC_IRQ_SOFTEMU   (PPC_STD_IRQ_LAST+1)  /* Software emulation. */
487#define PPC_IRQ_INST_PE   (PPC_STD_IRQ_LAST+2)  /* Insn protection error */
488#define PPC_IRQ_DATA_PE   (PPC_STD_IRQ_LAST+3)  /* Data protection error */
489#define PPC_IRQ_DATA_BP   (PPC_STD_IRQ_LAST+4)  /* Data breakpoint */
490#define PPC_IRQ_INST_BP   (PPC_STD_IRQ_LAST+5)  /* Insn breakpoint */
491#define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+6)  /* Maskable ext bkpt */
492#define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+7)  /* Non-maskable ext bkpt */
493#define PPC_IRQ_LAST      PPC_IRQ_NMEXT_BP
494
495#elif defined(ppc601)
496#define PPC_IRQ_TRACE    (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/
497#define PPC_IRQ_LAST     PPC_IRQ_TRACE       
498
499#elif defined(ppc602)
500#define PPC_IRQ_LAST     (PPC_STD_IRQ_LAST)
501
502#elif defined(ppc603) || defined(ppc603e)
503#define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/
504#define PPC_IRQ_DATA_LOAD  (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/
505#define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss     */
506#define PPC_IRQ_ADDR_BRK   (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */
507#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
508#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT   
509
510#elif defined(mpc604)
511#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break  */
512#define PPC_IRQ_SYS_MGT  (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */
513#define PPC_IRQ_LAST     PPC_IRQ_SYS_MGT 
514
515#elif defined(mpc860) || defined(mpc821)
516#define PPC_IRQ_EMULATE         (PPC_STD_IRQ_LAST+1) /*0x1000-Software emulation  */
517#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Instruction TLB miss*/
518#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB miss */
519#define PPC_IRQ_INST_ERR        (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction TLB err */
520#define PPC_IRQ_DATA_ERR        (PPC_STD_IRQ_LAST+5) /*0x1400-Data TLB error */
521#define PPC_IRQ_DATA_BPNT       (PPC_STD_IRQ_LAST+6) /*0x1C00-Data breakpoint */
522#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+7) /*0x1D00-Inst breakpoint */
523#define PPC_IRQ_IO_BPNT         (PPC_STD_IRQ_LAST+8) /*0x1E00-Peripheral breakpnt */
524#define PPC_IRQ_DEV_PORT        (PPC_STD_IRQ_LAST+9) /*0x1F00-Development port */
525#define PPC_IRQ_IRQ0            (PPC_STD_IRQ_LAST + 10)
526#define PPC_IRQ_LVL0            (PPC_STD_IRQ_LAST + 11)
527#define PPC_IRQ_IRQ1            (PPC_STD_IRQ_LAST + 12)
528#define PPC_IRQ_LVL1            (PPC_STD_IRQ_LAST + 13)
529#define PPC_IRQ_IRQ2            (PPC_STD_IRQ_LAST + 14)
530#define PPC_IRQ_LVL2            (PPC_STD_IRQ_LAST + 15)
531#define PPC_IRQ_IRQ3            (PPC_STD_IRQ_LAST + 16)
532#define PPC_IRQ_LVL3            (PPC_STD_IRQ_LAST + 17)
533#define PPC_IRQ_IRQ4            (PPC_STD_IRQ_LAST + 18)
534#define PPC_IRQ_LVL4            (PPC_STD_IRQ_LAST + 19)
535#define PPC_IRQ_IRQ5            (PPC_STD_IRQ_LAST + 20)
536#define PPC_IRQ_LVL5            (PPC_STD_IRQ_LAST + 21)
537#define PPC_IRQ_IRQ6            (PPC_STD_IRQ_LAST + 22)
538#define PPC_IRQ_LVL6            (PPC_STD_IRQ_LAST + 23)
539#define PPC_IRQ_IRQ7            (PPC_STD_IRQ_LAST + 24)
540#define PPC_IRQ_LVL7            (PPC_STD_IRQ_LAST + 25)
541#define PPC_IRQ_CPM_ERROR       (PPC_STD_IRQ_LAST + 26)
542#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 27)
543#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 28)
544#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 29)
545#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 30)
546#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 31)
547#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 32)
548#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 33)
549#define PPC_IRQ_CPM_RESERVED_8  (PPC_STD_IRQ_LAST + 34)
550#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 35)
551#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 36)
552#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 37)
553#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 38)
554#define PPC_IRQ_CPM_RESERVED_D  (PPC_STD_IRQ_LAST + 39)
555#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 40)
556#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 41)
557#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 42)
558#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 43)
559#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 44)
560#define PPC_IRQ_CPM_RESERVED_13 (PPC_STD_IRQ_LAST + 45)
561#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 46)
562#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 47)
563#define PPC_IRQ_CPM_SDMA_ERROR  (PPC_STD_IRQ_LAST + 48)
564#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 49)
565#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 50)
566#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 51)
567#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 52)
568#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 53)
569#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 54)
570#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 55)
571#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 56)
572#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 57)
573
574#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC15
575
576#elif defined(mpc8260)
577
578#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB miss*/
579#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Data TLB miss */
580#define PPC_IRQ_DATA_L_MISS     (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB load miss */
581#define PPC_IRQ_DATA_S_MISS     (PPC_STD_IRQ_LAST+4) /*0x1300-Data TLB store miss */
582#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+5) /*0x1400-Inst address breakpoint */
583#define PPC_IRQ_SYS_MGT         (PPC_STD_IRQ_LAST+6) /*0x1500-System Management */
584/* 0x1600 - 0x2F00 reserved */
585#define PPC_IRQ_CPM_NONE        (PPC_STD_IRQ_LAST + 50)
586#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 51)
587#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 52)
588#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 53)
589#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 54)
590#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 55)
591#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 56)
592#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 57)
593#define PPC_IRQ_CPM_IDMA3       (PPC_STD_IRQ_LAST + 58)
594#define PPC_IRQ_CPM_IDMA4       (PPC_STD_IRQ_LAST + 59)
595#define PPC_IRQ_CPM_SDMA        (PPC_STD_IRQ_LAST + 60)
596#define PPC_IRQ_CPM_RES_A       (PPC_STD_IRQ_LAST + 61)
597#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 62)
598#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 63)
599#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 64)
600#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 65)
601#define PPC_IRQ_CPM_TMCNT       (PPC_STD_IRQ_LAST + 66)
602#define PPC_IRQ_CPM_PIT         (PPC_STD_IRQ_LAST + 67)
603#define PPC_IRQ_CPM_RES_B       (PPC_STD_IRQ_LAST + 68)
604#define PPC_IRQ_CPM_IRQ1        (PPC_STD_IRQ_LAST + 69)
605#define PPC_IRQ_CPM_IRQ2        (PPC_STD_IRQ_LAST + 70)
606#define PPC_IRQ_CPM_IRQ3        (PPC_STD_IRQ_LAST + 71)
607#define PPC_IRQ_CPM_IRQ4        (PPC_STD_IRQ_LAST + 72)
608#define PPC_IRQ_CPM_IRQ5        (PPC_STD_IRQ_LAST + 73)
609#define PPC_IRQ_CPM_IRQ6        (PPC_STD_IRQ_LAST + 74)
610#define PPC_IRQ_CPM_IRQ7        (PPC_STD_IRQ_LAST + 75)
611#define PPC_IRQ_CPM_RES_C       (PPC_STD_IRQ_LAST + 76)
612#define PPC_IRQ_CPM_RES_D       (PPC_STD_IRQ_LAST + 77)
613#define PPC_IRQ_CPM_RES_E       (PPC_STD_IRQ_LAST + 78)
614#define PPC_IRQ_CPM_RES_F       (PPC_STD_IRQ_LAST + 79)
615#define PPC_IRQ_CPM_RES_G       (PPC_STD_IRQ_LAST + 80)
616#define PPC_IRQ_CPM_RES_H       (PPC_STD_IRQ_LAST + 81)
617#define PPC_IRQ_CPM_FCC1        (PPC_STD_IRQ_LAST + 82)
618#define PPC_IRQ_CPM_FCC2        (PPC_STD_IRQ_LAST + 83)
619#define PPC_IRQ_CPM_FCC3        (PPC_STD_IRQ_LAST + 84)
620#define PPC_IRQ_CPM_RES_I       (PPC_STD_IRQ_LAST + 85)
621#define PPC_IRQ_CPM_MCC1        (PPC_STD_IRQ_LAST + 86)
622#define PPC_IRQ_CPM_MCC2        (PPC_STD_IRQ_LAST + 87)
623#define PPC_IRQ_CPM_RES_J       (PPC_STD_IRQ_LAST + 88)
624#define PPC_IRQ_CPM_RES_K       (PPC_STD_IRQ_LAST + 89)
625#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 90)
626#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 91)
627#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 92)
628#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 93)
629#define PPC_IRQ_CPM_RES_L       (PPC_STD_IRQ_LAST + 94)
630#define PPC_IRQ_CPM_RES_M       (PPC_STD_IRQ_LAST + 95)
631#define PPC_IRQ_CPM_RES_N       (PPC_STD_IRQ_LAST + 96)
632#define PPC_IRQ_CPM_RES_O       (PPC_STD_IRQ_LAST + 97)
633#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 98)
634#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 99)
635#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 100)
636#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 101)
637#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 102)
638#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 103)
639#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 104)
640#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 105)
641#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 106)
642#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 107)
643#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 108)
644#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 109)
645#define PPC_IRQ_CPM_PC3         (PPC_STD_IRQ_LAST + 110)
646#define PPC_IRQ_CPM_PC2         (PPC_STD_IRQ_LAST + 111)
647#define PPC_IRQ_CPM_PC1         (PPC_STD_IRQ_LAST + 112)
648#define PPC_IRQ_CPM_PC0         (PPC_STD_IRQ_LAST + 113)
649
650#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC0
651
652#endif
653
654
655/*
656 *  If the maximum number of exception sources is too low,
657 *  then fix it
658 */
659
660#if PPC_INTERRUPT_MAX <= PPC_IRQ_LAST
661#undef PPC_INTERRUPT_MAX
662#define PPC_INTERRUPT_MAX ((PPC_IRQ_LAST) + 1)
663#endif
664
665/*
666 *  Machine Status Register (MSR) Constants Used by RTEMS
667 */
668
669#if PPC_HAS_RI
670#define PPC_MSR_RI       0x000000002 /* bit 30 - recoverable exception */
671#endif
672
673#define PPC_MSR_DR       0x000000010 /* bit 27 - data address translation */
674#define PPC_MSR_IR       0x000000020 /* bit 26 - instruction addr translation*/
675
676/*
677 *  Some PPC model manuals refer to the Exception Prefix (EP) bit as
678 *  IP for no apparent reason.
679 */
680#if (PPC_HAS_EXCEPTION_PREFIX)
681#define PPC_MSR_EP       0x000000040 /* bit 25 - exception prefix */
682#else
683#define PPC_MSR_EP       0x000000000 /* bit 25 - exception prefix */
684#endif
685
686#if (PPC_HAS_FPU)
687#define PPC_MSR_FP       0x000002000 /* bit 18 - floating point enable */
688#else
689#define PPC_MSR_FP       0x000000000 /* bit 18 - floating point enable */
690#endif
691
692#if (PPC_LOW_POWER_MODE == PPC_LOW_POWER_MODE_NONE)
693#define PPC_MSR_POW      0x000000000 /* bit 13 - power management enable */
694#else
695#define PPC_MSR_POW      0x000040000 /* bit 13 - power management enable */
696#endif
697
698#define PPC_MSR_ME       0x000001000 /* bit 19 - machine check enable */
699#define PPC_MSR_EE       0x000008000 /* bit 16 - external interrupt enable */
700
701#if (PPC_HAS_RFCI)
702#define PPC_MSR_CE       0x000020000 /* bit 14 - critical interrupt enable */
703#else
704#define PPC_MSR_CE       0x000000000 /* bit 14 - critical interrupt enable */
705#endif
706
707#define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE)
708
709/*
710 *  Initial value for the FPSCR register
711 */
712
713#define PPC_INIT_FPSCR          0x000000f8
714
715
716#define PPC_MINIMUM_STACK_FRAME_SIZE PPC_STACK_ALIGNMENT
717
718#ifdef __cplusplus
719}
720#endif
721
722#endif /* _RTEMS_POWERPC_POWERPC_H */
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