1 | /** |
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2 | * @file rtems/score/powerpc.h |
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3 | */ |
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4 | |
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5 | /* |
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6 | * This file contains definitions for the IBM/Motorola PowerPC |
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7 | * family members. |
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8 | * |
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9 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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10 | * |
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11 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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12 | * |
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13 | * MPC860 support code was added by Jay Monkman <jmonkman@frasca.com> |
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14 | * MPC8260 support added by Andy Dachs <a.dachs@sstl.co.uk> |
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15 | * Surrey Satellite Technology Limited |
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16 | * |
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17 | * To anyone who acknowledges that this file is provided "AS IS" |
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18 | * without any express or implied warranty: |
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19 | * permission to use, copy, modify, and distribute this file |
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20 | * for any purpose is hereby granted without fee, provided that |
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21 | * the above copyright notice and this notice appears in all |
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22 | * copies, and that the name of i-cubed limited not be used in |
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23 | * advertising or publicity pertaining to distribution of the |
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24 | * software without specific, written prior permission. |
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25 | * i-cubed limited makes no representations about the suitability |
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26 | * of this software for any purpose. |
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27 | * |
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28 | * Derived from c/src/exec/cpu/no_cpu/no_cpu.h: |
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29 | * |
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30 | * COPYRIGHT (c) 1989-1997. |
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31 | * On-Line Applications Research Corporation (OAR). |
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32 | * |
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33 | * The license and distribution terms for this file may in |
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34 | * the file LICENSE in this distribution or at |
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35 | * http://www.rtems.com/license/LICENSE. |
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36 | * |
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37 | * |
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38 | * Note: |
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39 | * This file is included by both C and assembler code ( -DASM ) |
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40 | * |
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41 | * $Id$ |
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42 | */ |
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43 | |
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44 | |
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45 | #ifndef _RTEMS_SCORE_POWERPC_H |
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46 | #define _RTEMS_SCORE_POWERPC_H |
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47 | |
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48 | #ifdef __cplusplus |
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49 | extern "C" { |
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50 | #endif |
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51 | |
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52 | #include <rtems/score/types.h> |
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53 | |
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54 | /* |
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55 | * Define the name of the CPU family. |
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56 | */ |
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57 | |
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58 | #define CPU_NAME "PowerPC" |
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59 | |
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60 | /* |
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61 | * This file contains the information required to build |
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62 | * RTEMS for a particular member of the PowerPC family. It does |
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63 | * this by setting variables to indicate which implementation |
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64 | * dependent features are present in a particular member |
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65 | * of the family. |
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66 | * |
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67 | * The following architectural feature definitions are defaulted |
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68 | * unless specifically set by the model definition: |
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69 | * |
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70 | * + PPC_INTERRUPT_MAX - 16 |
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71 | * + PPC_CACHE_ALIGNMENT - 32 |
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72 | * + PPC_LOW_POWER_MODE - PPC_LOW_POWER_MODE_NONE |
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73 | * + PPC_HAS_EXCEPTION_PREFIX - 1 |
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74 | * + PPC_HAS_FPU - 1 |
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75 | * + PPC_HAS_DOUBLE - 1 if PPC_HAS_FPU, |
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76 | * - 0 otherwise |
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77 | * + PPC_USE_MULTIPLE - 0 |
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78 | */ |
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79 | |
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80 | /* |
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81 | * Define the low power mode models |
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82 | * |
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83 | * Standard: as defined for 603e |
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84 | * Nap Mode: nap mode only (604) |
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85 | * XXX 403GB, 603, 603e, 604, 821 |
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86 | */ |
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87 | |
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88 | #define PPC_LOW_POWER_MODE_NONE 0 |
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89 | #define PPC_LOW_POWER_MODE_STANDARD 1 |
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90 | |
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91 | /* |
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92 | * Figure out all CPU Model Feature Flags based upon compiler |
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93 | * predefines. |
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94 | */ |
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95 | |
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96 | #if defined(ppc403) || defined(ppc405) |
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97 | /* |
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98 | * IBM 403 |
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99 | * |
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100 | * Developed for 403GA. Book checked for 403GB. |
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101 | * |
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102 | * Does not have user mode. |
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103 | */ |
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104 | |
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105 | #if defined(ppc403) |
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106 | #define CPU_MODEL_NAME "PowerPC 403" |
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107 | #elif defined (ppc405) |
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108 | #define CPU_MODEL_NAME "PowerPC 405" |
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109 | #endif |
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110 | #define PPC_ALIGNMENT 4 |
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111 | #define PPC_CACHE_ALIGNMENT 16 |
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112 | #define PPC_HAS_RFCI 1 |
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113 | #define PPC_HAS_FPU 0 |
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114 | #define PPC_USE_MULTIPLE 1 |
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115 | #define PPC_I_CACHE 2048 |
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116 | #define PPC_D_CACHE 1024 |
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117 | |
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118 | #define PPC_HAS_EXCEPTION_PREFIX 0 |
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119 | #define PPC_HAS_EVPR 1 |
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120 | |
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121 | #elif defined(mpc555) |
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122 | |
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123 | #define CPU_MODEL_NAME "PowerPC 555" |
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124 | |
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125 | /* Copied from mpc505 */ |
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126 | #define PPC_ALIGNMENT 4 |
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127 | #define PPC_CACHE_ALIGNMENT 16 |
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128 | |
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129 | /* Added by querbach@realtime.bc.ca */ |
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130 | #define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD |
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131 | |
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132 | /* Based on comments by Sergei Organov <osv@Javad.RU> */ |
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133 | #define PPC_I_CACHE 0 |
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134 | #define PPC_D_CACHE 0 |
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135 | |
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136 | #elif defined(mpc505) || defined(mpc509) |
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137 | /* |
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138 | * Submitted by Sergei Organov <osv@Javad.RU> as a patch against |
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139 | * 3.6.0 long after 4.0 was released. This is just an attempt |
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140 | * to get the setting correct. |
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141 | */ |
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142 | |
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143 | #define CPU_MODEL_NAME "PowerPC 505/509" |
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144 | |
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145 | #define PPC_ALIGNMENT 4 |
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146 | #define PPC_CACHE_ALIGNMENT 16 |
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147 | #define PPC_I_CACHE 4096 |
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148 | #define PPC_D_CACHE 0 |
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149 | |
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150 | |
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151 | #elif defined(ppc601) |
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152 | |
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153 | /* |
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154 | * Submitted with original port -- book checked only. |
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155 | */ |
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156 | |
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157 | #define CPU_MODEL_NAME "PowerPC 601" |
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158 | |
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159 | #define PPC_ALIGNMENT 8 |
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160 | #define PPC_USE_MULTIPLE 1 |
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161 | #define PPC_I_CACHE 0 |
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162 | #define PPC_D_CACHE 32768 |
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163 | |
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164 | #elif defined(ppc602) |
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165 | /* |
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166 | * Submitted with original port -- book checked only. |
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167 | */ |
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168 | |
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169 | #define CPU_MODEL_NAME "PowerPC 602" |
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170 | |
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171 | #define PPC_ALIGNMENT 4 |
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172 | #define PPC_HAS_DOUBLE 0 |
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173 | #define PPC_I_CACHE 4096 |
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174 | #define PPC_D_CACHE 4096 |
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175 | |
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176 | #elif defined(ppc603) |
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177 | /* |
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178 | * Submitted with original port -- book checked only. |
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179 | */ |
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180 | |
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181 | #define CPU_MODEL_NAME "PowerPC 603" |
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182 | |
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183 | #define PPC_ALIGNMENT 8 |
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184 | #define PPC_I_CACHE 8192 |
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185 | #define PPC_D_CACHE 8192 |
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186 | |
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187 | #elif defined(ppc603e) |
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188 | |
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189 | #define CPU_MODEL_NAME "PowerPC 603e" |
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190 | /* |
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191 | * Submitted with original port. |
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192 | * |
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193 | * Known to work on real hardware. |
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194 | */ |
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195 | |
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196 | #define PPC_ALIGNMENT 8 |
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197 | #define PPC_I_CACHE 16384 |
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198 | #define PPC_D_CACHE 16384 |
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199 | |
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200 | #define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD |
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201 | |
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202 | #elif defined(mpc604) |
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203 | /* |
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204 | * Submitted with original port -- book checked only. |
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205 | */ |
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206 | |
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207 | #define CPU_MODEL_NAME "PowerPC 604" |
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208 | |
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209 | #define PPC_ALIGNMENT 8 |
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210 | #define PPC_I_CACHE 16384 |
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211 | #define PPC_D_CACHE 16384 |
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212 | |
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213 | #elif defined(mpc860) |
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214 | /* |
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215 | * Added by Jay Monkman (jmonkman@frasca.com) 6/28/98 |
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216 | * with some changes by Darlene Stewart (Darlene.Stewart@iit.nrc.ca) |
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217 | */ |
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218 | #define CPU_MODEL_NAME "PowerPC MPC860" |
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219 | |
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220 | #define PPC_ALIGNMENT 4 |
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221 | #define PPC_I_CACHE 4096 |
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222 | #define PPC_D_CACHE 4096 |
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223 | #define PPC_CACHE_ALIGNMENT 16 |
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224 | #define PPC_INTERRUPT_MAX 71 |
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225 | #define PPC_HAS_FPU 0 |
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226 | #define PPC_HAS_DOUBLE 0 |
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227 | #define PPC_USE_MULTIPLE 1 |
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228 | |
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229 | #define PPC_MSR_0 0x00009000 |
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230 | #define PPC_MSR_1 0x00001000 |
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231 | #define PPC_MSR_2 0x00001000 |
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232 | #define PPC_MSR_3 0x00000000 |
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233 | |
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234 | #elif defined(mpc821) |
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235 | /* |
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236 | * Added by Andrew Bray <andy@chaos.org.uk> 6/April/1999 |
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237 | */ |
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238 | #define CPU_MODEL_NAME "PowerPC MPC821" |
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239 | |
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240 | #define PPC_ALIGNMENT 4 |
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241 | #define PPC_I_CACHE 4096 |
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242 | #define PPC_D_CACHE 4096 |
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243 | #define PPC_CACHE_ALIGNMENT 16 |
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244 | #define PPC_INTERRUPT_MAX 71 |
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245 | #define PPC_HAS_FPU 0 |
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246 | #define PPC_HAS_DOUBLE 0 |
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247 | |
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248 | #define PPC_MSR_0 0x00009000 |
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249 | #define PPC_MSR_1 0x00001000 |
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250 | #define PPC_MSR_2 0x00001000 |
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251 | #define PPC_MSR_3 0x00000000 |
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252 | |
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253 | #elif defined(mpc750) |
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254 | |
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255 | #define CPU_MODEL_NAME "PowerPC 750" |
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256 | |
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257 | #define PPC_ALIGNMENT 8 |
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258 | #define PPC_I_CACHE 16384 |
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259 | #define PPC_D_CACHE 16384 |
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260 | |
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261 | #elif defined(mpc7400) |
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262 | |
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263 | #define CPU_MODEL_NAME "PowerPC 7400" |
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264 | |
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265 | #define PPC_ALIGNMENT 8 |
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266 | #define PPC_I_CACHE 32768 |
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267 | #define PPC_D_CACHE 32768 |
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268 | |
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269 | #elif defined(mpc7455) |
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270 | /* |
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271 | * Added by S.K. Feng <feng1@bnl.gov> 10/03 |
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272 | */ |
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273 | |
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274 | #define CPU_MODEL_NAME "PowerPC 7455" |
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275 | |
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276 | #define PPC_ALIGNMENT 8 |
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277 | #define PPC_CACHE_ALIGNMENT 32 |
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278 | #define PPC_I_CACHE 32768 |
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279 | #define PPC_D_CACHE 32768 |
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280 | |
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281 | #elif defined(mpc8260) |
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282 | /* |
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283 | * Added by Andy Dachs <a.dachs@sstl.co.uk> 23/11/2000 |
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284 | */ |
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285 | #define CPU_MODEL_NAME "PowerPC MPC8260" |
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286 | |
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287 | #define PPC_ALIGNMENT 4 |
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288 | #define PPC_I_CACHE 16384 |
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289 | #define PPC_D_CACHE 16384 |
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290 | #define PPC_CACHE_ALIGNMENT 32 |
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291 | #define PPC_INTERRUPT_MAX 125 |
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292 | /*#define PPC_HAS_FPU 0 */ /* my 8260 is one the few with no FPU */ |
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293 | #define PPC_HAS_FPU 1 /* the rest do have one */ |
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294 | #define PPC_HAS_DOUBLE 1 |
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295 | #define PPC_USE_MULTIPLE 1 |
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296 | #else |
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297 | |
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298 | #error "Unsupported CPU Model" |
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299 | |
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300 | #endif |
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301 | |
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302 | /* |
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303 | * Application binary interfaces. |
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304 | * |
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305 | * PPC_ABI MUST be defined as one of these. |
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306 | * Only PPC_ABI_POWEROPEN is currently fully supported. |
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307 | * Only EABI will be supported in the end when |
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308 | * the tools are there. |
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309 | * Only big endian is currently supported. |
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310 | */ |
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311 | /* |
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312 | * PowerOpen ABI. This is Andy's hack of the |
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313 | * PowerOpen ABI to ELF. ELF rather than a |
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314 | * XCOFF assembler is used. |
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315 | */ |
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316 | #define PPC_ABI_POWEROPEN 0 |
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317 | /* |
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318 | * GCC 2.7.0 munched version of EABI, with |
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319 | * PowerOpen calling convention and stack frames, |
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320 | * but EABI style indirect function calls. |
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321 | */ |
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322 | #define PPC_ABI_GCC27 1 |
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323 | /* |
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324 | * SVR4 ABI |
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325 | */ |
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326 | #define PPC_ABI_SVR4 2 |
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327 | /* |
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328 | * Embedded ABI |
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329 | */ |
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330 | #define PPC_ABI_EABI 3 |
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331 | |
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332 | /* |
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333 | * Default to the EABI used by current GNU tools |
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334 | */ |
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335 | |
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336 | #ifndef PPC_ABI |
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337 | #define PPC_ABI PPC_ABI_EABI |
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338 | #endif |
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339 | |
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340 | #if (PPC_ABI == PPC_ABI_POWEROPEN) |
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341 | #define PPC_STACK_ALIGNMENT 8 |
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342 | #elif (PPC_ABI == PPC_ABI_GCC27) |
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343 | #define PPC_STACK_ALIGNMENT 8 |
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344 | #elif (PPC_ABI == PPC_ABI_SVR4) |
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345 | #define PPC_STACK_ALIGNMENT 16 |
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346 | #elif (PPC_ABI == PPC_ABI_EABI) |
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347 | #define PPC_STACK_ALIGNMENT 8 |
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348 | #else |
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349 | #error "PPC_ABI is not properly defined" |
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350 | #endif |
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351 | #ifndef PPC_ABI |
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352 | #error "PPC_ABI is not properly defined" |
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353 | #endif |
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354 | |
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355 | /* |
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356 | * Assemblers. |
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357 | * PPC_ASM MUST be defined as one of these. |
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358 | * |
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359 | * PPC_ASM_ELF: ELF assembler. Currently used for all ABIs. |
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360 | * |
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361 | * NOTE: Only PPC_ABI_ELF is currently fully supported. |
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362 | */ |
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363 | |
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364 | #define PPC_ASM_ELF 0 |
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365 | |
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366 | /* |
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367 | * Default to the assembler format used by the current GNU tools. |
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368 | */ |
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369 | |
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370 | #ifndef PPC_ASM |
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371 | #define PPC_ASM PPC_ASM_ELF |
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372 | #endif |
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373 | |
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374 | /* |
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375 | * If the maximum number of exception sources has not been defined, |
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376 | * then default it to 16. |
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377 | */ |
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378 | |
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379 | #ifndef PPC_INTERRUPT_MAX |
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380 | #define PPC_INTERRUPT_MAX 16 |
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381 | #endif |
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382 | |
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383 | /* |
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384 | * Unless specified otherwise, the cache line size is defaulted to 32. |
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385 | * |
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386 | * The derive the power of 2 the cache line is. |
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387 | */ |
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388 | |
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389 | #ifndef PPC_CACHE_ALIGNMENT |
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390 | #define PPC_CACHE_ALIGNMENT 32 |
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391 | #endif |
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392 | |
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393 | #if (PPC_CACHE_ALIGNMENT == 16) |
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394 | #define PPC_CACHE_ALIGN_POWER 4 |
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395 | #elif (PPC_CACHE_ALIGNMENT == 32) |
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396 | #define PPC_CACHE_ALIGN_POWER 5 |
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397 | #else |
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398 | #error "Undefined power of 2 for PPC_CACHE_ALIGNMENT" |
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399 | #endif |
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400 | |
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401 | /* |
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402 | * Unless otherwise specified, assume the model has an IP/EP bit to |
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403 | * set the exception address prefix. |
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404 | */ |
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405 | |
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406 | #ifndef PPC_HAS_EXCEPTION_PREFIX |
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407 | #define PPC_HAS_EXCEPTION_PREFIX 1 |
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408 | #endif |
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409 | |
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410 | /* |
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411 | * Unless otherwise specified, assume the model does NOT have |
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412 | * 403 style EVPR register to set the exception address prefix. |
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413 | */ |
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414 | |
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415 | #ifndef PPC_HAS_EVPR |
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416 | #define PPC_HAS_EVPR 0 |
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417 | #endif |
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418 | |
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419 | /* |
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420 | * If no low power mode model was specified, then assume there is none. |
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421 | */ |
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422 | |
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423 | #ifndef PPC_LOW_POWER_MODE |
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424 | #define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_NONE |
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425 | #endif |
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426 | |
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427 | /* |
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428 | * Unless specified above, then assume the model has FP support. |
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429 | */ |
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430 | |
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431 | #ifndef PPC_HAS_FPU |
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432 | #define PPC_HAS_FPU 1 |
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433 | #endif |
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434 | |
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435 | /* |
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436 | * Unless specified above, If the model has FP support, it is assumed to |
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437 | * support doubles (8-byte floating point numbers). |
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438 | * |
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439 | * If the model does NOT have FP support, then the model does |
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440 | * NOT have double length FP registers. |
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441 | */ |
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442 | |
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443 | #ifndef PPC_HAS_DOUBLE |
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444 | #if (PPC_HAS_FPU) |
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445 | #define PPC_HAS_DOUBLE 1 |
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446 | #else |
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447 | #define PPC_HAS_DOUBLE 0 |
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448 | #endif |
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449 | #endif |
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450 | |
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451 | /* |
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452 | * Unless specified above, then assume the model does NOT have critical |
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453 | * interrupt support. |
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454 | */ |
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455 | |
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456 | #ifndef PPC_HAS_RFCI |
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457 | #define PPC_HAS_RFCI 0 |
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458 | #endif |
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459 | |
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460 | /* |
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461 | * Unless specified above, do not use the load/store multiple instructions |
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462 | * in a context switch. |
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463 | */ |
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464 | |
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465 | #ifndef PPC_USE_MULTIPLE |
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466 | #define PPC_USE_MULTIPLE 0 |
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467 | #endif |
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468 | |
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469 | /* |
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470 | * The following exceptions are not maskable, and are not |
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471 | * necessarily predictable, so cannot be offered to RTEMS: |
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472 | * Alignment exception - handled by the CPU module |
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473 | * Data exceptions. |
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474 | * Instruction exceptions. |
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475 | */ |
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476 | |
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477 | /* |
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478 | * Base Interrupt vectors supported on all models. |
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479 | */ |
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480 | #define PPC_IRQ_SYSTEM_RESET 0 /* 0x00100 - System reset. */ |
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481 | #define PPC_IRQ_MCHECK 1 /* 0x00200 - Machine check */ |
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482 | #define PPC_IRQ_PROTECT 2 /* 0x00300 - Protection violation */ |
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483 | #define PPC_IRQ_ISI 3 /* 0x00400 - Instruction Fetch error */ |
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484 | #define PPC_IRQ_EXTERNAL 4 /* 0x00500 - External interrupt */ |
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485 | #define PPC_IRQ_ALIGNMENT 5 /* 0X00600 - Alignment exception */ |
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486 | #define PPC_IRQ_PROGRAM 6 /* 0x00700 - Program exception */ |
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487 | #define PPC_IRQ_NOFP 7 /* 0x00800 - Floating point unavailable */ |
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488 | #define PPC_IRQ_DECREMENTER 8 /* 0x00900 - Decrementer interrupt */ |
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489 | #define PPC_IRQ_RESERVED_A 9 /* 0x00a00 - Implementation Reserved */ |
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490 | #define PPC_IRQ_RESERVED_B 10 /* 0x00b00 - Implementation Reserved */ |
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491 | #define PPC_IRQ_SCALL 11 /* 0x00c00 - System call */ |
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492 | #define PPC_IRQ_TRACE 12 /* 0x00d00 - Trace Exception */ |
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493 | #define PPC_IRQ_FP_ASST 13 /* ox00e00 - Floating point assist */ |
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494 | #define PPC_STD_IRQ_LAST PPC_IRQ_FP_ASST |
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495 | |
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496 | #define PPC_IRQ_FIRST PPC_IRQ_SYSTEM_RESET |
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497 | |
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498 | #if defined(ppc403) || defined(ppc405) |
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499 | |
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500 | #define PPC_IRQ_CRIT PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */ |
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501 | #define PPC_IRQ_PIT (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/ |
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502 | #define PPC_IRQ_FIT (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer */ |
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503 | #define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer */ |
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504 | #define PPC_IRQ_DEBUG (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions */ |
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505 | #define PPC_IRQ_LAST PPC_IRQ_DEBUG |
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506 | |
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507 | #elif defined(mpc505) || defined(mpc509) |
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508 | #define PPC_IRQ_SOFTEMU (PPC_STD_IRQ_LAST+1) /* Software emulation. */ |
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509 | #define PPC_IRQ_DATA_BP (PPC_STD_IRQ_LAST+ 2) |
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510 | #define PPC_IRQ_INST_BP (PPC_STD_IRQ_LAST+ 3) |
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511 | #define PPC_IRQ_MEXT_BP (PPC_STD_IRQ_LAST+ 4) |
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512 | #define PPC_IRQ_NMEXT_BP (PPC_STD_IRQ_LAST+ 5) |
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513 | |
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514 | #elif defined(mpc555) |
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515 | #define PPC_IRQ_SOFTEMU (PPC_STD_IRQ_LAST+1) /* Software emulation. */ |
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516 | #define PPC_IRQ_INST_PE (PPC_STD_IRQ_LAST+2) /* Insn protection error */ |
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517 | #define PPC_IRQ_DATA_PE (PPC_STD_IRQ_LAST+3) /* Data protection error */ |
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518 | #define PPC_IRQ_DATA_BP (PPC_STD_IRQ_LAST+4) /* Data breakpoint */ |
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519 | #define PPC_IRQ_INST_BP (PPC_STD_IRQ_LAST+5) /* Insn breakpoint */ |
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520 | #define PPC_IRQ_MEXT_BP (PPC_STD_IRQ_LAST+6) /* Maskable ext bkpt */ |
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521 | #define PPC_IRQ_NMEXT_BP (PPC_STD_IRQ_LAST+7) /* Non-maskable ext bkpt */ |
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522 | #define PPC_IRQ_LAST PPC_IRQ_NMEXT_BP |
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523 | |
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524 | #elif defined(ppc601) |
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525 | #define PPC_IRQ_TRACE (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/ |
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526 | #define PPC_IRQ_LAST PPC_IRQ_TRACE |
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527 | |
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528 | #elif defined(ppc602) |
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529 | #define PPC_IRQ_LAST (PPC_STD_IRQ_LAST) |
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530 | |
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531 | #elif defined(ppc603) |
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532 | #define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/ |
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533 | #define PPC_IRQ_DATA_LOAD (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/ |
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534 | #define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss */ |
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535 | #define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */ |
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536 | #define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+5) /*0x1400-System Management */ |
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537 | #define PPC_IRQ_LAST PPC_IRQ_SYS_MGT |
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538 | |
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539 | #elif defined(ppc603e) |
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540 | #define PPC_TLB_INST_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB Miss*/ |
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541 | #define PPC_TLB_LOAD_MISS (PPC_STD_IRQ_LAST+2) /*0x1100-TLB miss on load */ |
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542 | #define PPC_TLB_STORE_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-TLB Miss on store */ |
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543 | #define PPC_IRQ_ADDRBRK (PPC_STD_IRQ_LAST+4) /*0x1300-Instruct addr break */ |
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544 | #define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+5) /*0x1400-System Management */ |
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545 | #define PPC_IRQ_LAST PPC_IRQ_SYS_MGT |
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546 | |
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547 | |
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548 | #elif defined(mpc604) |
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549 | #define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break */ |
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550 | #define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */ |
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551 | #define PPC_IRQ_LAST PPC_IRQ_SYS_MGT |
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552 | |
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553 | #elif defined(mpc860) || defined(mpc821) |
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554 | #define PPC_IRQ_EMULATE (PPC_STD_IRQ_LAST+1) /*0x1000-Software emulation */ |
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555 | #define PPC_IRQ_INST_MISS (PPC_STD_IRQ_LAST+2) /*0x1100-Instruction TLB miss*/ |
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556 | #define PPC_IRQ_DATA_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB miss */ |
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557 | #define PPC_IRQ_INST_ERR (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction TLB err */ |
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558 | #define PPC_IRQ_DATA_ERR (PPC_STD_IRQ_LAST+5) /*0x1400-Data TLB error */ |
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559 | #define PPC_IRQ_DATA_BPNT (PPC_STD_IRQ_LAST+6) /*0x1C00-Data breakpoint */ |
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560 | #define PPC_IRQ_INST_BPNT (PPC_STD_IRQ_LAST+7) /*0x1D00-Inst breakpoint */ |
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561 | #define PPC_IRQ_IO_BPNT (PPC_STD_IRQ_LAST+8) /*0x1E00-Peripheral breakpnt */ |
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562 | #define PPC_IRQ_DEV_PORT (PPC_STD_IRQ_LAST+9) /*0x1F00-Development port */ |
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563 | #define PPC_IRQ_IRQ0 (PPC_STD_IRQ_LAST + 10) |
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564 | #define PPC_IRQ_LVL0 (PPC_STD_IRQ_LAST + 11) |
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565 | #define PPC_IRQ_IRQ1 (PPC_STD_IRQ_LAST + 12) |
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566 | #define PPC_IRQ_LVL1 (PPC_STD_IRQ_LAST + 13) |
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567 | #define PPC_IRQ_IRQ2 (PPC_STD_IRQ_LAST + 14) |
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568 | #define PPC_IRQ_LVL2 (PPC_STD_IRQ_LAST + 15) |
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569 | #define PPC_IRQ_IRQ3 (PPC_STD_IRQ_LAST + 16) |
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570 | #define PPC_IRQ_LVL3 (PPC_STD_IRQ_LAST + 17) |
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571 | #define PPC_IRQ_IRQ4 (PPC_STD_IRQ_LAST + 18) |
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572 | #define PPC_IRQ_LVL4 (PPC_STD_IRQ_LAST + 19) |
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573 | #define PPC_IRQ_IRQ5 (PPC_STD_IRQ_LAST + 20) |
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574 | #define PPC_IRQ_LVL5 (PPC_STD_IRQ_LAST + 21) |
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575 | #define PPC_IRQ_IRQ6 (PPC_STD_IRQ_LAST + 22) |
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576 | #define PPC_IRQ_LVL6 (PPC_STD_IRQ_LAST + 23) |
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577 | #define PPC_IRQ_IRQ7 (PPC_STD_IRQ_LAST + 24) |
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578 | #define PPC_IRQ_LVL7 (PPC_STD_IRQ_LAST + 25) |
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579 | #define PPC_IRQ_CPM_ERROR (PPC_STD_IRQ_LAST + 26) |
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580 | #define PPC_IRQ_CPM_PC4 (PPC_STD_IRQ_LAST + 27) |
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581 | #define PPC_IRQ_CPM_PC5 (PPC_STD_IRQ_LAST + 28) |
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582 | #define PPC_IRQ_CPM_SMC2 (PPC_STD_IRQ_LAST + 29) |
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583 | #define PPC_IRQ_CPM_SMC1 (PPC_STD_IRQ_LAST + 30) |
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584 | #define PPC_IRQ_CPM_SPI (PPC_STD_IRQ_LAST + 31) |
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585 | #define PPC_IRQ_CPM_PC6 (PPC_STD_IRQ_LAST + 32) |
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586 | #define PPC_IRQ_CPM_TIMER4 (PPC_STD_IRQ_LAST + 33) |
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587 | #define PPC_IRQ_CPM_RESERVED_8 (PPC_STD_IRQ_LAST + 34) |
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588 | #define PPC_IRQ_CPM_PC7 (PPC_STD_IRQ_LAST + 35) |
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589 | #define PPC_IRQ_CPM_PC8 (PPC_STD_IRQ_LAST + 36) |
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590 | #define PPC_IRQ_CPM_PC9 (PPC_STD_IRQ_LAST + 37) |
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591 | #define PPC_IRQ_CPM_TIMER3 (PPC_STD_IRQ_LAST + 38) |
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592 | #define PPC_IRQ_CPM_RESERVED_D (PPC_STD_IRQ_LAST + 39) |
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593 | #define PPC_IRQ_CPM_PC10 (PPC_STD_IRQ_LAST + 40) |
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594 | #define PPC_IRQ_CPM_PC11 (PPC_STD_IRQ_LAST + 41) |
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595 | #define PPC_IRQ_CPM_I2C (PPC_STD_IRQ_LAST + 42) |
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596 | #define PPC_IRQ_CPM_RISC_TIMER (PPC_STD_IRQ_LAST + 43) |
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597 | #define PPC_IRQ_CPM_TIMER2 (PPC_STD_IRQ_LAST + 44) |
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598 | #define PPC_IRQ_CPM_RESERVED_13 (PPC_STD_IRQ_LAST + 45) |
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599 | #define PPC_IRQ_CPM_IDMA2 (PPC_STD_IRQ_LAST + 46) |
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600 | #define PPC_IRQ_CPM_IDMA1 (PPC_STD_IRQ_LAST + 47) |
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601 | #define PPC_IRQ_CPM_SDMA_ERROR (PPC_STD_IRQ_LAST + 48) |
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602 | #define PPC_IRQ_CPM_PC12 (PPC_STD_IRQ_LAST + 49) |
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603 | #define PPC_IRQ_CPM_PC13 (PPC_STD_IRQ_LAST + 50) |
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604 | #define PPC_IRQ_CPM_TIMER1 (PPC_STD_IRQ_LAST + 51) |
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605 | #define PPC_IRQ_CPM_PC14 (PPC_STD_IRQ_LAST + 52) |
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606 | #define PPC_IRQ_CPM_SCC4 (PPC_STD_IRQ_LAST + 53) |
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607 | #define PPC_IRQ_CPM_SCC3 (PPC_STD_IRQ_LAST + 54) |
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608 | #define PPC_IRQ_CPM_SCC2 (PPC_STD_IRQ_LAST + 55) |
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609 | #define PPC_IRQ_CPM_SCC1 (PPC_STD_IRQ_LAST + 56) |
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610 | #define PPC_IRQ_CPM_PC15 (PPC_STD_IRQ_LAST + 57) |
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611 | |
---|
612 | #define PPC_IRQ_LAST PPC_IRQ_CPM_PC15 |
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613 | |
---|
614 | #elif defined(mpc8260) |
---|
615 | |
---|
616 | #define PPC_IRQ_INST_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB miss*/ |
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617 | #define PPC_IRQ_DATA_MISS (PPC_STD_IRQ_LAST+2) /*0x1100-Data TLB miss */ |
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618 | #define PPC_IRQ_DATA_L_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB load miss */ |
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619 | #define PPC_IRQ_DATA_S_MISS (PPC_STD_IRQ_LAST+4) /*0x1300-Data TLB store miss */ |
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620 | #define PPC_IRQ_INST_BPNT (PPC_STD_IRQ_LAST+5) /*0x1400-Inst address breakpoint */ |
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621 | #define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+6) /*0x1500-System Management */ |
---|
622 | /* 0x1600 - 0x2F00 reserved */ |
---|
623 | #define PPC_IRQ_CPM_NONE (PPC_STD_IRQ_LAST + 50) |
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624 | #define PPC_IRQ_CPM_I2C (PPC_STD_IRQ_LAST + 51) |
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625 | #define PPC_IRQ_CPM_SPI (PPC_STD_IRQ_LAST + 52) |
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626 | #define PPC_IRQ_CPM_RISC_TIMER (PPC_STD_IRQ_LAST + 53) |
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627 | #define PPC_IRQ_CPM_SMC1 (PPC_STD_IRQ_LAST + 54) |
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628 | #define PPC_IRQ_CPM_SMC2 (PPC_STD_IRQ_LAST + 55) |
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629 | #define PPC_IRQ_CPM_IDMA1 (PPC_STD_IRQ_LAST + 56) |
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630 | #define PPC_IRQ_CPM_IDMA2 (PPC_STD_IRQ_LAST + 57) |
---|
631 | #define PPC_IRQ_CPM_IDMA3 (PPC_STD_IRQ_LAST + 58) |
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632 | #define PPC_IRQ_CPM_IDMA4 (PPC_STD_IRQ_LAST + 59) |
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633 | #define PPC_IRQ_CPM_SDMA (PPC_STD_IRQ_LAST + 60) |
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634 | #define PPC_IRQ_CPM_RES_A (PPC_STD_IRQ_LAST + 61) |
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635 | #define PPC_IRQ_CPM_TIMER1 (PPC_STD_IRQ_LAST + 62) |
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636 | #define PPC_IRQ_CPM_TIMER2 (PPC_STD_IRQ_LAST + 63) |
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637 | #define PPC_IRQ_CPM_TIMER3 (PPC_STD_IRQ_LAST + 64) |
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638 | #define PPC_IRQ_CPM_TIMER4 (PPC_STD_IRQ_LAST + 65) |
---|
639 | #define PPC_IRQ_CPM_TMCNT (PPC_STD_IRQ_LAST + 66) |
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640 | #define PPC_IRQ_CPM_PIT (PPC_STD_IRQ_LAST + 67) |
---|
641 | #define PPC_IRQ_CPM_RES_B (PPC_STD_IRQ_LAST + 68) |
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642 | #define PPC_IRQ_CPM_IRQ1 (PPC_STD_IRQ_LAST + 69) |
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643 | #define PPC_IRQ_CPM_IRQ2 (PPC_STD_IRQ_LAST + 70) |
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644 | #define PPC_IRQ_CPM_IRQ3 (PPC_STD_IRQ_LAST + 71) |
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645 | #define PPC_IRQ_CPM_IRQ4 (PPC_STD_IRQ_LAST + 72) |
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646 | #define PPC_IRQ_CPM_IRQ5 (PPC_STD_IRQ_LAST + 73) |
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647 | #define PPC_IRQ_CPM_IRQ6 (PPC_STD_IRQ_LAST + 74) |
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648 | #define PPC_IRQ_CPM_IRQ7 (PPC_STD_IRQ_LAST + 75) |
---|
649 | #define PPC_IRQ_CPM_RES_C (PPC_STD_IRQ_LAST + 76) |
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650 | #define PPC_IRQ_CPM_RES_D (PPC_STD_IRQ_LAST + 77) |
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651 | #define PPC_IRQ_CPM_RES_E (PPC_STD_IRQ_LAST + 78) |
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652 | #define PPC_IRQ_CPM_RES_F (PPC_STD_IRQ_LAST + 79) |
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653 | #define PPC_IRQ_CPM_RES_G (PPC_STD_IRQ_LAST + 80) |
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654 | #define PPC_IRQ_CPM_RES_H (PPC_STD_IRQ_LAST + 81) |
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655 | #define PPC_IRQ_CPM_FCC1 (PPC_STD_IRQ_LAST + 82) |
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656 | #define PPC_IRQ_CPM_FCC2 (PPC_STD_IRQ_LAST + 83) |
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657 | #define PPC_IRQ_CPM_FCC3 (PPC_STD_IRQ_LAST + 84) |
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658 | #define PPC_IRQ_CPM_RES_I (PPC_STD_IRQ_LAST + 85) |
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659 | #define PPC_IRQ_CPM_MCC1 (PPC_STD_IRQ_LAST + 86) |
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660 | #define PPC_IRQ_CPM_MCC2 (PPC_STD_IRQ_LAST + 87) |
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661 | #define PPC_IRQ_CPM_RES_J (PPC_STD_IRQ_LAST + 88) |
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662 | #define PPC_IRQ_CPM_RES_K (PPC_STD_IRQ_LAST + 89) |
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663 | #define PPC_IRQ_CPM_SCC1 (PPC_STD_IRQ_LAST + 90) |
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664 | #define PPC_IRQ_CPM_SCC2 (PPC_STD_IRQ_LAST + 91) |
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665 | #define PPC_IRQ_CPM_SCC3 (PPC_STD_IRQ_LAST + 92) |
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666 | #define PPC_IRQ_CPM_SCC4 (PPC_STD_IRQ_LAST + 93) |
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667 | #define PPC_IRQ_CPM_RES_L (PPC_STD_IRQ_LAST + 94) |
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668 | #define PPC_IRQ_CPM_RES_M (PPC_STD_IRQ_LAST + 95) |
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669 | #define PPC_IRQ_CPM_RES_N (PPC_STD_IRQ_LAST + 96) |
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670 | #define PPC_IRQ_CPM_RES_O (PPC_STD_IRQ_LAST + 97) |
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671 | #define PPC_IRQ_CPM_PC15 (PPC_STD_IRQ_LAST + 98) |
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672 | #define PPC_IRQ_CPM_PC14 (PPC_STD_IRQ_LAST + 99) |
---|
673 | #define PPC_IRQ_CPM_PC13 (PPC_STD_IRQ_LAST + 100) |
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674 | #define PPC_IRQ_CPM_PC12 (PPC_STD_IRQ_LAST + 101) |
---|
675 | #define PPC_IRQ_CPM_PC11 (PPC_STD_IRQ_LAST + 102) |
---|
676 | #define PPC_IRQ_CPM_PC10 (PPC_STD_IRQ_LAST + 103) |
---|
677 | #define PPC_IRQ_CPM_PC9 (PPC_STD_IRQ_LAST + 104) |
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678 | #define PPC_IRQ_CPM_PC8 (PPC_STD_IRQ_LAST + 105) |
---|
679 | #define PPC_IRQ_CPM_PC7 (PPC_STD_IRQ_LAST + 106) |
---|
680 | #define PPC_IRQ_CPM_PC6 (PPC_STD_IRQ_LAST + 107) |
---|
681 | #define PPC_IRQ_CPM_PC5 (PPC_STD_IRQ_LAST + 108) |
---|
682 | #define PPC_IRQ_CPM_PC4 (PPC_STD_IRQ_LAST + 109) |
---|
683 | #define PPC_IRQ_CPM_PC3 (PPC_STD_IRQ_LAST + 110) |
---|
684 | #define PPC_IRQ_CPM_PC2 (PPC_STD_IRQ_LAST + 111) |
---|
685 | #define PPC_IRQ_CPM_PC1 (PPC_STD_IRQ_LAST + 112) |
---|
686 | #define PPC_IRQ_CPM_PC0 (PPC_STD_IRQ_LAST + 113) |
---|
687 | |
---|
688 | #define PPC_IRQ_LAST PPC_IRQ_CPM_PC0 |
---|
689 | |
---|
690 | #endif |
---|
691 | |
---|
692 | |
---|
693 | /* |
---|
694 | * If the maximum number of exception sources is too low, |
---|
695 | * then fix it |
---|
696 | */ |
---|
697 | |
---|
698 | #if PPC_INTERRUPT_MAX <= PPC_IRQ_LAST |
---|
699 | #undef PPC_INTERRUPT_MAX |
---|
700 | #define PPC_INTERRUPT_MAX ((PPC_IRQ_LAST) + 1) |
---|
701 | #endif |
---|
702 | |
---|
703 | /* |
---|
704 | * Machine Status Register (MSR) Constants Used by RTEMS |
---|
705 | */ |
---|
706 | |
---|
707 | /* |
---|
708 | * Some PPC model manuals refer to the Exception Prefix (EP) bit as |
---|
709 | * IP for no apparent reason. |
---|
710 | */ |
---|
711 | |
---|
712 | #define PPC_MSR_RI 0x000000002 /* bit 30 - recoverable exception */ |
---|
713 | #define PPC_MSR_DR 0x000000010 /* bit 27 - data address translation */ |
---|
714 | #define PPC_MSR_IR 0x000000020 /* bit 26 - instruction addr translation*/ |
---|
715 | |
---|
716 | #if (PPC_HAS_EXCEPTION_PREFIX) |
---|
717 | #define PPC_MSR_EP 0x000000040 /* bit 25 - exception prefix */ |
---|
718 | #else |
---|
719 | #define PPC_MSR_EP 0x000000000 /* bit 25 - exception prefix */ |
---|
720 | #endif |
---|
721 | |
---|
722 | #if (PPC_HAS_FPU) |
---|
723 | #define PPC_MSR_FP 0x000002000 /* bit 18 - floating point enable */ |
---|
724 | #else |
---|
725 | #define PPC_MSR_FP 0x000000000 /* bit 18 - floating point enable */ |
---|
726 | #endif |
---|
727 | |
---|
728 | #if (PPC_LOW_POWER_MODE == PPC_LOW_POWER_MODE_NONE) |
---|
729 | #define PPC_MSR_POW 0x000000000 /* bit 13 - power management enable */ |
---|
730 | #else |
---|
731 | #define PPC_MSR_POW 0x000040000 /* bit 13 - power management enable */ |
---|
732 | #endif |
---|
733 | |
---|
734 | #define PPC_MSR_ME 0x000001000 /* bit 19 - machine check enable */ |
---|
735 | #define PPC_MSR_EE 0x000008000 /* bit 16 - external interrupt enable */ |
---|
736 | |
---|
737 | #if (PPC_HAS_RFCI) |
---|
738 | #define PPC_MSR_CE 0x000020000 /* bit 14 - critical interrupt enable */ |
---|
739 | #else |
---|
740 | #define PPC_MSR_CE 0x000000000 /* bit 14 - critical interrupt enable */ |
---|
741 | #endif |
---|
742 | |
---|
743 | #define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE) |
---|
744 | |
---|
745 | /* |
---|
746 | * Initial value for the FPSCR register |
---|
747 | */ |
---|
748 | |
---|
749 | #define PPC_INIT_FPSCR 0x000000f8 |
---|
750 | |
---|
751 | #ifdef __cplusplus |
---|
752 | } |
---|
753 | #endif |
---|
754 | |
---|
755 | #endif /* _RTEMS_SCORE_POWERPC_H */ |
---|