source: rtems/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h @ 3c6fe2e

4.104.114.9
Last change on this file since 3c6fe2e was 3c6fe2e, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on Jul 14, 2008 at 8:46:06 AM

added haleakala BSP contributed by Michael Hamel

  • Property mode set to 100644
File size: 19.9 KB
Line 
1/**
2 * @file rtems/powerpc/powerpc.h
3 */
4
5/*
6 *  This file contains definitions for the IBM/Motorola PowerPC
7 *  family members.
8 *
9 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
10 *
11 *  COPYRIGHT (c) 1995 by i-cubed ltd.
12 *
13 *  MPC860 support code was added by Jay Monkman <jmonkman@frasca.com>
14 *  MPC8260 support added by Andy Dachs <a.dachs@sstl.co.uk>
15 *  Surrey Satellite Technology Limited
16 *
17 *  To anyone who acknowledges that this file is provided "AS IS"
18 *  without any express or implied warranty:
19 *      permission to use, copy, modify, and distribute this file
20 *      for any purpose is hereby granted without fee, provided that
21 *      the above copyright notice and this notice appears in all
22 *      copies, and that the name of i-cubed limited not be used in
23 *      advertising or publicity pertaining to distribution of the
24 *      software without specific, written prior permission.
25 *      i-cubed limited makes no representations about the suitability
26 *      of this software for any purpose.
27 *
28 *  Derived from c/src/exec/cpu/no_cpu/no_cpu.h:
29 *
30 *  COPYRIGHT (c) 1989-1997.
31 *  On-Line Applications Research Corporation (OAR).
32 *
33 *  The license and distribution terms for this file may in
34 *  the file LICENSE in this distribution or at
35 *  http://www.rtems.com/license/LICENSE.
36 *
37 *
38 * Note:
39 *      This file is included by both C and assembler code ( -DASM )
40 *
41 *  $Id$
42 */
43
44
45#ifndef _RTEMS_POWERPC_POWERPC_H
46#define _RTEMS_POWERPC_POWERPC_H
47
48#ifdef __cplusplus
49extern "C" {
50#endif
51
52
53/* Till S. 2008/07/10:
54 *
55 * Using the macros/definitions which depend on a preprocessor
56 * symbol defining the CPU flavor is discouraged.
57 * I recommend to not use definitions from this file and
58 * in particular - not to add more bits and pieces.
59 *
60 * Instead, try to use run-time detection (see e.g. cpuIdent.c/cpuIdent.h)
61 * of features etc.
62 */
63
64#include <rtems/score/powerpc.h>
65
66/*
67 *  This file contains the information required to build
68 *  RTEMS for a particular member of the PowerPC family.  It does
69 *  this by setting variables to indicate which implementation
70 *  dependent features are present in a particular member
71 *  of the family.
72 *
73 *  The following architectural feature definitions are defaulted
74 *  unless specifically set by the model definition:
75 *
76 *    + PPC_INTERRUPT_MAX        - 16
77 *    + PPC_CACHE_ALIGNMENT      - 32
78 *    + PPC_LOW_POWER_MODE       - PPC_LOW_POWER_MODE_NONE
79 *    + PPC_HAS_EXCEPTION_PREFIX - 1
80 *    + PPC_USE_MULTIPLE         - 0
81 */
82 
83/*
84 *  Define the low power mode models
85 *
86 *  Standard:   as defined for 603e
87 *  Nap Mode:   nap mode only (604)
88 *  XXX 403GB, 603, 603e, 604, 821
89 */
90
91#define PPC_LOW_POWER_MODE_NONE      0
92#define PPC_LOW_POWER_MODE_STANDARD  1
93
94/*
95 *  Figure out all CPU Model Feature Flags based upon compiler
96 *  predefines.
97 */
98
99#if defined(ppc403) || defined(ppc405)
100/*
101 *  IBM 403
102 *
103 *  Developed for 403GA.  Book checked for 403GB.
104 *
105 *  Does not have user mode.
106 */
107 
108#define PPC_CACHE_ALIGNMENT     16
109#define PPC_HAS_RI              0
110#define PPC_HAS_RFCI            1
111#define PPC_USE_MULTIPLE        1
112#define PPC_I_CACHE             2048
113#define PPC_D_CACHE             1024
114
115#define PPC_HAS_EXCEPTION_PREFIX 0
116#define PPC_HAS_EVPR             1
117
118#elif defined (ppc405)
119
120#define PPC_CACHE_ALIGNMENT     32
121#define PPC_HAS_RI           0
122#define PPC_HAS_RFCI            1
123#define PPC_USE_MULTIPLE        1
124#define PPC_I_CACHE             16384
125#define PPC_D_CACHE             16384           /* except GP/CR */
126#define PPC_HAS_EXCEPTION_PREFIX 0
127#define PPC_HAS_EVPR             1
128
129#elif defined(mpc555)
130
131/* Copied from mpc505 */
132#define PPC_CACHE_ALIGNMENT     16
133
134/* Added by querbach@realtime.bc.ca */
135#define PPC_LOW_POWER_MODE      PPC_LOW_POWER_MODE_STANDARD
136
137/* Based on comments by Sergei Organov <osv@Javad.RU> */
138#define PPC_I_CACHE             0
139#define PPC_D_CACHE             0
140
141#elif defined(mpc505) || defined(mpc509)
142/*
143 *  Submitted by Sergei Organov <osv@Javad.RU> as a patch against
144 *  3.6.0 long after 4.0 was released.   This is just an attempt
145 *  to get the setting correct.
146 */
147
148#define PPC_CACHE_ALIGNMENT     16
149#define PPC_I_CACHE             4096
150#define PPC_D_CACHE             0
151
152
153#elif defined(ppc601)
154
155/*
156 *  Submitted with original port -- book checked only.
157 */
158 
159#define PPC_USE_MULTIPLE        1
160#define PPC_I_CACHE             0
161#define PPC_D_CACHE             32768
162
163#elif defined(ppc603)
164/*
165 *  Submitted with original port -- book checked only.
166 */
167 
168#define PPC_I_CACHE             8192
169#define PPC_D_CACHE             8192
170
171#elif defined(ppc603e)
172 
173/*
174 *  Submitted with original port.
175 *
176 *  Known to work on real hardware.
177 */
178
179#define PPC_I_CACHE             16384
180#define PPC_D_CACHE             16384
181
182#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD
183
184#elif defined(mpc604)
185/*
186 *  Submitted with original port -- book checked only.
187 */
188 
189#define PPC_I_CACHE             16384
190#define PPC_D_CACHE             16384
191 
192#elif defined(mpc860)
193/*
194 *  Added by Jay Monkman (jmonkman@frasca.com) 6/28/98
195 *  with some changes by Darlene Stewart (Darlene.Stewart@iit.nrc.ca)
196 */ 
197#define PPC_I_CACHE             4096
198#define PPC_D_CACHE             4096
199#define PPC_CACHE_ALIGNMENT     16
200#define PPC_INTERRUPT_MAX       71
201#define PPC_USE_MULTIPLE        1
202
203#define PPC_MSR_0               0x00009000
204#define PPC_MSR_1               0x00001000
205#define PPC_MSR_2               0x00001000
206#define PPC_MSR_3               0x00000000
207
208#elif defined(mpc821)
209/*
210 *  Added by Andrew Bray <andy@chaos.org.uk> 6/April/1999
211 */ 
212#define PPC_I_CACHE             4096
213#define PPC_D_CACHE             4096
214#define PPC_CACHE_ALIGNMENT     16
215#define PPC_INTERRUPT_MAX       71
216
217#define PPC_MSR_0               0x00009000
218#define PPC_MSR_1               0x00001000
219#define PPC_MSR_2               0x00001000
220#define PPC_MSR_3               0x00000000
221
222#elif defined(mpc750)
223
224#define PPC_I_CACHE             16384
225#define PPC_D_CACHE             16384
226
227#elif defined(mpc7400)
228
229#define PPC_I_CACHE             32768
230#define PPC_D_CACHE             32768
231
232#elif defined(mpc7455)
233/*
234 *  Added by S.K. Feng <feng1@bnl.gov> 10/03
235 */
236
237#define PPC_CACHE_ALIGNMENT     32
238#define PPC_I_CACHE             32768
239#define PPC_D_CACHE             32768
240
241#elif defined(mpc8260)
242/*
243 *  Added by Andy Dachs <a.dachs@sstl.co.uk> 23/11/2000
244 */
245#define PPC_I_CACHE             16384
246#define PPC_D_CACHE             16384
247#define PPC_CACHE_ALIGNMENT     32
248#define PPC_INTERRUPT_MAX       125
249#define PPC_USE_MULTIPLE        1
250
251#elif defined(__ppc_generic)
252#define PPC_CACHE_ALIGNMENT 32
253
254#else
255 
256#error "Unsupported CPU Model"
257 
258#endif
259
260/*
261 *  If the maximum number of exception sources has not been defined,
262 *  then default it to 16.
263 */
264
265#ifndef PPC_INTERRUPT_MAX
266#define PPC_INTERRUPT_MAX       16
267#endif
268
269/*
270 *  Unless specified otherwise, the cache line size is defaulted to 32.
271 *
272 *  The derive the power of 2 the cache line is.
273 */
274
275#ifndef PPC_CACHE_ALIGNMENT
276#define PPC_CACHE_ALIGNMENT 32
277#endif
278
279#if (PPC_CACHE_ALIGNMENT == 16)
280#define PPC_CACHE_ALIGN_POWER 4
281#elif (PPC_CACHE_ALIGNMENT == 32)
282#define PPC_CACHE_ALIGN_POWER 5
283#else
284#error "Undefined power of 2 for PPC_CACHE_ALIGNMENT"
285#endif
286
287/*
288 *  Unless otherwise specified, assume the model has an IP/EP bit to
289 *  set the exception address prefix.
290 */
291
292#ifndef PPC_HAS_EXCEPTION_PREFIX
293#define PPC_HAS_EXCEPTION_PREFIX 1
294#endif
295/*
296 *  Unless otherwise specified, assume the model has an RI bit to
297 *  identify non-recoverable interrupts
298 */
299
300#ifndef PPC_HAS_RI
301#define PPC_HAS_RI 1
302#endif
303
304/*
305 *  Unless otherwise specified, assume the model does NOT have
306 *  403 style EVPR register to set the exception address prefix.
307 */
308
309#ifndef PPC_HAS_EVPR
310#define PPC_HAS_EVPR 0
311#endif
312
313/*
314 *  If no low power mode model was specified, then assume there is none.
315 */
316
317#ifndef PPC_LOW_POWER_MODE
318#define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_NONE
319#endif
320
321/*
322 *  Unless specified above, then assume the model does NOT have critical
323 *  interrupt support.
324 */
325
326#ifndef PPC_HAS_RFCI
327#define PPC_HAS_RFCI 0
328#endif
329
330/*
331 *  Unless specified above, do not use the load/store multiple instructions
332 *  in a context switch.
333 */
334
335#ifndef PPC_USE_MULTIPLE
336#define PPC_USE_MULTIPLE 0
337#endif
338
339/*
340 *  The following exceptions are not maskable, and are not
341 *  necessarily predictable, so cannot be offered to RTEMS:
342 *    Alignment exception - handled by the CPU module
343 *    Data exceptions.
344 *    Instruction exceptions.
345 */
346
347/*
348 *  Base Interrupt vectors supported on all models.
349 */
350#define PPC_IRQ_SYSTEM_RESET     0 /* 0x00100 - System reset.              */
351#define PPC_IRQ_MCHECK           1 /* 0x00200 - Machine check              */
352#define PPC_IRQ_PROTECT          2 /* 0x00300 - Protection violation       */
353#define PPC_IRQ_ISI              3 /* 0x00400 - Instruction Fetch error    */
354#define PPC_IRQ_EXTERNAL         4 /* 0x00500 - External interrupt         */
355#define PPC_IRQ_ALIGNMENT        5 /* 0X00600 - Alignment exception        */
356#define PPC_IRQ_PROGRAM          6 /* 0x00700 - Program exception          */
357#define PPC_IRQ_NOFP             7 /* 0x00800 - Floating point unavailable */
358#define PPC_IRQ_DECREMENTER      8 /* 0x00900 - Decrementer interrupt      */
359#define PPC_IRQ_RESERVED_A       9 /* 0x00a00 - Implementation Reserved    */
360#define PPC_IRQ_RESERVED_B      10 /* 0x00b00 - Implementation Reserved    */
361#define PPC_IRQ_SCALL           11 /* 0x00c00 - System call                */
362#define PPC_IRQ_TRACE           12 /* 0x00d00 - Trace Exception            */
363#define PPC_IRQ_FP_ASST         13 /* ox00e00 - Floating point assist      */
364#define PPC_STD_IRQ_LAST        PPC_IRQ_FP_ASST
365
366#define PPC_IRQ_FIRST           PPC_IRQ_SYSTEM_RESET
367
368#if defined(ppc403) || defined(ppc405)
369                                 
370#define PPC_IRQ_CRIT     PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */
371#define PPC_IRQ_PIT      (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/
372#define PPC_IRQ_FIT      (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer  */
373#define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer    */
374#define PPC_IRQ_DEBUG    (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions  */
375#define PPC_IRQ_LAST     PPC_IRQ_DEBUG
376
377#elif defined(mpc505) || defined(mpc509)
378#define PPC_IRQ_SOFTEMU   (PPC_STD_IRQ_LAST+1)    /* Software emulation. */
379#define PPC_IRQ_DATA_BP   (PPC_STD_IRQ_LAST+ 2)
380#define PPC_IRQ_INST_BP   (PPC_STD_IRQ_LAST+ 3)
381#define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+ 4)
382#define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+ 5)
383
384#elif defined(mpc555)
385#define PPC_IRQ_SOFTEMU   (PPC_STD_IRQ_LAST+1)  /* Software emulation. */
386#define PPC_IRQ_INST_PE   (PPC_STD_IRQ_LAST+2)  /* Insn protection error */
387#define PPC_IRQ_DATA_PE   (PPC_STD_IRQ_LAST+3)  /* Data protection error */
388#define PPC_IRQ_DATA_BP   (PPC_STD_IRQ_LAST+4)  /* Data breakpoint */
389#define PPC_IRQ_INST_BP   (PPC_STD_IRQ_LAST+5)  /* Insn breakpoint */
390#define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+6)  /* Maskable ext bkpt */
391#define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+7)  /* Non-maskable ext bkpt */
392#define PPC_IRQ_LAST      PPC_IRQ_NMEXT_BP
393
394#elif defined(ppc601)
395#define PPC_IRQ_TRACE    (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/
396#define PPC_IRQ_LAST     PPC_IRQ_TRACE       
397
398#elif defined(ppc602)
399#define PPC_IRQ_LAST     (PPC_STD_IRQ_LAST)
400
401#elif defined(ppc603) || defined(ppc603e)
402#define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/
403#define PPC_IRQ_DATA_LOAD  (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/
404#define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss     */
405#define PPC_IRQ_ADDR_BRK   (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */
406#define PPC_IRQ_SYS_MGT    (PPC_STD_IRQ_LAST+5) /*0x1400-System Management   */
407#define PPC_IRQ_LAST       PPC_IRQ_SYS_MGT   
408
409#elif defined(mpc604)
410#define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break  */
411#define PPC_IRQ_SYS_MGT  (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */
412#define PPC_IRQ_LAST     PPC_IRQ_SYS_MGT 
413
414#elif defined(mpc860) || defined(mpc821)
415#define PPC_IRQ_EMULATE         (PPC_STD_IRQ_LAST+1) /*0x1000-Software emulation  */
416#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Instruction TLB miss*/
417#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB miss */
418#define PPC_IRQ_INST_ERR        (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction TLB err */
419#define PPC_IRQ_DATA_ERR        (PPC_STD_IRQ_LAST+5) /*0x1400-Data TLB error */
420#define PPC_IRQ_DATA_BPNT       (PPC_STD_IRQ_LAST+6) /*0x1C00-Data breakpoint */
421#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+7) /*0x1D00-Inst breakpoint */
422#define PPC_IRQ_IO_BPNT         (PPC_STD_IRQ_LAST+8) /*0x1E00-Peripheral breakpnt */
423#define PPC_IRQ_DEV_PORT        (PPC_STD_IRQ_LAST+9) /*0x1F00-Development port */
424#define PPC_IRQ_IRQ0            (PPC_STD_IRQ_LAST + 10)
425#define PPC_IRQ_LVL0            (PPC_STD_IRQ_LAST + 11)
426#define PPC_IRQ_IRQ1            (PPC_STD_IRQ_LAST + 12)
427#define PPC_IRQ_LVL1            (PPC_STD_IRQ_LAST + 13)
428#define PPC_IRQ_IRQ2            (PPC_STD_IRQ_LAST + 14)
429#define PPC_IRQ_LVL2            (PPC_STD_IRQ_LAST + 15)
430#define PPC_IRQ_IRQ3            (PPC_STD_IRQ_LAST + 16)
431#define PPC_IRQ_LVL3            (PPC_STD_IRQ_LAST + 17)
432#define PPC_IRQ_IRQ4            (PPC_STD_IRQ_LAST + 18)
433#define PPC_IRQ_LVL4            (PPC_STD_IRQ_LAST + 19)
434#define PPC_IRQ_IRQ5            (PPC_STD_IRQ_LAST + 20)
435#define PPC_IRQ_LVL5            (PPC_STD_IRQ_LAST + 21)
436#define PPC_IRQ_IRQ6            (PPC_STD_IRQ_LAST + 22)
437#define PPC_IRQ_LVL6            (PPC_STD_IRQ_LAST + 23)
438#define PPC_IRQ_IRQ7            (PPC_STD_IRQ_LAST + 24)
439#define PPC_IRQ_LVL7            (PPC_STD_IRQ_LAST + 25)
440#define PPC_IRQ_CPM_ERROR       (PPC_STD_IRQ_LAST + 26)
441#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 27)
442#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 28)
443#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 29)
444#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 30)
445#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 31)
446#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 32)
447#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 33)
448#define PPC_IRQ_CPM_RESERVED_8  (PPC_STD_IRQ_LAST + 34)
449#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 35)
450#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 36)
451#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 37)
452#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 38)
453#define PPC_IRQ_CPM_RESERVED_D  (PPC_STD_IRQ_LAST + 39)
454#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 40)
455#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 41)
456#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 42)
457#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 43)
458#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 44)
459#define PPC_IRQ_CPM_RESERVED_13 (PPC_STD_IRQ_LAST + 45)
460#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 46)
461#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 47)
462#define PPC_IRQ_CPM_SDMA_ERROR  (PPC_STD_IRQ_LAST + 48)
463#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 49)
464#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 50)
465#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 51)
466#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 52)
467#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 53)
468#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 54)
469#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 55)
470#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 56)
471#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 57)
472
473#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC15
474
475#elif defined(mpc8260)
476
477#define PPC_IRQ_INST_MISS       (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB miss*/
478#define PPC_IRQ_DATA_MISS       (PPC_STD_IRQ_LAST+2) /*0x1100-Data TLB miss */
479#define PPC_IRQ_DATA_L_MISS     (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB load miss */
480#define PPC_IRQ_DATA_S_MISS     (PPC_STD_IRQ_LAST+4) /*0x1300-Data TLB store miss */
481#define PPC_IRQ_INST_BPNT       (PPC_STD_IRQ_LAST+5) /*0x1400-Inst address breakpoint */
482#define PPC_IRQ_SYS_MGT         (PPC_STD_IRQ_LAST+6) /*0x1500-System Management */
483/* 0x1600 - 0x2F00 reserved */
484#define PPC_IRQ_CPM_NONE        (PPC_STD_IRQ_LAST + 50)
485#define PPC_IRQ_CPM_I2C         (PPC_STD_IRQ_LAST + 51)
486#define PPC_IRQ_CPM_SPI         (PPC_STD_IRQ_LAST + 52)
487#define PPC_IRQ_CPM_RISC_TIMER  (PPC_STD_IRQ_LAST + 53)
488#define PPC_IRQ_CPM_SMC1        (PPC_STD_IRQ_LAST + 54)
489#define PPC_IRQ_CPM_SMC2        (PPC_STD_IRQ_LAST + 55)
490#define PPC_IRQ_CPM_IDMA1       (PPC_STD_IRQ_LAST + 56)
491#define PPC_IRQ_CPM_IDMA2       (PPC_STD_IRQ_LAST + 57)
492#define PPC_IRQ_CPM_IDMA3       (PPC_STD_IRQ_LAST + 58)
493#define PPC_IRQ_CPM_IDMA4       (PPC_STD_IRQ_LAST + 59)
494#define PPC_IRQ_CPM_SDMA        (PPC_STD_IRQ_LAST + 60)
495#define PPC_IRQ_CPM_RES_A       (PPC_STD_IRQ_LAST + 61)
496#define PPC_IRQ_CPM_TIMER1      (PPC_STD_IRQ_LAST + 62)
497#define PPC_IRQ_CPM_TIMER2      (PPC_STD_IRQ_LAST + 63)
498#define PPC_IRQ_CPM_TIMER3      (PPC_STD_IRQ_LAST + 64)
499#define PPC_IRQ_CPM_TIMER4      (PPC_STD_IRQ_LAST + 65)
500#define PPC_IRQ_CPM_TMCNT       (PPC_STD_IRQ_LAST + 66)
501#define PPC_IRQ_CPM_PIT         (PPC_STD_IRQ_LAST + 67)
502#define PPC_IRQ_CPM_RES_B       (PPC_STD_IRQ_LAST + 68)
503#define PPC_IRQ_CPM_IRQ1        (PPC_STD_IRQ_LAST + 69)
504#define PPC_IRQ_CPM_IRQ2        (PPC_STD_IRQ_LAST + 70)
505#define PPC_IRQ_CPM_IRQ3        (PPC_STD_IRQ_LAST + 71)
506#define PPC_IRQ_CPM_IRQ4        (PPC_STD_IRQ_LAST + 72)
507#define PPC_IRQ_CPM_IRQ5        (PPC_STD_IRQ_LAST + 73)
508#define PPC_IRQ_CPM_IRQ6        (PPC_STD_IRQ_LAST + 74)
509#define PPC_IRQ_CPM_IRQ7        (PPC_STD_IRQ_LAST + 75)
510#define PPC_IRQ_CPM_RES_C       (PPC_STD_IRQ_LAST + 76)
511#define PPC_IRQ_CPM_RES_D       (PPC_STD_IRQ_LAST + 77)
512#define PPC_IRQ_CPM_RES_E       (PPC_STD_IRQ_LAST + 78)
513#define PPC_IRQ_CPM_RES_F       (PPC_STD_IRQ_LAST + 79)
514#define PPC_IRQ_CPM_RES_G       (PPC_STD_IRQ_LAST + 80)
515#define PPC_IRQ_CPM_RES_H       (PPC_STD_IRQ_LAST + 81)
516#define PPC_IRQ_CPM_FCC1        (PPC_STD_IRQ_LAST + 82)
517#define PPC_IRQ_CPM_FCC2        (PPC_STD_IRQ_LAST + 83)
518#define PPC_IRQ_CPM_FCC3        (PPC_STD_IRQ_LAST + 84)
519#define PPC_IRQ_CPM_RES_I       (PPC_STD_IRQ_LAST + 85)
520#define PPC_IRQ_CPM_MCC1        (PPC_STD_IRQ_LAST + 86)
521#define PPC_IRQ_CPM_MCC2        (PPC_STD_IRQ_LAST + 87)
522#define PPC_IRQ_CPM_RES_J       (PPC_STD_IRQ_LAST + 88)
523#define PPC_IRQ_CPM_RES_K       (PPC_STD_IRQ_LAST + 89)
524#define PPC_IRQ_CPM_SCC1        (PPC_STD_IRQ_LAST + 90)
525#define PPC_IRQ_CPM_SCC2        (PPC_STD_IRQ_LAST + 91)
526#define PPC_IRQ_CPM_SCC3        (PPC_STD_IRQ_LAST + 92)
527#define PPC_IRQ_CPM_SCC4        (PPC_STD_IRQ_LAST + 93)
528#define PPC_IRQ_CPM_RES_L       (PPC_STD_IRQ_LAST + 94)
529#define PPC_IRQ_CPM_RES_M       (PPC_STD_IRQ_LAST + 95)
530#define PPC_IRQ_CPM_RES_N       (PPC_STD_IRQ_LAST + 96)
531#define PPC_IRQ_CPM_RES_O       (PPC_STD_IRQ_LAST + 97)
532#define PPC_IRQ_CPM_PC15        (PPC_STD_IRQ_LAST + 98)
533#define PPC_IRQ_CPM_PC14        (PPC_STD_IRQ_LAST + 99)
534#define PPC_IRQ_CPM_PC13        (PPC_STD_IRQ_LAST + 100)
535#define PPC_IRQ_CPM_PC12        (PPC_STD_IRQ_LAST + 101)
536#define PPC_IRQ_CPM_PC11        (PPC_STD_IRQ_LAST + 102)
537#define PPC_IRQ_CPM_PC10        (PPC_STD_IRQ_LAST + 103)
538#define PPC_IRQ_CPM_PC9         (PPC_STD_IRQ_LAST + 104)
539#define PPC_IRQ_CPM_PC8         (PPC_STD_IRQ_LAST + 105)
540#define PPC_IRQ_CPM_PC7         (PPC_STD_IRQ_LAST + 106)
541#define PPC_IRQ_CPM_PC6         (PPC_STD_IRQ_LAST + 107)
542#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 108)
543#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 109)
544#define PPC_IRQ_CPM_PC3         (PPC_STD_IRQ_LAST + 110)
545#define PPC_IRQ_CPM_PC2         (PPC_STD_IRQ_LAST + 111)
546#define PPC_IRQ_CPM_PC1         (PPC_STD_IRQ_LAST + 112)
547#define PPC_IRQ_CPM_PC0         (PPC_STD_IRQ_LAST + 113)
548
549#define PPC_IRQ_LAST             PPC_IRQ_CPM_PC0
550
551#endif
552
553
554/*
555 *  If the maximum number of exception sources is too low,
556 *  then fix it
557 */
558
559#if PPC_INTERRUPT_MAX <= PPC_IRQ_LAST
560#undef PPC_INTERRUPT_MAX
561#define PPC_INTERRUPT_MAX ((PPC_IRQ_LAST) + 1)
562#endif
563
564/*
565 *  Machine Status Register (MSR) Constants Used by RTEMS
566 */
567
568#if PPC_HAS_RI
569#define PPC_MSR_RI       0x000000002 /* bit 30 - recoverable exception */
570#endif
571
572#define PPC_MSR_DR       0x000000010 /* bit 27 - data address translation */
573#define PPC_MSR_IR       0x000000020 /* bit 26 - instruction addr translation*/
574
575/*
576 *  Some PPC model manuals refer to the Exception Prefix (EP) bit as
577 *  IP for no apparent reason.
578 */
579#if (PPC_HAS_EXCEPTION_PREFIX)
580#define PPC_MSR_EP       0x000000040 /* bit 25 - exception prefix */
581#else
582#define PPC_MSR_EP       0x000000000 /* bit 25 - exception prefix */
583#endif
584
585#if (PPC_HAS_FPU)
586#define PPC_MSR_FP       0x000002000 /* bit 18 - floating point enable */
587#else
588#define PPC_MSR_FP       0x000000000 /* bit 18 - floating point enable */
589#endif
590
591#if (PPC_LOW_POWER_MODE == PPC_LOW_POWER_MODE_NONE)
592#define PPC_MSR_POW      0x000000000 /* bit 13 - power management enable */
593#else
594#define PPC_MSR_POW      0x000040000 /* bit 13 - power management enable */
595#endif
596
597#define PPC_MSR_ME       0x000001000 /* bit 19 - machine check enable */
598#define PPC_MSR_EE       0x000008000 /* bit 16 - external interrupt enable */
599
600#if (PPC_HAS_RFCI)
601#define PPC_MSR_CE       0x000020000 /* bit 14 - critical interrupt enable */
602#else
603#define PPC_MSR_CE       0x000000000 /* bit 14 - critical interrupt enable */
604#endif
605
606#define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE)
607
608#define PPC_MINIMUM_STACK_FRAME_SIZE PPC_STACK_ALIGNMENT
609
610#ifdef __cplusplus
611}
612#endif
613
614#endif /* _RTEMS_POWERPC_POWERPC_H */
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