| 1 | /** |
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| 2 | * @file rtems/powerpc/powerpc.h |
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| 3 | */ |
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| 4 | |
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| 5 | /* |
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| 6 | * This file contains definitions for the IBM/Motorola PowerPC |
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| 7 | * family members. |
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| 8 | * |
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| 9 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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| 10 | * |
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| 11 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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| 12 | * |
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| 13 | * MPC860 support code was added by Jay Monkman <jmonkman@frasca.com> |
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| 14 | * MPC8260 support added by Andy Dachs <a.dachs@sstl.co.uk> |
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| 15 | * Surrey Satellite Technology Limited |
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| 16 | * |
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| 17 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 18 | * without any express or implied warranty: |
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| 19 | * permission to use, copy, modify, and distribute this file |
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| 20 | * for any purpose is hereby granted without fee, provided that |
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| 21 | * the above copyright notice and this notice appears in all |
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| 22 | * copies, and that the name of i-cubed limited not be used in |
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| 23 | * advertising or publicity pertaining to distribution of the |
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| 24 | * software without specific, written prior permission. |
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| 25 | * i-cubed limited makes no representations about the suitability |
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| 26 | * of this software for any purpose. |
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| 27 | * |
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| 28 | * Derived from c/src/exec/cpu/no_cpu/no_cpu.h: |
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| 29 | * |
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| 30 | * COPYRIGHT (c) 1989-1997. |
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| 31 | * On-Line Applications Research Corporation (OAR). |
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| 32 | * |
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| 33 | * The license and distribution terms for this file may in |
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| 34 | * the file LICENSE in this distribution or at |
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| 35 | * http://www.rtems.org/license/LICENSE. |
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| 36 | * |
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| 37 | * |
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| 38 | * Note: |
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| 39 | * This file is included by both C and assembler code ( -DASM ) |
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| 40 | */ |
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| 41 | |
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| 42 | |
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| 43 | #ifndef _RTEMS_POWERPC_POWERPC_H |
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| 44 | #define _RTEMS_POWERPC_POWERPC_H |
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| 45 | |
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| 46 | #ifdef __cplusplus |
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| 47 | extern "C" { |
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| 48 | #endif |
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| 49 | |
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| 50 | |
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| 51 | /* Till S. 2008/07/10: |
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| 52 | * |
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| 53 | * Using the macros/definitions which depend on a preprocessor |
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| 54 | * symbol defining the CPU flavor is discouraged. |
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| 55 | * I recommend to not use definitions from this file and |
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| 56 | * in particular - not to add more bits and pieces. |
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| 57 | * |
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| 58 | * Instead, try to use run-time detection (see e.g. cpuIdent.c/cpuIdent.h) |
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| 59 | * of features etc. |
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| 60 | */ |
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| 61 | |
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| 62 | #include <rtems/score/powerpc.h> |
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| 63 | |
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| 64 | /* |
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| 65 | * This file contains the information required to build |
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| 66 | * RTEMS for a particular member of the PowerPC family. It does |
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| 67 | * this by setting variables to indicate which implementation |
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| 68 | * dependent features are present in a particular member |
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| 69 | * of the family. |
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| 70 | * |
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| 71 | * The following architectural feature definitions are defaulted |
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| 72 | * unless specifically set by the model definition: |
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| 73 | * |
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| 74 | * + PPC_INTERRUPT_MAX - 16 |
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| 75 | * + PPC_CACHE_ALIGNMENT - 32 |
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| 76 | * + PPC_LOW_POWER_MODE - PPC_LOW_POWER_MODE_NONE |
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| 77 | * + PPC_HAS_EXCEPTION_PREFIX - 1 |
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| 78 | * + PPC_USE_MULTIPLE - 0 |
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| 79 | */ |
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| 80 | |
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| 81 | /* |
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| 82 | * Define the low power mode models |
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| 83 | * |
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| 84 | * Standard: as defined for 603e |
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| 85 | * Nap Mode: nap mode only (604) |
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| 86 | * XXX 403GB, 603, 603e, 604, 821 |
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| 87 | */ |
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| 88 | |
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| 89 | #define PPC_LOW_POWER_MODE_NONE 0 |
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| 90 | #define PPC_LOW_POWER_MODE_STANDARD 1 |
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| 91 | |
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| 92 | /** |
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| 93 | * @brief For boards with no cache set PPC_CACHE_ALIGNMENT to this value. |
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| 94 | */ |
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| 95 | #define PPC_NO_CACHE_ALIGNMENT 4 |
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| 96 | |
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| 97 | /** |
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| 98 | * @brief Used to define PPC_CACHE_ALIGN_POWER for boards with no cache (and |
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| 99 | * PPC_NO_CACHE_ALIGNMENT defined). |
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| 100 | */ |
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| 101 | #define PPC_NO_CACHE_ALIGNMENT_POWER 2 |
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| 102 | |
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| 103 | /* |
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| 104 | * Figure out all CPU Model Feature Flags based upon compiler |
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| 105 | * predefines. |
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| 106 | */ |
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| 107 | |
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| 108 | #if defined(ppc403) |
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| 109 | /* |
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| 110 | * IBM 403 |
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| 111 | * |
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| 112 | * Developed for 403GA. Book checked for 403GB. |
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| 113 | * |
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| 114 | * Does not have user mode. |
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| 115 | */ |
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| 116 | |
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| 117 | #define PPC_CACHE_ALIGNMENT 16 |
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| 118 | #define PPC_HAS_RI 0 |
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| 119 | #define PPC_HAS_RFCI 1 |
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| 120 | #define PPC_USE_MULTIPLE 1 |
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| 121 | #define PPC_I_CACHE 2048 |
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| 122 | #define PPC_D_CACHE 1024 |
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| 123 | |
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| 124 | #define PPC_HAS_EXCEPTION_PREFIX 0 |
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| 125 | #define PPC_HAS_EVPR 1 |
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| 126 | |
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| 127 | #elif defined (ppc405) |
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| 128 | |
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| 129 | #define PPC_CACHE_ALIGNMENT 32 |
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| 130 | #define PPC_HAS_RI 0 |
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| 131 | #define PPC_HAS_RFCI 1 |
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| 132 | #define PPC_USE_MULTIPLE 1 |
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| 133 | #define PPC_I_CACHE 16384 |
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| 134 | #define PPC_D_CACHE 16384 /* except GP/CR */ |
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| 135 | #define PPC_HAS_EXCEPTION_PREFIX 0 |
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| 136 | #define PPC_HAS_EVPR 1 |
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| 137 | |
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| 138 | #elif defined (ppc440) |
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| 139 | |
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| 140 | #define PPC_CACHE_ALIGNMENT 32 |
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| 141 | #define PPC_HAS_RI 0 |
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| 142 | #define PPC_HAS_RFCI 1 |
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| 143 | #define PPC_USE_MULTIPLE 1 |
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| 144 | #define PPC_I_CACHE 32768 |
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| 145 | #define PPC_D_CACHE 32768 |
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| 146 | #define PPC_HAS_EXCEPTION_PREFIX 0 |
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| 147 | #define PPC_HAS_EVPR 1 |
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| 148 | |
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| 149 | #elif defined(mpc555) |
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| 150 | |
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| 151 | /* Copied from mpc505 */ |
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| 152 | #define PPC_CACHE_ALIGNMENT PPC_NO_CACHE_ALIGNMENT |
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| 153 | |
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| 154 | /* Added by querbach@realtime.bc.ca */ |
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| 155 | #define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD |
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| 156 | |
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| 157 | /* Based on comments by Sergei Organov <osv@Javad.RU> */ |
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| 158 | #define PPC_I_CACHE 0 |
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| 159 | #define PPC_D_CACHE 0 |
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| 160 | |
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| 161 | #elif defined(mpc505) || defined(mpc509) |
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| 162 | /* |
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| 163 | * Submitted by Sergei Organov <osv@Javad.RU> as a patch against |
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| 164 | * 3.6.0 long after 4.0 was released. This is just an attempt |
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| 165 | * to get the setting correct. |
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| 166 | */ |
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| 167 | |
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| 168 | #define CPU_MODEL_NAME "PowerPC 505/509" |
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| 169 | |
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| 170 | #define PPC_CACHE_ALIGNMENT PPC_NO_CACHE_ALIGNMENT |
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| 171 | #define PPC_I_CACHE 4096 |
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| 172 | #define PPC_D_CACHE 0 |
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| 173 | |
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| 174 | |
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| 175 | #elif defined(ppc601) |
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| 176 | |
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| 177 | /* |
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| 178 | * Submitted with original port -- book checked only. |
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| 179 | */ |
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| 180 | |
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| 181 | #define PPC_USE_MULTIPLE 1 |
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| 182 | #define PPC_I_CACHE 0 |
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| 183 | #define PPC_D_CACHE 32768 |
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| 184 | |
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| 185 | #elif defined(ppc603) |
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| 186 | /* |
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| 187 | * Submitted with original port -- book checked only. |
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| 188 | */ |
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| 189 | |
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| 190 | #define PPC_I_CACHE 8192 |
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| 191 | #define PPC_D_CACHE 8192 |
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| 192 | |
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| 193 | #elif defined(ppc603e) |
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| 194 | |
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| 195 | /* |
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| 196 | * Submitted with original port. |
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| 197 | * |
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| 198 | * Known to work on real hardware. |
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| 199 | */ |
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| 200 | |
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| 201 | #define PPC_I_CACHE 16384 |
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| 202 | #define PPC_D_CACHE 16384 |
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| 203 | |
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| 204 | #define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD |
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| 205 | |
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| 206 | #elif defined(mpc604) |
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| 207 | /* |
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| 208 | * Submitted with original port -- book checked only. |
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| 209 | */ |
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| 210 | |
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| 211 | #define PPC_I_CACHE 16384 |
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| 212 | #define PPC_D_CACHE 16384 |
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| 213 | |
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| 214 | #elif defined(mpc860) |
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| 215 | /* |
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| 216 | * Added by Jay Monkman (jmonkman@frasca.com) 6/28/98 |
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| 217 | * with some changes by Darlene Stewart (Darlene.Stewart@iit.nrc.ca) |
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| 218 | */ |
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| 219 | #define PPC_I_CACHE 4096 |
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| 220 | #define PPC_D_CACHE 4096 |
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| 221 | #define PPC_CACHE_ALIGNMENT 16 |
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| 222 | #define PPC_INTERRUPT_MAX 71 |
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| 223 | #define PPC_USE_MULTIPLE 1 |
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| 224 | |
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| 225 | #define PPC_MSR_0 0x00009000 |
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| 226 | #define PPC_MSR_1 0x00001000 |
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| 227 | #define PPC_MSR_2 0x00001000 |
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| 228 | #define PPC_MSR_3 0x00000000 |
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| 229 | |
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| 230 | #elif defined(mpc821) |
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| 231 | /* |
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| 232 | * Added by Andrew Bray <andy@chaos.org.uk> 6/April/1999 |
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| 233 | */ |
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| 234 | #define PPC_I_CACHE 4096 |
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| 235 | #define PPC_D_CACHE 4096 |
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| 236 | #define PPC_CACHE_ALIGNMENT 16 |
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| 237 | #define PPC_INTERRUPT_MAX 71 |
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| 238 | |
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| 239 | #define PPC_MSR_0 0x00009000 |
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| 240 | #define PPC_MSR_1 0x00001000 |
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| 241 | #define PPC_MSR_2 0x00001000 |
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| 242 | #define PPC_MSR_3 0x00000000 |
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| 243 | |
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| 244 | #elif defined(mpc750) |
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| 245 | |
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| 246 | #define PPC_I_CACHE 16384 |
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| 247 | #define PPC_D_CACHE 16384 |
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| 248 | |
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| 249 | #elif defined(mpc7400) |
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| 250 | |
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| 251 | #define PPC_I_CACHE 32768 |
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| 252 | #define PPC_D_CACHE 32768 |
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| 253 | |
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| 254 | #elif defined(mpc7455) |
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| 255 | /* |
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| 256 | * Added by S.K. Feng <feng1@bnl.gov> 10/03 |
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| 257 | */ |
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| 258 | |
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| 259 | #define PPC_CACHE_ALIGNMENT 32 |
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| 260 | #define PPC_I_CACHE 32768 |
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| 261 | #define PPC_D_CACHE 32768 |
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| 262 | |
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| 263 | #elif defined(mpc8260) |
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| 264 | /* |
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| 265 | * Added by Andy Dachs <a.dachs@sstl.co.uk> 23/11/2000 |
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| 266 | */ |
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| 267 | #define PPC_I_CACHE 16384 |
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| 268 | #define PPC_D_CACHE 16384 |
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| 269 | #define PPC_CACHE_ALIGNMENT 32 |
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| 270 | #define PPC_INTERRUPT_MAX 125 |
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| 271 | #define PPC_USE_MULTIPLE 1 |
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| 272 | |
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| 273 | #elif defined(__ppc_generic) |
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| 274 | #define PPC_CACHE_ALIGNMENT 32 |
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| 275 | |
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| 276 | #else |
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| 277 | |
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| 278 | #error "Unsupported CPU Model" |
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| 279 | |
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| 280 | #endif |
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| 281 | |
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| 282 | /* |
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| 283 | * If the maximum number of exception sources has not been defined, |
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| 284 | * then default it to 16. |
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| 285 | */ |
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| 286 | |
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| 287 | #ifndef PPC_INTERRUPT_MAX |
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| 288 | #define PPC_INTERRUPT_MAX 16 |
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| 289 | #endif |
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| 290 | |
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| 291 | /* |
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| 292 | * Unless specified otherwise, the cache line size is defaulted to 32. |
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| 293 | * |
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| 294 | * The derive the power of 2 the cache line is. |
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| 295 | */ |
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| 296 | |
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| 297 | #ifndef PPC_CACHE_ALIGNMENT |
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| 298 | #define PPC_CACHE_ALIGNMENT 32 |
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| 299 | #endif |
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| 300 | |
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| 301 | #if (PPC_CACHE_ALIGNMENT == 16) |
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| 302 | #define PPC_CACHE_ALIGN_POWER 4 |
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| 303 | #elif (PPC_CACHE_ALIGNMENT == 32) |
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| 304 | #define PPC_CACHE_ALIGN_POWER 5 |
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| 305 | #elif (PPC_CACHE_ALIGNMENT == PPC_NO_CACHE_ALIGNMENT) |
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| 306 | #define PPC_CACHE_ALIGN_POWER PPC_NO_CACHE_ALIGNMENT_POWER |
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| 307 | #else |
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| 308 | #error "Undefined power of 2 for PPC_CACHE_ALIGNMENT" |
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| 309 | #endif |
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| 310 | |
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| 311 | /* |
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| 312 | * Unless otherwise specified, assume the model has an IP/EP bit to |
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| 313 | * set the exception address prefix. |
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| 314 | */ |
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| 315 | |
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| 316 | #ifndef PPC_HAS_EXCEPTION_PREFIX |
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| 317 | #define PPC_HAS_EXCEPTION_PREFIX 1 |
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| 318 | #endif |
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| 319 | /* |
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| 320 | * Unless otherwise specified, assume the model has an RI bit to |
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| 321 | * identify non-recoverable interrupts |
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| 322 | */ |
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| 323 | |
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| 324 | #ifndef PPC_HAS_RI |
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| 325 | #define PPC_HAS_RI 1 |
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| 326 | #endif |
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| 327 | |
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| 328 | /* |
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| 329 | * Unless otherwise specified, assume the model does NOT have |
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| 330 | * 403 style EVPR register to set the exception address prefix. |
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| 331 | */ |
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| 332 | |
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| 333 | #ifndef PPC_HAS_EVPR |
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| 334 | #define PPC_HAS_EVPR 0 |
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| 335 | #endif |
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| 336 | |
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| 337 | /* |
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| 338 | * If no low power mode model was specified, then assume there is none. |
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| 339 | */ |
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| 340 | |
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| 341 | #ifndef PPC_LOW_POWER_MODE |
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| 342 | #define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_NONE |
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| 343 | #endif |
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| 344 | |
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| 345 | /* |
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| 346 | * Unless specified above, then assume the model does NOT have critical |
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| 347 | * interrupt support. |
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| 348 | */ |
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| 349 | |
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| 350 | #ifndef PPC_HAS_RFCI |
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| 351 | #define PPC_HAS_RFCI 0 |
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| 352 | #endif |
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| 353 | |
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| 354 | /* |
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| 355 | * Unless specified above, do not use the load/store multiple instructions |
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| 356 | * in a context switch. |
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| 357 | */ |
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| 358 | |
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| 359 | #ifndef PPC_USE_MULTIPLE |
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| 360 | #define PPC_USE_MULTIPLE 0 |
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| 361 | #endif |
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| 362 | |
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| 363 | /* |
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| 364 | * The following exceptions are not maskable, and are not |
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| 365 | * necessarily predictable, so cannot be offered to RTEMS: |
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| 366 | * Alignment exception - handled by the CPU module |
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| 367 | * Data exceptions. |
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| 368 | * Instruction exceptions. |
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| 369 | */ |
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| 370 | |
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| 371 | /* |
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| 372 | * Base Interrupt vectors supported on all models. |
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| 373 | */ |
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| 374 | #define PPC_IRQ_SYSTEM_RESET 0 /* 0x00100 - System reset. */ |
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| 375 | #define PPC_IRQ_MCHECK 1 /* 0x00200 - Machine check */ |
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| 376 | #define PPC_IRQ_PROTECT 2 /* 0x00300 - Protection violation */ |
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| 377 | #define PPC_IRQ_ISI 3 /* 0x00400 - Instruction Fetch error */ |
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| 378 | #define PPC_IRQ_EXTERNAL 4 /* 0x00500 - External interrupt */ |
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| 379 | #define PPC_IRQ_ALIGNMENT 5 /* 0X00600 - Alignment exception */ |
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| 380 | #define PPC_IRQ_PROGRAM 6 /* 0x00700 - Program exception */ |
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| 381 | #define PPC_IRQ_NOFP 7 /* 0x00800 - Floating point unavailable */ |
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| 382 | #define PPC_IRQ_DECREMENTER 8 /* 0x00900 - Decrementer interrupt */ |
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| 383 | #define PPC_IRQ_RESERVED_A 9 /* 0x00a00 - Implementation Reserved */ |
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| 384 | #define PPC_IRQ_RESERVED_B 10 /* 0x00b00 - Implementation Reserved */ |
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| 385 | #define PPC_IRQ_SCALL 11 /* 0x00c00 - System call */ |
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| 386 | #define PPC_IRQ_TRACE 12 /* 0x00d00 - Trace Exception */ |
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| 387 | #define PPC_IRQ_FP_ASST 13 /* ox00e00 - Floating point assist */ |
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| 388 | #define PPC_STD_IRQ_LAST PPC_IRQ_FP_ASST |
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| 389 | |
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| 390 | #define PPC_IRQ_FIRST PPC_IRQ_SYSTEM_RESET |
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| 391 | |
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| 392 | #if defined(ppc403) || defined(ppc405) || defined(ppc440) |
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| 393 | |
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| 394 | #define PPC_IRQ_CRIT PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */ |
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| 395 | #define PPC_IRQ_PIT (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/ |
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| 396 | #define PPC_IRQ_FIT (PPC_STD_IRQ_LAST+2) /*0x01010- Fixed int. timer */ |
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| 397 | #define PPC_IRQ_WATCHDOG (PPC_STD_IRQ_LAST+3) /*0x01020- Watchdog timer */ |
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| 398 | #define PPC_IRQ_DEBUG (PPC_STD_IRQ_LAST+4) /*0x02000- Debug exceptions */ |
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| 399 | #define PPC_IRQ_LAST PPC_IRQ_DEBUG |
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| 400 | |
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| 401 | #elif defined(mpc505) || defined(mpc509) |
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| 402 | #define PPC_IRQ_SOFTEMU (PPC_STD_IRQ_LAST+1) /* Software emulation. */ |
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| 403 | #define PPC_IRQ_DATA_BP (PPC_STD_IRQ_LAST+ 2) |
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| 404 | #define PPC_IRQ_INST_BP (PPC_STD_IRQ_LAST+ 3) |
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| 405 | #define PPC_IRQ_MEXT_BP (PPC_STD_IRQ_LAST+ 4) |
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| 406 | #define PPC_IRQ_NMEXT_BP (PPC_STD_IRQ_LAST+ 5) |
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| 407 | |
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| 408 | #elif defined(mpc555) |
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| 409 | #define PPC_IRQ_SOFTEMU (PPC_STD_IRQ_LAST+1) /* Software emulation. */ |
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| 410 | #define PPC_IRQ_INST_PE (PPC_STD_IRQ_LAST+2) /* Insn protection error */ |
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| 411 | #define PPC_IRQ_DATA_PE (PPC_STD_IRQ_LAST+3) /* Data protection error */ |
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| 412 | #define PPC_IRQ_DATA_BP (PPC_STD_IRQ_LAST+4) /* Data breakpoint */ |
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| 413 | #define PPC_IRQ_INST_BP (PPC_STD_IRQ_LAST+5) /* Insn breakpoint */ |
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| 414 | #define PPC_IRQ_MEXT_BP (PPC_STD_IRQ_LAST+6) /* Maskable ext bkpt */ |
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| 415 | #define PPC_IRQ_NMEXT_BP (PPC_STD_IRQ_LAST+7) /* Non-maskable ext bkpt */ |
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| 416 | #define PPC_IRQ_LAST PPC_IRQ_NMEXT_BP |
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| 417 | |
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| 418 | #elif defined(ppc601) |
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| 419 | #undef PPC_IRQ_TRACE |
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| 420 | #define PPC_IRQ_TRACE (PPC_STD_IRQ_LAST+1) /*0x02000-Run/Trace Exception*/ |
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| 421 | #define PPC_IRQ_LAST PPC_IRQ_TRACE |
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| 422 | |
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| 423 | #elif defined(ppc602) |
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| 424 | #define PPC_IRQ_LAST (PPC_STD_IRQ_LAST) |
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| 425 | |
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| 426 | #elif defined(ppc603) || defined(ppc603e) |
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| 427 | #define PPC_IRQ_TRANS_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Ins Translation Miss*/ |
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| 428 | #define PPC_IRQ_DATA_LOAD (PPC_STD_IRQ_LAST+2) /*0x1100-Data Load Trans Miss*/ |
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| 429 | #define PPC_IRQ_DATA_STORE (PPC_STD_IRQ_LAST+3) /*0x1200-Data Store Miss */ |
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| 430 | #define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction Bkpoint */ |
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| 431 | #define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+5) /*0x1400-System Management */ |
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| 432 | #define PPC_IRQ_LAST PPC_IRQ_SYS_MGT |
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| 433 | |
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| 434 | #elif defined(mpc604) |
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| 435 | #define PPC_IRQ_ADDR_BRK (PPC_STD_IRQ_LAST+1) /*0x1300- Inst. addr break */ |
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| 436 | #define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+2) /*0x1400- System Management */ |
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| 437 | #define PPC_IRQ_LAST PPC_IRQ_SYS_MGT |
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| 438 | |
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| 439 | #elif defined(mpc860) || defined(mpc821) |
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| 440 | #define PPC_IRQ_EMULATE (PPC_STD_IRQ_LAST+1) /*0x1000-Software emulation */ |
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| 441 | #define PPC_IRQ_INST_MISS (PPC_STD_IRQ_LAST+2) /*0x1100-Instruction TLB miss*/ |
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| 442 | #define PPC_IRQ_DATA_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB miss */ |
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| 443 | #define PPC_IRQ_INST_ERR (PPC_STD_IRQ_LAST+4) /*0x1300-Instruction TLB err */ |
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| 444 | #define PPC_IRQ_DATA_ERR (PPC_STD_IRQ_LAST+5) /*0x1400-Data TLB error */ |
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| 445 | #define PPC_IRQ_DATA_BPNT (PPC_STD_IRQ_LAST+6) /*0x1C00-Data breakpoint */ |
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| 446 | #define PPC_IRQ_INST_BPNT (PPC_STD_IRQ_LAST+7) /*0x1D00-Inst breakpoint */ |
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| 447 | #define PPC_IRQ_IO_BPNT (PPC_STD_IRQ_LAST+8) /*0x1E00-Peripheral breakpnt */ |
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| 448 | #define PPC_IRQ_DEV_PORT (PPC_STD_IRQ_LAST+9) /*0x1F00-Development port */ |
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| 449 | #define PPC_IRQ_IRQ0 (PPC_STD_IRQ_LAST + 10) |
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| 450 | #define PPC_IRQ_LVL0 (PPC_STD_IRQ_LAST + 11) |
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| 451 | #define PPC_IRQ_IRQ1 (PPC_STD_IRQ_LAST + 12) |
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| 452 | #define PPC_IRQ_LVL1 (PPC_STD_IRQ_LAST + 13) |
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| 453 | #define PPC_IRQ_IRQ2 (PPC_STD_IRQ_LAST + 14) |
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| 454 | #define PPC_IRQ_LVL2 (PPC_STD_IRQ_LAST + 15) |
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| 455 | #define PPC_IRQ_IRQ3 (PPC_STD_IRQ_LAST + 16) |
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| 456 | #define PPC_IRQ_LVL3 (PPC_STD_IRQ_LAST + 17) |
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| 457 | #define PPC_IRQ_IRQ4 (PPC_STD_IRQ_LAST + 18) |
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| 458 | #define PPC_IRQ_LVL4 (PPC_STD_IRQ_LAST + 19) |
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| 459 | #define PPC_IRQ_IRQ5 (PPC_STD_IRQ_LAST + 20) |
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| 460 | #define PPC_IRQ_LVL5 (PPC_STD_IRQ_LAST + 21) |
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| 461 | #define PPC_IRQ_IRQ6 (PPC_STD_IRQ_LAST + 22) |
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| 462 | #define PPC_IRQ_LVL6 (PPC_STD_IRQ_LAST + 23) |
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| 463 | #define PPC_IRQ_IRQ7 (PPC_STD_IRQ_LAST + 24) |
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| 464 | #define PPC_IRQ_LVL7 (PPC_STD_IRQ_LAST + 25) |
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| 465 | #define PPC_IRQ_CPM_ERROR (PPC_STD_IRQ_LAST + 26) |
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| 466 | #define PPC_IRQ_CPM_PC4 (PPC_STD_IRQ_LAST + 27) |
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| 467 | #define PPC_IRQ_CPM_PC5 (PPC_STD_IRQ_LAST + 28) |
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| 468 | #define PPC_IRQ_CPM_SMC2 (PPC_STD_IRQ_LAST + 29) |
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| 469 | #define PPC_IRQ_CPM_SMC1 (PPC_STD_IRQ_LAST + 30) |
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| 470 | #define PPC_IRQ_CPM_SPI (PPC_STD_IRQ_LAST + 31) |
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| 471 | #define PPC_IRQ_CPM_PC6 (PPC_STD_IRQ_LAST + 32) |
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| 472 | #define PPC_IRQ_CPM_TIMER4 (PPC_STD_IRQ_LAST + 33) |
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| 473 | #define PPC_IRQ_CPM_RESERVED_8 (PPC_STD_IRQ_LAST + 34) |
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| 474 | #define PPC_IRQ_CPM_PC7 (PPC_STD_IRQ_LAST + 35) |
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| 475 | #define PPC_IRQ_CPM_PC8 (PPC_STD_IRQ_LAST + 36) |
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| 476 | #define PPC_IRQ_CPM_PC9 (PPC_STD_IRQ_LAST + 37) |
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| 477 | #define PPC_IRQ_CPM_TIMER3 (PPC_STD_IRQ_LAST + 38) |
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| 478 | #define PPC_IRQ_CPM_RESERVED_D (PPC_STD_IRQ_LAST + 39) |
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| 479 | #define PPC_IRQ_CPM_PC10 (PPC_STD_IRQ_LAST + 40) |
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| 480 | #define PPC_IRQ_CPM_PC11 (PPC_STD_IRQ_LAST + 41) |
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| 481 | #define PPC_IRQ_CPM_I2C (PPC_STD_IRQ_LAST + 42) |
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| 482 | #define PPC_IRQ_CPM_RISC_TIMER (PPC_STD_IRQ_LAST + 43) |
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| 483 | #define PPC_IRQ_CPM_TIMER2 (PPC_STD_IRQ_LAST + 44) |
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| 484 | #define PPC_IRQ_CPM_RESERVED_13 (PPC_STD_IRQ_LAST + 45) |
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| 485 | #define PPC_IRQ_CPM_IDMA2 (PPC_STD_IRQ_LAST + 46) |
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| 486 | #define PPC_IRQ_CPM_IDMA1 (PPC_STD_IRQ_LAST + 47) |
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| 487 | #define PPC_IRQ_CPM_SDMA_ERROR (PPC_STD_IRQ_LAST + 48) |
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| 488 | #define PPC_IRQ_CPM_PC12 (PPC_STD_IRQ_LAST + 49) |
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| 489 | #define PPC_IRQ_CPM_PC13 (PPC_STD_IRQ_LAST + 50) |
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| 490 | #define PPC_IRQ_CPM_TIMER1 (PPC_STD_IRQ_LAST + 51) |
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| 491 | #define PPC_IRQ_CPM_PC14 (PPC_STD_IRQ_LAST + 52) |
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| 492 | #define PPC_IRQ_CPM_SCC4 (PPC_STD_IRQ_LAST + 53) |
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| 493 | #define PPC_IRQ_CPM_SCC3 (PPC_STD_IRQ_LAST + 54) |
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| 494 | #define PPC_IRQ_CPM_SCC2 (PPC_STD_IRQ_LAST + 55) |
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| 495 | #define PPC_IRQ_CPM_SCC1 (PPC_STD_IRQ_LAST + 56) |
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| 496 | #define PPC_IRQ_CPM_PC15 (PPC_STD_IRQ_LAST + 57) |
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| 497 | |
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| 498 | #define PPC_IRQ_LAST PPC_IRQ_CPM_PC15 |
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| 499 | |
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| 500 | #elif defined(mpc8260) |
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| 501 | |
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| 502 | #define PPC_IRQ_INST_MISS (PPC_STD_IRQ_LAST+1) /*0x1000-Instruction TLB miss*/ |
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| 503 | #define PPC_IRQ_DATA_MISS (PPC_STD_IRQ_LAST+2) /*0x1100-Data TLB miss */ |
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| 504 | #define PPC_IRQ_DATA_L_MISS (PPC_STD_IRQ_LAST+3) /*0x1200-Data TLB load miss */ |
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| 505 | #define PPC_IRQ_DATA_S_MISS (PPC_STD_IRQ_LAST+4) /*0x1300-Data TLB store miss */ |
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| 506 | #define PPC_IRQ_INST_BPNT (PPC_STD_IRQ_LAST+5) /*0x1400-Inst address breakpoint */ |
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| 507 | #define PPC_IRQ_SYS_MGT (PPC_STD_IRQ_LAST+6) /*0x1500-System Management */ |
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| 508 | /* 0x1600 - 0x2F00 reserved */ |
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| 509 | #define PPC_IRQ_CPM_NONE (PPC_STD_IRQ_LAST + 50) |
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| 510 | #define PPC_IRQ_CPM_I2C (PPC_STD_IRQ_LAST + 51) |
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| 511 | #define PPC_IRQ_CPM_SPI (PPC_STD_IRQ_LAST + 52) |
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| 512 | #define PPC_IRQ_CPM_RISC_TIMER (PPC_STD_IRQ_LAST + 53) |
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| 513 | #define PPC_IRQ_CPM_SMC1 (PPC_STD_IRQ_LAST + 54) |
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| 514 | #define PPC_IRQ_CPM_SMC2 (PPC_STD_IRQ_LAST + 55) |
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| 515 | #define PPC_IRQ_CPM_IDMA1 (PPC_STD_IRQ_LAST + 56) |
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| 516 | #define PPC_IRQ_CPM_IDMA2 (PPC_STD_IRQ_LAST + 57) |
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| 517 | #define PPC_IRQ_CPM_IDMA3 (PPC_STD_IRQ_LAST + 58) |
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| 518 | #define PPC_IRQ_CPM_IDMA4 (PPC_STD_IRQ_LAST + 59) |
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| 519 | #define PPC_IRQ_CPM_SDMA (PPC_STD_IRQ_LAST + 60) |
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| 520 | #define PPC_IRQ_CPM_RES_A (PPC_STD_IRQ_LAST + 61) |
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| 521 | #define PPC_IRQ_CPM_TIMER1 (PPC_STD_IRQ_LAST + 62) |
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| 522 | #define PPC_IRQ_CPM_TIMER2 (PPC_STD_IRQ_LAST + 63) |
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| 523 | #define PPC_IRQ_CPM_TIMER3 (PPC_STD_IRQ_LAST + 64) |
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| 524 | #define PPC_IRQ_CPM_TIMER4 (PPC_STD_IRQ_LAST + 65) |
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| 525 | #define PPC_IRQ_CPM_TMCNT (PPC_STD_IRQ_LAST + 66) |
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| 526 | #define PPC_IRQ_CPM_PIT (PPC_STD_IRQ_LAST + 67) |
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| 527 | #define PPC_IRQ_CPM_RES_B (PPC_STD_IRQ_LAST + 68) |
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| 528 | #define PPC_IRQ_CPM_IRQ1 (PPC_STD_IRQ_LAST + 69) |
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| 529 | #define PPC_IRQ_CPM_IRQ2 (PPC_STD_IRQ_LAST + 70) |
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| 530 | #define PPC_IRQ_CPM_IRQ3 (PPC_STD_IRQ_LAST + 71) |
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| 531 | #define PPC_IRQ_CPM_IRQ4 (PPC_STD_IRQ_LAST + 72) |
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| 532 | #define PPC_IRQ_CPM_IRQ5 (PPC_STD_IRQ_LAST + 73) |
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| 533 | #define PPC_IRQ_CPM_IRQ6 (PPC_STD_IRQ_LAST + 74) |
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| 534 | #define PPC_IRQ_CPM_IRQ7 (PPC_STD_IRQ_LAST + 75) |
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| 535 | #define PPC_IRQ_CPM_RES_C (PPC_STD_IRQ_LAST + 76) |
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| 536 | #define PPC_IRQ_CPM_RES_D (PPC_STD_IRQ_LAST + 77) |
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| 537 | #define PPC_IRQ_CPM_RES_E (PPC_STD_IRQ_LAST + 78) |
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| 538 | #define PPC_IRQ_CPM_RES_F (PPC_STD_IRQ_LAST + 79) |
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| 539 | #define PPC_IRQ_CPM_RES_G (PPC_STD_IRQ_LAST + 80) |
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| 540 | #define PPC_IRQ_CPM_RES_H (PPC_STD_IRQ_LAST + 81) |
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| 541 | #define PPC_IRQ_CPM_FCC1 (PPC_STD_IRQ_LAST + 82) |
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| 542 | #define PPC_IRQ_CPM_FCC2 (PPC_STD_IRQ_LAST + 83) |
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| 543 | #define PPC_IRQ_CPM_FCC3 (PPC_STD_IRQ_LAST + 84) |
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| 544 | #define PPC_IRQ_CPM_RES_I (PPC_STD_IRQ_LAST + 85) |
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| 545 | #define PPC_IRQ_CPM_MCC1 (PPC_STD_IRQ_LAST + 86) |
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| 546 | #define PPC_IRQ_CPM_MCC2 (PPC_STD_IRQ_LAST + 87) |
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| 547 | #define PPC_IRQ_CPM_RES_J (PPC_STD_IRQ_LAST + 88) |
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| 548 | #define PPC_IRQ_CPM_RES_K (PPC_STD_IRQ_LAST + 89) |
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| 549 | #define PPC_IRQ_CPM_SCC1 (PPC_STD_IRQ_LAST + 90) |
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| 550 | #define PPC_IRQ_CPM_SCC2 (PPC_STD_IRQ_LAST + 91) |
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| 551 | #define PPC_IRQ_CPM_SCC3 (PPC_STD_IRQ_LAST + 92) |
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| 552 | #define PPC_IRQ_CPM_SCC4 (PPC_STD_IRQ_LAST + 93) |
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| 553 | #define PPC_IRQ_CPM_RES_L (PPC_STD_IRQ_LAST + 94) |
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| 554 | #define PPC_IRQ_CPM_RES_M (PPC_STD_IRQ_LAST + 95) |
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| 555 | #define PPC_IRQ_CPM_RES_N (PPC_STD_IRQ_LAST + 96) |
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| 556 | #define PPC_IRQ_CPM_RES_O (PPC_STD_IRQ_LAST + 97) |
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| 557 | #define PPC_IRQ_CPM_PC15 (PPC_STD_IRQ_LAST + 98) |
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| 558 | #define PPC_IRQ_CPM_PC14 (PPC_STD_IRQ_LAST + 99) |
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| 559 | #define PPC_IRQ_CPM_PC13 (PPC_STD_IRQ_LAST + 100) |
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| 560 | #define PPC_IRQ_CPM_PC12 (PPC_STD_IRQ_LAST + 101) |
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| 561 | #define PPC_IRQ_CPM_PC11 (PPC_STD_IRQ_LAST + 102) |
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| 562 | #define PPC_IRQ_CPM_PC10 (PPC_STD_IRQ_LAST + 103) |
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| 563 | #define PPC_IRQ_CPM_PC9 (PPC_STD_IRQ_LAST + 104) |
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| 564 | #define PPC_IRQ_CPM_PC8 (PPC_STD_IRQ_LAST + 105) |
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| 565 | #define PPC_IRQ_CPM_PC7 (PPC_STD_IRQ_LAST + 106) |
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| 566 | #define PPC_IRQ_CPM_PC6 (PPC_STD_IRQ_LAST + 107) |
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| 567 | #define PPC_IRQ_CPM_PC5 (PPC_STD_IRQ_LAST + 108) |
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| 568 | #define PPC_IRQ_CPM_PC4 (PPC_STD_IRQ_LAST + 109) |
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| 569 | #define PPC_IRQ_CPM_PC3 (PPC_STD_IRQ_LAST + 110) |
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| 570 | #define PPC_IRQ_CPM_PC2 (PPC_STD_IRQ_LAST + 111) |
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| 571 | #define PPC_IRQ_CPM_PC1 (PPC_STD_IRQ_LAST + 112) |
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| 572 | #define PPC_IRQ_CPM_PC0 (PPC_STD_IRQ_LAST + 113) |
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| 573 | |
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| 574 | #define PPC_IRQ_LAST PPC_IRQ_CPM_PC0 |
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| 575 | |
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| 576 | #endif |
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| 577 | |
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| 578 | |
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| 579 | /* |
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| 580 | * If the maximum number of exception sources is too low, |
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| 581 | * then fix it |
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| 582 | */ |
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| 583 | |
|---|
| 584 | #if PPC_INTERRUPT_MAX <= PPC_IRQ_LAST |
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| 585 | #undef PPC_INTERRUPT_MAX |
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| 586 | #define PPC_INTERRUPT_MAX ((PPC_IRQ_LAST) + 1) |
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| 587 | #endif |
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| 588 | |
|---|
| 589 | /* |
|---|
| 590 | * Machine Status Register (MSR) Constants Used by RTEMS |
|---|
| 591 | */ |
|---|
| 592 | |
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| 593 | #if PPC_HAS_RI |
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| 594 | #define PPC_MSR_RI 0x000000002 /* bit 30 - recoverable exception */ |
|---|
| 595 | #endif |
|---|
| 596 | |
|---|
| 597 | #define PPC_MSR_DR 0x000000010 /* bit 27 - data address translation */ |
|---|
| 598 | #define PPC_MSR_IR 0x000000020 /* bit 26 - instruction addr translation*/ |
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| 599 | |
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| 600 | /* |
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| 601 | * Some PPC model manuals refer to the Exception Prefix (EP) bit as |
|---|
| 602 | * IP for no apparent reason. |
|---|
| 603 | */ |
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| 604 | #if (PPC_HAS_EXCEPTION_PREFIX) |
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| 605 | #define PPC_MSR_EP 0x000000040 /* bit 25 - exception prefix */ |
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| 606 | #else |
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| 607 | #define PPC_MSR_EP 0x000000000 /* bit 25 - exception prefix */ |
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| 608 | #endif |
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| 609 | |
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| 610 | #if (PPC_HAS_FPU) |
|---|
| 611 | #define PPC_MSR_FP 0x000002000 /* bit 18 - floating point enable */ |
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| 612 | #else |
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| 613 | #define PPC_MSR_FP 0x000000000 /* bit 18 - floating point enable */ |
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| 614 | #endif |
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| 615 | |
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| 616 | #if (PPC_LOW_POWER_MODE == PPC_LOW_POWER_MODE_NONE) |
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| 617 | #define PPC_MSR_POW 0x000000000 /* bit 13 - power management enable */ |
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| 618 | #else |
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| 619 | #define PPC_MSR_POW 0x000040000 /* bit 13 - power management enable */ |
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| 620 | #endif |
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| 621 | |
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| 622 | #define PPC_MSR_ME 0x000001000 /* bit 19 - machine check enable */ |
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| 623 | #define PPC_MSR_EE 0x000008000 /* bit 16 - external interrupt enable */ |
|---|
| 624 | |
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| 625 | #if (PPC_HAS_RFCI) |
|---|
| 626 | #define PPC_MSR_CE 0x000020000 /* bit 14 - critical interrupt enable */ |
|---|
| 627 | #else |
|---|
| 628 | #define PPC_MSR_CE 0x000000000 /* bit 14 - critical interrupt enable */ |
|---|
| 629 | #endif |
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| 630 | |
|---|
| 631 | #define PPC_MSR_DISABLE_MASK (PPC_MSR_ME|PPC_MSR_EE|PPC_MSR_CE) |
|---|
| 632 | |
|---|
| 633 | #define PPC_MINIMUM_STACK_FRAME_SIZE PPC_STACK_ALIGNMENT |
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| 634 | |
|---|
| 635 | #ifdef __cplusplus |
|---|
| 636 | } |
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| 637 | #endif |
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| 638 | |
|---|
| 639 | #endif /* _RTEMS_POWERPC_POWERPC_H */ |
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