1 | /* vectors.s 1.0 - 95/08/08 |
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2 | * |
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3 | * This file contains the assembly code for the PowerPC 403 |
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4 | * interrupt veneers for RTEMS. |
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5 | * |
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6 | * Author: Andrew Bray <andy@i-cubed.demon.co.uk> |
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7 | * |
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8 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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9 | * |
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10 | * To anyone who acknowledges that this file is provided "AS IS" |
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11 | * without any express or implied warranty: |
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12 | * permission to use, copy, modify, and distribute this file |
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13 | * for any purpose is hereby granted without fee, provided that |
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14 | * the above copyright notice and this notice appears in all |
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15 | * copies, and that the name of i-cubed limited not be used in |
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16 | * advertising or publicity pertaining to distribution of the |
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17 | * software without specific, written prior permission. |
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18 | * i-cubed limited makes no representations about the suitability |
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19 | * of this software for any purpose. |
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20 | * |
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21 | */ |
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22 | |
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23 | /* |
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24 | * The issue with this file is getting it loaded at the right place. |
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25 | * The first vector MUST be at address 0x????0100. |
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26 | * How this is achieved is dependant on the tool chain. |
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27 | * |
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28 | * However the basic mechanism for ELF assemblers is to create a |
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29 | * section called ".vectors", which will be loaded to an address |
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30 | * between 0x????0000 and 0x????0100 (inclusive) via a link script. |
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31 | * |
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32 | * The basic mechanism for XCOFF assemblers is to place it in the |
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33 | * normal text section, and arrange for this file to be located |
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34 | * at an appropriate position on the linker command line. |
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35 | * |
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36 | * The variable 'PPC_VECTOR_FILE_BASE' must be defined to be the |
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37 | * offset from 0x????0000 to the first location in the file. This |
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38 | * will usually be 0x0000 or 0x0100. |
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39 | */ |
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40 | |
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41 | #include "asm.h" |
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42 | |
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43 | #ifndef PPC_VECTOR_FILE_BASE |
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44 | #error "PPC_VECTOR_FILE_BASE is not defined." |
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45 | #endif |
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46 | |
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47 | /* Where this file will be loaded */ |
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48 | .set file_base, PPC_VECTOR_FILE_BASE |
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49 | |
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50 | /* Offset to store reg 0 */ |
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51 | |
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52 | .set IP_LINK, 0 |
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53 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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54 | .set IP_0, (IP_LINK + 56) |
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55 | #else |
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56 | .set IP_0, (IP_LINK + 8) |
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57 | #endif |
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58 | .set IP_2, (IP_0 + 4) |
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59 | |
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60 | .set IP_3, (IP_2 + 4) |
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61 | .set IP_4, (IP_3 + 4) |
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62 | .set IP_5, (IP_4 + 4) |
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63 | .set IP_6, (IP_5 + 4) |
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64 | |
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65 | .set IP_7, (IP_6 + 4) |
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66 | .set IP_8, (IP_7 + 4) |
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67 | .set IP_9, (IP_8 + 4) |
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68 | .set IP_10, (IP_9 + 4) |
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69 | |
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70 | .set IP_11, (IP_10 + 4) |
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71 | .set IP_12, (IP_11 + 4) |
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72 | .set IP_13, (IP_12 + 4) |
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73 | .set IP_28, (IP_13 + 4) |
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74 | |
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75 | .set IP_29, (IP_28 + 4) |
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76 | .set IP_30, (IP_29 + 4) |
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77 | .set IP_31, (IP_30 + 4) |
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78 | .set IP_CR, (IP_31 + 4) |
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79 | |
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80 | .set IP_CTR, (IP_CR + 4) |
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81 | .set IP_XER, (IP_CTR + 4) |
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82 | .set IP_LR, (IP_XER + 4) |
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83 | .set IP_PC, (IP_LR + 4) |
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84 | |
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85 | .set IP_MSR, (IP_PC + 4) |
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86 | |
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87 | .set IP_END, (IP_MSR + 16) |
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88 | |
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89 | /* Vector offsets */ |
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90 | .set begin_vector,0x0000 |
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91 | .set crit_vector,0x0100 |
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92 | .set mach_vector,0x0200 |
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93 | .set prot_vector,0x0300 |
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94 | .set ext_vector,0x0500 |
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95 | .set align_vector,0x0600 |
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96 | .set prog_vector,0x0700 |
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97 | .set sys_vector,0x0C00 |
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98 | .set pit_vector,0x1000 |
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99 | .set fit_vector,0x1010 |
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100 | .set wadt_vector,0x1020 |
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101 | .set debug_vector,0x2000 |
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102 | |
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103 | /* Go to the right section */ |
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104 | #if PPC_ASM == PPC_ASM_ELF |
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105 | .section .vectors,"awx",@progbits |
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106 | #elif PPC_ASM == PPC_ASM_XCOFF |
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107 | .csect .text[PR] |
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108 | #endif |
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109 | |
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110 | PUBLIC_VAR (__vectors) |
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111 | SYM (__vectors): |
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112 | |
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113 | /* Critical error handling */ |
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114 | .org crit_vector - file_base |
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115 | mtsprg1 r0 |
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116 | mfsprg2 r0 |
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117 | mtmsr r0 |
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118 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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119 | #if (PPC_HAS_FPU) |
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120 | stwu r1, -(20*4 + 18*8 + IP_END)(r1) |
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121 | #else |
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122 | stwu r1, -(20*4 + IP_END)(r1) |
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123 | #endif |
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124 | #else |
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125 | stwu r1, -(IP_END)(r1) |
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126 | #endif |
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127 | mfsprg1 r0 |
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128 | stw r0, IP_0(r1) |
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129 | |
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130 | li r0, PPC_IRQ_CRIT |
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131 | b PROC (_ISR_HandlerC) |
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132 | |
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133 | /* Machine check exception */ |
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134 | .org mach_vector - file_base |
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135 | mtsprg1 r0 |
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136 | mfsprg2 r0 |
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137 | mtmsr r0 |
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138 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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139 | #if (PPC_HAS_FPU) |
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140 | stwu r1, -(20*4 + 18*8 + IP_END)(r1) |
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141 | #else |
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142 | stwu r1, -(20*4 + IP_END)(r1) |
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143 | #endif |
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144 | #else |
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145 | stwu r1, -(IP_END)(r1) |
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146 | #endif |
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147 | mfsprg1 r0 |
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148 | stw r0, IP_0(r1) |
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149 | |
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150 | li r0, PPC_IRQ_MCHECK |
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151 | b PROC (_ISR_HandlerC) |
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152 | |
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153 | /* Protection exception */ |
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154 | .org prot_vector - file_base |
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155 | mtsprg0 r0 |
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156 | mfsprg2 r0 |
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157 | mtmsr r0 |
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158 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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159 | #if (PPC_HAS_FPU) |
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160 | stwu r1, -(20*4 + 18*8 + IP_END)(r1) |
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161 | #else |
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162 | stwu r1, -(20*4 + IP_END)(r1) |
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163 | #endif |
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164 | #else |
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165 | stwu r1, -(IP_END)(r1) |
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166 | #endif |
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167 | mfsprg0 r0 |
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168 | stw r0, IP_0(r1) |
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169 | |
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170 | li r0, PPC_IRQ_PROTECT |
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171 | b PROC (_ISR_Handler) |
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172 | |
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173 | /* External interrupt */ |
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174 | .org ext_vector - file_base |
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175 | mtsprg0 r0 |
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176 | mfsprg2 r0 |
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177 | mtmsr r0 |
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178 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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179 | #if (PPC_HAS_FPU) |
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180 | stwu r1, -(20*4 + 18*8 + IP_END)(r1) |
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181 | #else |
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182 | stwu r1, -(20*4 + IP_END)(r1) |
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183 | #endif |
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184 | #else |
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185 | stwu r1, -(IP_END)(r1) |
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186 | #endif |
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187 | mfsprg0 r0 |
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188 | stw r0, IP_0(r1) |
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189 | |
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190 | li r0, PPC_IRQ_EXTERNAL |
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191 | b PROC (_ISR_Handler) |
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192 | |
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193 | /* Align exception */ |
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194 | .org align_vector - file_base |
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195 | .extern align_h |
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196 | b align_h |
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197 | |
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198 | /* Program exception */ |
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199 | .org prog_vector - file_base |
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200 | mtsprg0 r0 |
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201 | mfsprg2 r0 |
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202 | mtmsr r0 |
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203 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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204 | #if (PPC_HAS_FPU) |
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205 | stwu r1, -(20*4 + 18*8 + IP_END)(r1) |
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206 | #else |
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207 | stwu r1, -(20*4 + IP_END)(r1) |
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208 | #endif |
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209 | #else |
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210 | stwu r1, -(IP_END)(r1) |
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211 | #endif |
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212 | mfsprg0 r0 |
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213 | stw r0, IP_0(r1) |
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214 | |
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215 | li r0, PPC_IRQ_PROGRAM |
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216 | b PROC (_ISR_Handler) |
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217 | |
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218 | /* System call */ |
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219 | .org sys_vector - file_base |
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220 | mtsprg0 r0 |
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221 | mfsprg2 r0 |
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222 | mtmsr r0 |
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223 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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224 | #if (PPC_HAS_FPU) |
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225 | stwu r1, -(20*4 + 18*8 + IP_END)(r1) |
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226 | #else |
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227 | stwu r1, -(20*4 + IP_END)(r1) |
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228 | #endif |
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229 | #else |
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230 | stwu r1, -(IP_END)(r1) |
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231 | #endif |
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232 | mfsprg0 r0 |
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233 | stw r0, IP_0(r1) |
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234 | |
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235 | li r0, PPC_IRQ_SCALL |
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236 | b PROC (_ISR_Handler) |
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237 | |
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238 | /* PIT interrupt */ |
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239 | .org pit_vector - file_base |
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240 | b pit |
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241 | |
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242 | /* FIT interrupt */ |
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243 | .org fit_vector - file_base |
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244 | b fit |
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245 | |
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246 | /* Watchdog interrupt */ |
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247 | .org wadt_vector - file_base |
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248 | b watch |
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249 | |
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250 | /* PIT interrupt */ |
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251 | pit: |
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252 | mtsprg0 r0 |
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253 | mfsprg2 r0 |
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254 | mtmsr r0 |
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255 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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256 | #if (PPC_HAS_FPU) |
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257 | stwu r1, -(20*4 + 18*8 + IP_END)(r1) |
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258 | #else |
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259 | stwu r1, -(20*4 + IP_END)(r1) |
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260 | #endif |
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261 | #else |
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262 | stwu r1, -(IP_END)(r1) |
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263 | #endif |
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264 | mfsprg0 r0 |
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265 | stw r0, IP_0(r1) |
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266 | |
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267 | li r0, PPC_IRQ_PIT |
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268 | b PROC (_ISR_Handler) |
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269 | |
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270 | /* FIT interrupt */ |
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271 | fit: |
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272 | mtsprg0 r0 |
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273 | mfsprg2 r0 |
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274 | mtmsr r0 |
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275 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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276 | #if (PPC_HAS_FPU) |
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277 | stwu r1, -(20*4 + 18*8 + IP_END)(r1) |
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278 | #else |
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279 | stwu r1, -(20*4 + IP_END)(r1) |
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280 | #endif |
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281 | #else |
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282 | stwu r1, -(IP_END)(r1) |
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283 | #endif |
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284 | mfsprg0 r0 |
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285 | stw r0, IP_0(r1) |
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286 | |
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287 | li r0, PPC_IRQ_FIT |
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288 | b PROC (_ISR_Handler) |
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289 | |
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290 | /* Watchdog interrupt */ |
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291 | watch: |
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292 | mtsprg1 r0 |
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293 | mfsprg2 r0 |
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294 | mtmsr r0 |
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295 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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296 | #if (PPC_HAS_FPU) |
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297 | stwu r1, -(20*4 + 18*8 + IP_END)(r1) |
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298 | #else |
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299 | stwu r1, -(20*4 + IP_END)(r1) |
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300 | #endif |
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301 | #else |
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302 | stwu r1, -(IP_END)(r1) |
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303 | #endif |
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304 | mfsprg1 r0 |
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305 | stw r0, IP_0(r1) |
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306 | |
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307 | li r0, PPC_IRQ_WATCHDOG |
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308 | b PROC (_ISR_HandlerC) |
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309 | |
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310 | /* Debug exception */ |
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311 | debug: |
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312 | mtsprg1 r0 |
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313 | mfsprg2 r0 |
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314 | mtmsr r0 |
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315 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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316 | #if (PPC_HAS_FPU) |
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317 | stwu r1, -(20*4 + 18*8 + IP_END)(r1) |
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318 | #else |
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319 | stwu r1, -(20*4 + IP_END)(r1) |
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320 | #endif |
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321 | #else |
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322 | stwu r1, -(IP_END)(r1) |
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323 | #endif |
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324 | mfsprg1 r0 |
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325 | stw r0, IP_0(r1) |
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326 | |
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327 | li r0, PPC_IRQ_DEBUG |
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328 | b PROC (_ISR_HandlerC) |
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329 | |
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330 | /* Debug exception */ |
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331 | .org debug_vector - file_base |
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332 | b debug |
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