[e57b0e2] | 1 | /* vectors.s 1.1 - 95/12/04 |
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[3235ad9] | 2 | * |
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| 3 | * This file contains the assembly code for the PowerPC 403 |
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| 4 | * interrupt veneers for RTEMS. |
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| 5 | * |
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[e57b0e2] | 6 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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[3235ad9] | 7 | * |
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| 8 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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| 9 | * |
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| 10 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 11 | * without any express or implied warranty: |
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| 12 | * permission to use, copy, modify, and distribute this file |
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| 13 | * for any purpose is hereby granted without fee, provided that |
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| 14 | * the above copyright notice and this notice appears in all |
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| 15 | * copies, and that the name of i-cubed limited not be used in |
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| 16 | * advertising or publicity pertaining to distribution of the |
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| 17 | * software without specific, written prior permission. |
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| 18 | * i-cubed limited makes no representations about the suitability |
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| 19 | * of this software for any purpose. |
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| 20 | * |
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| 21 | */ |
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| 22 | |
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| 23 | /* |
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| 24 | * The issue with this file is getting it loaded at the right place. |
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| 25 | * The first vector MUST be at address 0x????0100. |
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| 26 | * How this is achieved is dependant on the tool chain. |
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| 27 | * |
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| 28 | * However the basic mechanism for ELF assemblers is to create a |
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| 29 | * section called ".vectors", which will be loaded to an address |
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| 30 | * between 0x????0000 and 0x????0100 (inclusive) via a link script. |
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| 31 | * |
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| 32 | * The variable 'PPC_VECTOR_FILE_BASE' must be defined to be the |
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| 33 | * offset from 0x????0000 to the first location in the file. This |
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| 34 | * will usually be 0x0000 or 0x0100. |
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[e57b0e2] | 35 | * |
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| 36 | * $Id$ |
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[3235ad9] | 37 | */ |
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| 38 | |
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[cdf62746] | 39 | #include <bsp.h> /* PPC_VECTOR_FILE_BASE */ |
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[11c2382] | 40 | #include <rtems/asm.h> |
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[3235ad9] | 41 | |
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| 42 | #ifndef PPC_VECTOR_FILE_BASE |
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| 43 | #error "PPC_VECTOR_FILE_BASE is not defined." |
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| 44 | #endif |
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| 45 | |
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| 46 | /* Where this file will be loaded */ |
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| 47 | .set file_base, PPC_VECTOR_FILE_BASE |
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| 48 | |
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| 49 | /* Offset to store reg 0 */ |
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| 50 | |
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| 51 | .set IP_LINK, 0 |
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| 52 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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| 53 | .set IP_0, (IP_LINK + 56) |
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| 54 | #else |
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| 55 | .set IP_0, (IP_LINK + 8) |
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| 56 | #endif |
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| 57 | .set IP_2, (IP_0 + 4) |
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| 58 | |
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| 59 | .set IP_3, (IP_2 + 4) |
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| 60 | .set IP_4, (IP_3 + 4) |
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| 61 | .set IP_5, (IP_4 + 4) |
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| 62 | .set IP_6, (IP_5 + 4) |
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| 63 | |
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| 64 | .set IP_7, (IP_6 + 4) |
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| 65 | .set IP_8, (IP_7 + 4) |
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| 66 | .set IP_9, (IP_8 + 4) |
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| 67 | .set IP_10, (IP_9 + 4) |
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| 68 | |
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| 69 | .set IP_11, (IP_10 + 4) |
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| 70 | .set IP_12, (IP_11 + 4) |
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| 71 | .set IP_13, (IP_12 + 4) |
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| 72 | .set IP_28, (IP_13 + 4) |
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| 73 | |
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| 74 | .set IP_29, (IP_28 + 4) |
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| 75 | .set IP_30, (IP_29 + 4) |
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| 76 | .set IP_31, (IP_30 + 4) |
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| 77 | .set IP_CR, (IP_31 + 4) |
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| 78 | |
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| 79 | .set IP_CTR, (IP_CR + 4) |
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| 80 | .set IP_XER, (IP_CTR + 4) |
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| 81 | .set IP_LR, (IP_XER + 4) |
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| 82 | .set IP_PC, (IP_LR + 4) |
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| 83 | |
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| 84 | .set IP_MSR, (IP_PC + 4) |
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| 85 | |
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| 86 | .set IP_END, (IP_MSR + 16) |
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| 87 | |
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| 88 | /* Vector offsets */ |
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| 89 | .set begin_vector,0x0000 |
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| 90 | .set crit_vector,0x0100 |
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| 91 | .set mach_vector,0x0200 |
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| 92 | .set prot_vector,0x0300 |
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| 93 | .set ext_vector,0x0500 |
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| 94 | .set align_vector,0x0600 |
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| 95 | .set prog_vector,0x0700 |
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[1a3e4fa] | 96 | .set dec_vector,0x0900 |
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[3235ad9] | 97 | .set sys_vector,0x0C00 |
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| 98 | .set pit_vector,0x1000 |
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| 99 | .set fit_vector,0x1010 |
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| 100 | .set wadt_vector,0x1020 |
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| 101 | .set debug_vector,0x2000 |
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| 102 | |
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| 103 | /* Go to the right section */ |
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| 104 | #if PPC_ASM == PPC_ASM_ELF |
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| 105 | .section .vectors,"awx",@progbits |
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| 106 | #endif |
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| 107 | |
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| 108 | PUBLIC_VAR (__vectors) |
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| 109 | SYM (__vectors): |
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| 110 | |
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| 111 | /* Critical error handling */ |
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| 112 | .org crit_vector - file_base |
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| 113 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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| 114 | #if (PPC_HAS_FPU) |
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| 115 | stwu r1, -(20*4 + 18*8 + IP_END)(r1) |
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| 116 | #else |
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| 117 | stwu r1, -(20*4 + IP_END)(r1) |
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| 118 | #endif |
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| 119 | #else |
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| 120 | stwu r1, -(IP_END)(r1) |
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| 121 | #endif |
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| 122 | stw r0, IP_0(r1) |
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| 123 | |
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| 124 | li r0, PPC_IRQ_CRIT |
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| 125 | b PROC (_ISR_HandlerC) |
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| 126 | |
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| 127 | /* Machine check exception */ |
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| 128 | .org mach_vector - file_base |
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| 129 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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| 130 | #if (PPC_HAS_FPU) |
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| 131 | stwu r1, -(20*4 + 18*8 + IP_END)(r1) |
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| 132 | #else |
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| 133 | stwu r1, -(20*4 + IP_END)(r1) |
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| 134 | #endif |
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| 135 | #else |
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| 136 | stwu r1, -(IP_END)(r1) |
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| 137 | #endif |
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| 138 | stw r0, IP_0(r1) |
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| 139 | |
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| 140 | li r0, PPC_IRQ_MCHECK |
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| 141 | b PROC (_ISR_HandlerC) |
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| 142 | |
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| 143 | /* Protection exception */ |
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| 144 | .org prot_vector - file_base |
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| 145 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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| 146 | #if (PPC_HAS_FPU) |
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| 147 | stwu r1, -(20*4 + 18*8 + IP_END)(r1) |
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| 148 | #else |
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| 149 | stwu r1, -(20*4 + IP_END)(r1) |
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| 150 | #endif |
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| 151 | #else |
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| 152 | stwu r1, -(IP_END)(r1) |
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| 153 | #endif |
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| 154 | stw r0, IP_0(r1) |
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| 155 | |
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| 156 | li r0, PPC_IRQ_PROTECT |
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| 157 | b PROC (_ISR_Handler) |
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| 158 | |
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| 159 | /* External interrupt */ |
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| 160 | .org ext_vector - file_base |
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| 161 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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| 162 | #if (PPC_HAS_FPU) |
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| 163 | stwu r1, -(20*4 + 18*8 + IP_END)(r1) |
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| 164 | #else |
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| 165 | stwu r1, -(20*4 + IP_END)(r1) |
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| 166 | #endif |
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| 167 | #else |
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| 168 | stwu r1, -(IP_END)(r1) |
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| 169 | #endif |
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| 170 | stw r0, IP_0(r1) |
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| 171 | |
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| 172 | li r0, PPC_IRQ_EXTERNAL |
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| 173 | b PROC (_ISR_Handler) |
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| 174 | |
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| 175 | /* Align exception */ |
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| 176 | .org align_vector - file_base |
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| 177 | .extern align_h |
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| 178 | b align_h |
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| 179 | |
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| 180 | /* Program exception */ |
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| 181 | .org prog_vector - file_base |
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| 182 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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| 183 | #if (PPC_HAS_FPU) |
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| 184 | stwu r1, -(20*4 + 18*8 + IP_END)(r1) |
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| 185 | #else |
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| 186 | stwu r1, -(20*4 + IP_END)(r1) |
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| 187 | #endif |
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| 188 | #else |
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| 189 | stwu r1, -(IP_END)(r1) |
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| 190 | #endif |
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| 191 | stw r0, IP_0(r1) |
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| 192 | |
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| 193 | li r0, PPC_IRQ_PROGRAM |
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| 194 | b PROC (_ISR_Handler) |
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| 195 | |
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[1a3e4fa] | 196 | /* Decrementer exception */ |
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| 197 | .org dec_vector - file_base |
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| 198 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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| 199 | #if (PPC_HAS_FPU) |
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| 200 | stwu r1, -(20*4 + 18*8 + IP_END)(r1) |
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| 201 | #else |
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| 202 | stwu r1, -(20*4 + IP_END)(r1) |
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| 203 | #endif |
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| 204 | #else |
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| 205 | stwu r1, -(IP_END)(r1) |
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| 206 | #endif |
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| 207 | stw r0, IP_0(r1) |
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| 208 | |
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| 209 | li r0, PPC_IRQ_PROGRAM |
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| 210 | b PROC (_ISR_Handler) |
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| 211 | |
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[3235ad9] | 212 | /* System call */ |
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| 213 | .org sys_vector - file_base |
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| 214 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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| 215 | #if (PPC_HAS_FPU) |
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| 216 | stwu r1, -(20*4 + 18*8 + IP_END)(r1) |
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| 217 | #else |
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| 218 | stwu r1, -(20*4 + IP_END)(r1) |
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| 219 | #endif |
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| 220 | #else |
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| 221 | stwu r1, -(IP_END)(r1) |
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| 222 | #endif |
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| 223 | stw r0, IP_0(r1) |
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| 224 | |
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| 225 | li r0, PPC_IRQ_SCALL |
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| 226 | b PROC (_ISR_Handler) |
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| 227 | |
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| 228 | /* PIT interrupt */ |
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| 229 | .org pit_vector - file_base |
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| 230 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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| 231 | #if (PPC_HAS_FPU) |
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| 232 | stwu r1, -(20*4 + 18*8 + IP_END)(r1) |
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| 233 | #else |
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| 234 | stwu r1, -(20*4 + IP_END)(r1) |
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| 235 | #endif |
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| 236 | #else |
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| 237 | stwu r1, -(IP_END)(r1) |
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| 238 | #endif |
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| 239 | stw r0, IP_0(r1) |
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| 240 | |
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| 241 | li r0, PPC_IRQ_PIT |
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| 242 | b PROC (_ISR_Handler) |
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[e57b0e2] | 243 | |
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[3235ad9] | 244 | /* FIT interrupt */ |
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[e57b0e2] | 245 | .org fit_vector - file_base |
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[3235ad9] | 246 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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| 247 | #if (PPC_HAS_FPU) |
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| 248 | stwu r1, -(20*4 + 18*8 + IP_END)(r1) |
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| 249 | #else |
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| 250 | stwu r1, -(20*4 + IP_END)(r1) |
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| 251 | #endif |
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| 252 | #else |
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| 253 | stwu r1, -(IP_END)(r1) |
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| 254 | #endif |
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| 255 | stw r0, IP_0(r1) |
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| 256 | |
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| 257 | li r0, PPC_IRQ_FIT |
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| 258 | b PROC (_ISR_Handler) |
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[e57b0e2] | 259 | |
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[3235ad9] | 260 | /* Watchdog interrupt */ |
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[e57b0e2] | 261 | .org wadt_vector - file_base |
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[3235ad9] | 262 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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| 263 | #if (PPC_HAS_FPU) |
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| 264 | stwu r1, -(20*4 + 18*8 + IP_END)(r1) |
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| 265 | #else |
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| 266 | stwu r1, -(20*4 + IP_END)(r1) |
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| 267 | #endif |
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| 268 | #else |
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| 269 | stwu r1, -(IP_END)(r1) |
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| 270 | #endif |
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| 271 | stw r0, IP_0(r1) |
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| 272 | |
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| 273 | li r0, PPC_IRQ_WATCHDOG |
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| 274 | b PROC (_ISR_HandlerC) |
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| 275 | |
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| 276 | /* Debug exception */ |
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| 277 | debug: |
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| 278 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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| 279 | #if (PPC_HAS_FPU) |
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| 280 | stwu r1, -(20*4 + 18*8 + IP_END)(r1) |
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| 281 | #else |
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| 282 | stwu r1, -(20*4 + IP_END)(r1) |
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| 283 | #endif |
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| 284 | #else |
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| 285 | stwu r1, -(IP_END)(r1) |
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| 286 | #endif |
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| 287 | stw r0, IP_0(r1) |
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| 288 | |
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| 289 | li r0, PPC_IRQ_DEBUG |
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| 290 | b PROC (_ISR_HandlerC) |
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| 291 | |
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| 292 | /* Debug exception */ |
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| 293 | .org debug_vector - file_base |
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| 294 | b debug |
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