1 | /* ictrl.c |
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2 | * |
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3 | * This routine installs and handles external interrupt vectors for |
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4 | * PowerPC 403 CPU built-in external interrupt controller |
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5 | * |
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6 | * Author: Thomas Doerfler <td@imd.m.isar.de> |
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7 | * |
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8 | * COPYRIGHT (c) 1998 by IMD, Puchheim, Germany |
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9 | * |
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10 | * To anyone who acknowledges that this file is provided "AS IS" |
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11 | * without any express or implied warranty: |
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12 | * permission to use, copy, modify, and distribute this file |
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13 | * for any purpose is hereby granted without fee, provided that |
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14 | * the above copyright notice and this notice appears in all |
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15 | * copies, and that the name of IMD not be used in |
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16 | * advertising or publicity pertaining to distribution of the |
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17 | * software without specific, written prior permission. |
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18 | * IMD makes no representations about the suitability |
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19 | * of this software for any purpose. |
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20 | * |
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21 | * Modifications for PPC405GP by Dennis Ehlin |
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22 | * |
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23 | */ |
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24 | |
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25 | #include "ictrl.h" |
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26 | #include <rtems.h> |
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27 | #include <rtems/libio.h> |
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28 | |
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29 | #include <stdlib.h> /* for atexit() */ |
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30 | |
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31 | /* |
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32 | * ISR vector table to dispatch external interrupts |
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33 | */ |
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34 | |
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35 | rtems_isr_entry ictrl_vector_table[PPC_IRQ_EXT_MAX]; |
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36 | |
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37 | /* |
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38 | * |
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39 | * some utilities to access the EXI* registers |
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40 | * |
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41 | */ |
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42 | |
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43 | /* |
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44 | * clear bits in EXISR that have a bit set in mask |
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45 | */ |
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46 | #if defined(ppc405) |
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47 | RTEMS_INLINE_ROUTINE void |
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48 | clr_exisr(uint32_t mask) |
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49 | { |
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50 | asm volatile ("mtdcr 0xC0,%0"::"r" (mask));/*EXISR*/ |
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51 | } |
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52 | |
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53 | /* |
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54 | * get value of EXISR |
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55 | */ |
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56 | RTEMS_INLINE_ROUTINE uint32_t |
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57 | get_exisr(void) |
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58 | { |
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59 | uint32_t val; |
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60 | |
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61 | asm volatile ("mfdcr %0,0xC0":"=r" (val));/*EXISR*/ |
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62 | return val; |
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63 | } |
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64 | |
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65 | /* |
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66 | * get value of EXIER |
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67 | */ |
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68 | RTEMS_INLINE_ROUTINE uint32_t |
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69 | get_exier(void) |
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70 | { |
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71 | uint32_t val; |
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72 | asm volatile ("mfdcr %0,0xC2":"=r" (val));/*EXIER*/ |
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73 | return val; |
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74 | } |
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75 | |
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76 | /* |
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77 | * set value of EXIER |
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78 | */ |
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79 | RTEMS_INLINE_ROUTINE void |
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80 | set_exier(uint32_t val) |
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81 | { |
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82 | asm volatile ("mtdcr 0xC2,%0"::"r" (val));/*EXIER*/ |
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83 | } |
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84 | |
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85 | #else /* not ppc405 */ |
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86 | |
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87 | RTEMS_INLINE_ROUTINE void |
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88 | clr_exisr(uint32_t mask) |
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89 | { |
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90 | asm volatile ("mtdcr 0x40,%0"::"r" (mask));/*EXISR*/ |
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91 | } |
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92 | |
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93 | /* |
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94 | * get value of EXISR |
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95 | */ |
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96 | RTEMS_INLINE_ROUTINE uint32_t |
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97 | get_exisr(void) |
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98 | { |
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99 | uint32_t val; |
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100 | |
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101 | asm volatile ("mfdcr %0,0x40":"=r" (val));/*EXISR*/ |
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102 | return val; |
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103 | } |
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104 | |
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105 | /* |
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106 | * get value of EXIER |
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107 | */ |
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108 | RTEMS_INLINE_ROUTINE uint32_t |
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109 | get_exier(void) |
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110 | { |
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111 | uint32_t val; |
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112 | asm volatile ("mfdcr %0,0x42":"=r" (val));/*EXIER*/ |
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113 | return val; |
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114 | } |
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115 | |
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116 | /* |
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117 | * set value of EXIER |
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118 | */ |
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119 | RTEMS_INLINE_ROUTINE void |
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120 | set_exier(uint32_t val) |
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121 | { |
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122 | asm volatile ("mtdcr 0x42,%0"::"r" (val));/*EXIER*/ |
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123 | } |
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124 | #endif /* ppc405 */ |
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125 | /* |
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126 | * enable an external interrupt, make this interrupt consistent |
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127 | */ |
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128 | RTEMS_INLINE_ROUTINE void |
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129 | enable_ext_irq( uint32_t mask) |
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130 | { |
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131 | rtems_interrupt_level level; |
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132 | |
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133 | rtems_interrupt_disable(level); |
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134 | set_exier(get_exier() | ((mask)&PPC_EXI_MASK)); |
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135 | rtems_interrupt_enable(level); |
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136 | } |
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137 | |
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138 | /* |
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139 | * disable an external interrupt, make this interrupt consistent |
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140 | */ |
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141 | RTEMS_INLINE_ROUTINE void |
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142 | disable_ext_irq( uint32_t mask) |
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143 | { |
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144 | rtems_interrupt_level level; |
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145 | |
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146 | rtems_interrupt_disable(level); |
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147 | set_exier(get_exier() & ~(mask) & PPC_EXI_MASK); |
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148 | rtems_interrupt_enable(level); |
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149 | } |
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150 | |
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151 | /* |
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152 | * |
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153 | * this function is called, when a external interrupt is present and |
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154 | * enabled but there is no handler installed. It will clear |
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155 | * the corresponding enable bits and call the spurious handler |
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156 | * present in the CPU Configuration Table, if any. |
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157 | * |
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158 | */ |
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159 | void |
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160 | ictrl_spurious_handler(uint32_t spurious_mask, |
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161 | CPU_Interrupt_frame *cpu_frame) |
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162 | { |
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163 | int v; |
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164 | |
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165 | for (v=0; v < PPC_IRQ_EXT_MAX; v++) { |
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166 | if (VEC_TO_EXMSK(v) & spurious_mask) { |
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167 | clr_exisr(VEC_TO_EXMSK(v)); |
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168 | disable_ext_irq(VEC_TO_EXMSK(v)); |
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169 | #if 0 |
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170 | printf("spurious external interrupt: %d at pc 0x%x; disabling\n", |
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171 | vector, cpu_frame->Interrupt.pcoqfront); |
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172 | #endif |
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173 | if (rtems_cpu_configuration_get_spurious_handler()) { |
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174 | rtems_cpu_configuration_get_spurious_handler()(v + PPC_IRQ_EXT_BASE,cpu_frame); |
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175 | } |
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176 | } |
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177 | } |
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178 | } |
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179 | |
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180 | |
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181 | /* |
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182 | * ISR Handler: this is called from the primary exception dispatcher |
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183 | */ |
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184 | |
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185 | void |
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186 | ictrl_isr(rtems_vector_number vector,CPU_Interrupt_frame *cpu_frame) |
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187 | { |
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188 | uint32_t istat, |
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189 | mask, |
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190 | global_vec; |
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191 | int exvec; |
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192 | rtems_isr_entry handler; |
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193 | |
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194 | istat = get_exisr() & get_exier() & PPC_EXI_MASK; |
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195 | |
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196 | /* FIXME: this may be speeded up using cntlzw instruction */ |
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197 | for (exvec = 0;exvec < PPC_IRQ_EXT_MAX;exvec++) { |
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198 | mask = VEC_TO_EXMSK(exvec); |
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199 | if (0 != (istat & mask)) { |
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200 | /*clr_exisr(mask); too early to ack*/ |
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201 | handler = ictrl_vector_table[exvec]; |
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202 | if (handler) { |
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203 | istat &= ~mask; |
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204 | global_vec = exvec + PPC_IRQ_EXT_BASE; |
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205 | (handler)(global_vec); |
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206 | } |
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207 | clr_exisr(mask);/* now we can ack*/ |
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208 | } |
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209 | } |
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210 | if (istat != 0) { /* anything left? then we have a spurious interrupt */ |
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211 | ictrl_spurious_handler(istat,cpu_frame); |
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212 | } |
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213 | } |
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214 | |
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215 | /* |
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216 | * |
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217 | * the following functions form the user interface |
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218 | * |
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219 | */ |
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220 | |
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221 | /* |
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222 | * |
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223 | * install a user vector for one of the external interrupt sources |
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224 | * |
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225 | */ |
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226 | rtems_status_code |
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227 | ictrl_set_vector(rtems_isr_entry new_handler, |
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228 | uint32_t vector, |
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229 | rtems_isr_entry *old_handler |
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230 | ) |
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231 | { |
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232 | /* |
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233 | * We put the actual user ISR address in 'ictrl_vector_table'. This will |
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234 | * be used by the _ictrl_isr so the user gets control. |
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235 | */ |
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236 | |
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237 | /* check for valid vector range */ |
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238 | if ((vector >= PPC_IRQ_EXT_BASE) && |
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239 | (vector < PPC_IRQ_EXT_BASE + PPC_IRQ_EXT_MAX)) { |
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240 | /* return old handler entry */ |
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241 | *old_handler = ictrl_vector_table[vector - PPC_IRQ_EXT_BASE]; |
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242 | |
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243 | if (new_handler != NULL) { |
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244 | /* store handler function... */ |
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245 | ictrl_vector_table[vector - PPC_IRQ_EXT_BASE] = new_handler; |
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246 | /* then enable it in EXIER register */ |
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247 | enable_ext_irq(VEC_TO_EXMSK(vector - PPC_IRQ_EXT_BASE)); |
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248 | } |
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249 | else { /* new_handler == NULL */ |
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250 | /* then disable it in EXIER register */ |
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251 | disable_ext_irq(VEC_TO_EXMSK(vector - PPC_IRQ_EXT_BASE)); |
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252 | ictrl_vector_table[vector - PPC_IRQ_EXT_BASE] = NULL; |
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253 | } |
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254 | return RTEMS_SUCCESSFUL; |
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255 | } |
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256 | else { |
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257 | return RTEMS_INVALID_NUMBER; |
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258 | } |
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259 | } |
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260 | |
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261 | /* |
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262 | * Called via atexit() |
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263 | * deactivate the interrupt controller |
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264 | */ |
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265 | |
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266 | void |
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267 | ictrl_exit(void) |
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268 | { |
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269 | /* mark them all unused */ |
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270 | disable_ext_irq(~0); |
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271 | clr_exisr(~0); |
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272 | |
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273 | } |
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274 | |
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275 | /* |
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276 | * activate the interrupt controller |
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277 | */ |
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278 | |
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279 | rtems_status_code |
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280 | ictrl_init(void) |
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281 | { |
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282 | proc_ptr dummy; |
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283 | |
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284 | /* mark them all unused */ |
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285 | disable_ext_irq(~0); |
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286 | clr_exisr(~0); |
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287 | |
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288 | /* install the external interrupt handler */ |
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289 | _CPU_ISR_install_vector(PPC_IRQ_EXTERNAL, |
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290 | ictrl_isr, |
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291 | &dummy); |
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292 | atexit(ictrl_exit); |
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293 | return RTEMS_SUCCESSFUL; |
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294 | } |
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