1 | |
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2 | /* |
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3 | |
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4 | Constants for manipulating system registers of PPC 405EX in C |
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5 | |
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6 | Michael Hamel ADInstruments May 2008 |
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7 | |
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8 | */ |
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9 | |
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10 | #include <libcpu/powerpc-utility.h> |
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11 | /* Indirect access to Clocking/Power-On registers */ |
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12 | #define CPR0_DCR_BASE 0x0C |
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13 | #define cprcfga (CPR0_DCR_BASE+0x0) |
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14 | #define cprcfgd (CPR0_DCR_BASE+0x1) |
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15 | |
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16 | #define mtcpr(reg, d) \ |
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17 | do { \ |
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18 | PPC_SET_DEVICE_CONTROL_REGISTER(cprcfga,reg); \ |
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19 | PPC_SET_DEVICE_CONTROL_REGISTER(cprcfgd,d); \ |
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20 | } while (0) |
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21 | |
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22 | #define mfcpr(reg, d) \ |
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23 | do { \ |
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24 | PPC_SET_DEVICE_CONTROL_REGISTER(cprcfga,reg); \ |
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25 | d = PPC_DEVICE_CONTROL_REGISTER(cprcfgd); \ |
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26 | } while (0) |
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27 | |
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28 | |
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29 | /* Indirect access to System registers */ |
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30 | #define SDR_DCR_BASE 0x0E |
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31 | #define sdrcfga (SDR_DCR_BASE+0x0) |
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32 | #define sdrcfgd (SDR_DCR_BASE+0x1) |
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33 | |
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34 | #define mtsdr(reg, d) \ |
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35 | do { \ |
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36 | PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfga,reg); \ |
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37 | PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfgd,d); \ |
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38 | } while (0) |
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39 | |
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40 | #define mfsdr(reg, d) \ |
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41 | do { \ |
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42 | PPC_SET_DEVICE_CONTROL_REGISTER(sdrcfga,reg); \ |
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43 | d = PPC_DEVICE_CONTROL_REGISTER(sdrcfgd); \ |
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44 | } while (0) |
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45 | |
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46 | /* Indirect access to EBC registers */ |
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47 | #define EBC_DCR_BASE 0x12 |
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48 | #define ebccfga (EBC_DCR_BASE+0x0) |
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49 | #define ebccfgd (EBC_DCR_BASE+0x1) |
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50 | |
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51 | #define mtebc(reg, d) \ |
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52 | do { \ |
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53 | PPC_SET_DEVICE_CONTROL_REGISTER(ebccfga,reg); \ |
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54 | PPC_SET_DEVICE_CONTROL_REGISTER(ebccfgd,d); \ |
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55 | } while (0) |
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56 | |
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57 | #define mfebc(reg, d) \ |
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58 | do { \ |
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59 | PPC_SET_DEVICE_CONTROL_REGISTER(ebccfga,reg); \ |
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60 | d = PPC_DEVICE_CONTROL_REGISTER(ebccfgd); \ |
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61 | } while (0) |
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62 | |
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63 | /* EBC DCRs */ |
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64 | enum { |
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65 | /* |
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66 | EBC0_B0CR = 0, |
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67 | EBC0_B1CR = 1, |
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68 | EBC0_B2CR = 2, |
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69 | EBC0_B3CR = 3, |
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70 | EBC0_B0AP = 0x10, |
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71 | EBC0_B1AP = 0x11, |
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72 | EBC0_B2AP = 0x12, |
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73 | EBC0_B3AP = 0x13, |
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74 | EBC0_BEAR = 0x20, |
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75 | EBC0_BESR = 0x21, |
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76 | EBC0_CFG = 0x23, |
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77 | */ |
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78 | EBC0_CID = 0x24 |
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79 | }; |
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80 | |
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81 | enum { |
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82 | SDR0_UART0 = 0x120, |
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83 | SDR0_UART1 = 0x121, |
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84 | SDR0_C405 = 0x180, |
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85 | SDR0_MALTBL = 0x280, |
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86 | SDR0_MALRBL = 0x2A0, |
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87 | SDR0_MALTBS = 0x2C0, |
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88 | SDR0_MALRBS = 0x2E0 |
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89 | }; |
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90 | |
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91 | |
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92 | /* Memory-mapped registers */ |
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93 | |
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94 | |
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95 | /*======================= Ethernet =================== */ |
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96 | |
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97 | |
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98 | typedef struct EthernetRegisters_EX { |
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99 | uint32_t mode0; |
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100 | uint32_t mode1; |
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101 | uint32_t xmtMode0; |
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102 | uint32_t xmtMode1; |
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103 | uint32_t rcvMode; |
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104 | uint32_t intStatus; |
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105 | uint32_t intEnable; |
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106 | uint32_t addrHi; |
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107 | uint32_t addrLo; |
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108 | uint32_t VLANTPID; |
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109 | uint32_t VLANTCI; |
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110 | uint32_t pauseTimer; |
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111 | uint32_t multicastAddr[2]; |
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112 | uint32_t multicastMask[2]; |
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113 | uint32_t unused[4]; |
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114 | uint32_t lastSrcLo; |
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115 | uint32_t lastSrcHi; |
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116 | uint32_t IPGap; |
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117 | uint32_t STAcontrol; |
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118 | uint32_t xmtReqThreshold; |
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119 | uint32_t rcvWatermark; |
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120 | uint32_t bytesXmtd; |
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121 | uint32_t bytesRcvd; |
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122 | uint32_t unused2; |
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123 | uint32_t revID; |
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124 | uint32_t unused3[2]; |
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125 | uint32_t indivHash[8]; |
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126 | uint32_t groupHash[8]; |
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127 | uint32_t xmtPause; |
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128 | } EthernetRegisters_EX; |
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129 | |
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130 | enum { |
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131 | EMAC0Address = 0xEF600900, |
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132 | EMAC1Address = 0xEF600A00 |
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133 | }; |
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134 | |
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135 | |
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136 | typedef struct GPIORegisters { |
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137 | uint32_t OR; |
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138 | uint32_t GPIO_TCR; /* Note that TCR is defined as a DCR name */ |
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139 | uint32_t OSRL; |
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140 | uint32_t OSRH; |
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141 | uint32_t TSRL; |
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142 | uint32_t TSRH; |
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143 | uint32_t ODR; |
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144 | uint32_t IR; |
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145 | uint32_t RR1; |
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146 | uint32_t RR2; |
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147 | uint32_t RR3; |
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148 | uint32_t unknown; |
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149 | uint32_t ISR1L; |
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150 | uint32_t ISR1H; |
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151 | uint32_t ISR2L; |
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152 | uint32_t ISR2H; |
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153 | uint32_t ISR3L; |
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154 | uint32_t ISR3H; |
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155 | } GPIORegisters; |
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156 | |
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157 | enum { GPIOAddress = 0xEF600800 }; |
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158 | |
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