1 | /* ictrl.h |
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2 | * |
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3 | * This file contains definitions and declarations for the |
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4 | * PowerPC 403 CPU built-in external interrupt controller |
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5 | * |
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6 | * |
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7 | * Author: Thomas Doerfler <td@imd.m.isar.de> |
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8 | * |
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9 | * COPYRIGHT (c) 1998 by IMD, Puchheim, Germany |
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10 | * |
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11 | * To anyone who acknowledges that this file is provided "AS IS" |
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12 | * without any express or implied warranty: |
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13 | * permission to use, copy, modify, and distribute this file |
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14 | * for any purpose is hereby granted without fee, provided that |
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15 | * the above copyright notice and this notice appears in all |
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16 | * copies, and that the name of IMD not be used in |
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17 | * advertising or publicity pertaining to distribution of the |
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18 | * software without specific, written prior permission. |
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19 | * IMD makes no representations about the suitability |
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20 | * of this software for any purpose. |
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21 | * |
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22 | * Modifications for PPC405GP by Dennis Ehlin |
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23 | * |
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24 | */ |
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25 | |
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26 | |
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27 | #ifndef _ICTRL_H |
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28 | #define _ICTRL_H |
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29 | |
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30 | #include <rtems.h> |
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31 | #include <rtems/system.h> |
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32 | #include <rtems/score/isr.h> |
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33 | #ifdef __cplusplus |
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34 | extern "C" { |
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35 | #endif |
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36 | |
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37 | /* |
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38 | * definitions for second level IRQ handler support |
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39 | * External Interrupts via EXTERNAL/EISR |
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40 | */ |
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41 | #define PPC_IRQ_EXT_BASE (PPC_IRQ_LAST+1) |
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42 | |
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43 | /* mask for external interrupt status in EXIER/EXISR register */ |
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44 | /* note: critical interrupt is in these registers aswell */ |
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45 | #ifndef ppc405 |
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46 | #define PPC_EXI_MASK 0x0FFFFFFF |
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47 | #else /* ppc405 */ |
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48 | #define PPC_EXI_MASK 0xFFFFFFFF |
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49 | #endif /* ppc405 */ |
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50 | |
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51 | #ifndef ppc405 |
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52 | #define PPC_IRQ_EXT_SPIR (PPC_IRQ_EXT_BASE+4) |
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53 | #define PPC_IRQ_EXT_SPIT (PPC_IRQ_EXT_BASE+5) |
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54 | #else /* ppc405 */ |
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55 | #define PPC_IRQ_EXT_UART0 (PPC_IRQ_EXT_BASE+0) |
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56 | #define PPC_IRQ_EXT_UART1 (PPC_IRQ_EXT_BASE+1) |
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57 | #endif /* ppc405 */ |
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58 | #define PPC_IRQ_EXT_JTAGR (PPC_IRQ_EXT_BASE+6) |
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59 | #define PPC_IRQ_EXT_JTAGT (PPC_IRQ_EXT_BASE+7) |
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60 | #define PPC_IRQ_EXT_DMA0 (PPC_IRQ_EXT_BASE+8) |
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61 | #define PPC_IRQ_EXT_DMA1 (PPC_IRQ_EXT_BASE+9) |
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62 | #define PPC_IRQ_EXT_DMA2 (PPC_IRQ_EXT_BASE+10) |
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63 | #define PPC_IRQ_EXT_DMA3 (PPC_IRQ_EXT_BASE+11) |
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64 | #define PPC_IRQ_EXT_0 (PPC_IRQ_EXT_BASE+27) |
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65 | #define PPC_IRQ_EXT_1 (PPC_IRQ_EXT_BASE+28) |
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66 | #define PPC_IRQ_EXT_2 (PPC_IRQ_EXT_BASE+29) |
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67 | #define PPC_IRQ_EXT_3 (PPC_IRQ_EXT_BASE+30) |
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68 | #define PPC_IRQ_EXT_4 (PPC_IRQ_EXT_BASE+31) |
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69 | |
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70 | #define PPC_IRQ_EXT_MAX (32) |
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71 | |
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72 | #define VEC_TO_EXMSK(v) (0x80000000 >> (v)) |
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73 | |
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74 | /* |
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75 | * |
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76 | * install a user vector for one of the external interrupt sources |
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77 | * |
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78 | */ |
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79 | rtems_status_code |
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80 | ictrl_set_vector(rtems_isr_entry new_handler, |
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81 | uint32_t vector, |
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82 | rtems_isr_entry *old_handler |
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83 | ); |
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84 | /* |
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85 | * activate the interrupt controller |
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86 | */ |
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87 | rtems_status_code |
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88 | ictrl_init(void); |
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89 | |
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90 | #ifdef __cplusplus |
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91 | } |
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92 | #endif |
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93 | |
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94 | #endif /* _ICTRL_H */ |
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95 | /* end of include file */ |
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