[e9ae97fb] | 1 | /* |
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| 2 | * This file contains the PowerPC 405GP console IO package. |
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| 3 | * |
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| 4 | * Author: Thomas Doerfler <td@imd.m.isar.de> |
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| 5 | * IMD Ingenieurbuero fuer Microcomputertechnik |
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| 6 | * |
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| 7 | * COPYRIGHT (c) 1998 by IMD |
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| 8 | * |
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| 9 | * Changes from IMD are covered by the original distributions terms. |
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| 10 | * changes include interrupt support and termios support |
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| 11 | * for backward compatibility, the original polled driver has been |
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| 12 | * renamed to console.c.polled |
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| 13 | * |
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| 14 | * This file has been initially created (polled version) by |
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| 15 | * |
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| 16 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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| 17 | * |
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| 18 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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| 19 | * |
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| 20 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 21 | * without any express or implied warranty: |
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| 22 | * permission to use, copy, modify, and distribute this file |
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| 23 | * for any purpose is hereby granted without fee, provided that |
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| 24 | * the above copyright notice and this notice appears in all |
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| 25 | * copies, and that the name of i-cubed limited not be used in |
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| 26 | * advertising or publicity pertaining to distribution of the |
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| 27 | * software without specific, written prior permission. |
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| 28 | * i-cubed limited makes no representations about the suitability |
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| 29 | * of this software for any purpose. |
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| 30 | * |
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| 31 | * Modifications for spooling (interrupt driven) console driver |
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| 32 | * by Thomas Doerfler <td@imd.m.isar.de> |
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| 33 | * for these modifications: |
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| 34 | * COPYRIGHT (c) 1997 by IMD, Puchheim, Germany. |
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| 35 | * |
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| 36 | * |
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| 37 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 38 | * without any express or implied warranty: |
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| 39 | * permission to use, copy, modify, and distribute this file |
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| 40 | * for any purpose is hereby granted without fee, provided that |
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| 41 | * the above copyright notice and this notice appears in all |
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| 42 | * copies. IMD makes no representations about the suitability |
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| 43 | * of this software for any purpose. |
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| 44 | * |
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| 45 | * Derived from c/src/lib/libbsp/no_cpu/no_bsp/console/console.c: |
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| 46 | * |
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| 47 | * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. |
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| 48 | * On-Line Applications Research Corporation (OAR). |
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| 49 | * All rights assigned to U.S. Government, 1994. |
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| 50 | * |
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| 51 | * This material may be reproduced by or for the U.S. Government pursuant |
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| 52 | * to the copyright license under the clause at DFARS 252.227-7013. This |
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| 53 | * notice must appear in all copies of this file and its derivatives. |
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| 54 | * |
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| 55 | * Modifications for PPC405GP by Dennis Ehlin |
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| 56 | * |
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| 57 | * console405.c,v 1.4 1995/12/05 19:23:02 joel Exp |
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| 58 | */ |
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| 59 | |
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| 60 | #define NO_BSP_INIT |
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| 61 | |
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| 62 | #include <rtems.h> |
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| 63 | #include <rtems/libio.h> |
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| 64 | #include "../ictrl/ictrl.h" |
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| 65 | #include <stdlib.h> /* for atexit() */ |
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| 66 | |
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| 67 | |
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| 68 | |
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| 69 | struct async { |
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| 70 | /*---------------------------------------------------------------------------+ |
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| 71 | | Data Register. |
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| 72 | +---------------------------------------------------------------------------*/ |
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| 73 | unsigned char RBR; /* 0x00 */ |
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| 74 | #define THR RBR |
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| 75 | /*---------------------------------------------------------------------------+ |
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| 76 | | Interrupt registers |
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| 77 | +---------------------------------------------------------------------------*/ |
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| 78 | unsigned char IER; /* 0x01 */ |
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| 79 | #define IER_RCV 0x01 |
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| 80 | #define IER_XMT 0x02 |
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| 81 | #define IER_LS 0x04 |
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| 82 | #define IER_MS 0x08 |
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| 83 | |
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| 84 | unsigned char ISR; /* 0x02 */ |
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| 85 | #define ISR_MS 0x00 |
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| 86 | #define ISR_nIP 0x01 |
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| 87 | #define ISR_Tx 0x02 |
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| 88 | #define ISR_Rx 0x04 |
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| 89 | #define ISR_LS 0x06 |
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| 90 | #define ISR_RxTO 0x0C |
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| 91 | #define ISR_64BFIFO 0x20 |
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| 92 | #define ISR_FIFOworks 0x40 |
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| 93 | #define ISR_FIFOen 0x80 |
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| 94 | |
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| 95 | /*---------------------------------------------------------------------------+ |
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| 96 | | FIFO Control registers |
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| 97 | +---------------------------------------------------------------------------*/ |
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| 98 | #define FCR ISR |
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| 99 | #define FCR_FE 0x01 /* FIFO enable */ |
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| 100 | #define FCR_CRF 0x02 /* Clear receive FIFO */ |
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| 101 | #define FCR_CTF 0x04 /* Clear transmit FIFO */ |
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| 102 | #define FCR_DMA 0x08 /* DMA mode select */ |
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| 103 | #define FCR_F64 0x20 /* Enable 64 byte fifo (16750+) */ |
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| 104 | #define FCR_RT14 0xC0 /* Set Rx trigger at 14 */ |
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| 105 | #define FCR_RT8 0x80 /* Set Rx trigger at 8 */ |
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| 106 | #define FCR_RT4 0x40 /* Set Rx trigger at 4 */ |
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| 107 | #define FCR_RT1 0x00 /* Set Rx trigger at 1 */ |
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| 108 | |
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| 109 | /*---------------------------------------------------------------------------+ |
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| 110 | | Baud rate divisor registers |
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| 111 | +---------------------------------------------------------------------------*/ |
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| 112 | #define DLL RBR |
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| 113 | #define DLM IER |
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| 114 | |
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| 115 | /*---------------------------------------------------------------------------+ |
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| 116 | | Alternate function registers |
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| 117 | +---------------------------------------------------------------------------*/ |
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| 118 | #define AFR ISR |
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| 119 | |
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| 120 | /*---------------------------------------------------------------------------+ |
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| 121 | | Line control Register. |
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| 122 | +---------------------------------------------------------------------------*/ |
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| 123 | unsigned char LCR; /* 0x03 */ |
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| 124 | #define LCR_WL5 0x00 /* Word length 5 */ |
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| 125 | #define LCR_WL6 0x01 /* Word length 6 */ |
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| 126 | #define LCR_WL7 0x02 /* Word length 7 */ |
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| 127 | #define LCR_WL8 0x03 /* Word length 8 */ |
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| 128 | |
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| 129 | #define LCR_SB1 0x00 /* 1 stop bits */ |
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| 130 | #define LCR_SB1_5 0x04 /* 1.5 stop bits , only valid with 5 bit words*/ |
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| 131 | #define LCR_SB1_5 0x04 /* 2 stop bits */ |
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| 132 | |
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| 133 | #define LCR_PN 0x00 /* Parity NONE */ |
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| 134 | #define LCR_PE 0x0C /* Parity EVEN */ |
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| 135 | #define LCR_PO 0x08 /* Parity ODD */ |
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| 136 | #define LCR_PM 0x28 /* Forced "mark" parity */ |
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| 137 | #define LCR_PS 0x38 /* Forced "space" parity */ |
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| 138 | |
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| 139 | #define LCR_DL 0x80 /* Enable baudrate latch */ |
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| 140 | |
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| 141 | /*---------------------------------------------------------------------------+ |
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| 142 | | Modem control Register. |
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| 143 | +---------------------------------------------------------------------------*/ |
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| 144 | unsigned char MCR; /* 0x04 */ |
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| 145 | #define MCR_DTR 0x01 |
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| 146 | #define MCR_RTS 0x02 |
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| 147 | #define MCR_INT 0x08 /* Enable interrupts */ |
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| 148 | #define MCR_LOOP 0x10 /* Loopback mode */ |
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| 149 | |
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| 150 | /*---------------------------------------------------------------------------+ |
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| 151 | | Line status Register. |
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| 152 | +---------------------------------------------------------------------------*/ |
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| 153 | unsigned char LSR; /* 0x05 */ |
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| 154 | #define LSR_RSR 0x01 |
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| 155 | #define LSR_OE 0x02 |
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| 156 | #define LSR_PE 0x04 |
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| 157 | #define LSR_FE 0x08 |
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| 158 | #define LSR_BI 0x10 |
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| 159 | #define LSR_THE 0x20 |
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| 160 | #define LSR_TEMT 0x40 |
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| 161 | #define LSR_FIE 0x80 |
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| 162 | |
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| 163 | /*---------------------------------------------------------------------------+ |
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| 164 | | Modem status Register. |
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| 165 | +---------------------------------------------------------------------------*/ |
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| 166 | unsigned char MSR; /* 0x06 */ |
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| 167 | #define MSR_DCTS 0x01 |
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| 168 | #define MSR_DDSR 0x02 |
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| 169 | #define MSR_TERI 0x04 |
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| 170 | #define MSR_DDCD 0x08 |
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| 171 | #define MSR_CTS 0x10 |
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| 172 | #define MSR_DSR 0x20 |
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| 173 | #define MSR_RI 0x40 |
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| 174 | #define MSR_CD 0x80 |
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| 175 | |
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| 176 | /*---------------------------------------------------------------------------+ |
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| 177 | | Scratch pad Register. |
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| 178 | +---------------------------------------------------------------------------*/ |
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| 179 | unsigned char SCR; /* 0x07 */ |
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| 180 | }; |
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| 181 | |
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| 182 | |
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| 183 | #define USE_UART 0 /* 0=UART0 1=UART1 */ |
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| 184 | #define UART_INTERNAL_CLOCK_DIVISOR 16 |
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| 185 | |
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| 186 | typedef volatile struct async *pasync; |
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| 187 | static const pasync port = (pasync)(0xEF600300 + (USE_UART*0x100)); /* 0xEF600300 - port A, 0xEF600400 - port B */ |
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| 188 | |
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| 189 | static void *spittyp; /* handle for termios */ |
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| 190 | int ppc403_spi_interrupt = 0; /* do not use interrupts... */ |
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| 191 | |
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| 192 | |
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| 193 | int round(double x) |
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| 194 | { |
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| 195 | return (int)((int)((x-(int)x)*1000)>500 ? x+1 : x); |
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| 196 | } |
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| 197 | |
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| 198 | void |
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| 199 | spiBaudSet(unsigned32 baudrate) |
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| 200 | { |
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| 201 | unsigned32 tmp; |
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| 202 | |
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| 203 | tmp = round( (double)rtems_cpu_configuration_get_serial_per_sec() / (baudrate * 16) ); |
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| 204 | |
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| 205 | port->LCR = port->LCR | LCR_DL; |
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| 206 | |
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| 207 | port->DLL = tmp & 0xff; |
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| 208 | port->DLM = tmp >> 8; |
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| 209 | |
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| 210 | port->LCR = port->LCR & ~LCR_DL; |
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| 211 | } |
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| 212 | /* |
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| 213 | * Hardware-dependent portion of tcsetattr(). |
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| 214 | */ |
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| 215 | static int |
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| 216 | spiSetAttributes (int minor, const struct termios *t) |
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| 217 | { |
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| 218 | int baud; |
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| 219 | |
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| 220 | /* FIXME: check c_cflag & CRTSCTS for hardware flowcontrol */ |
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| 221 | /* FIXME: check and IMPLEMENT XON/XOFF */ |
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| 222 | switch (t->c_cflag & CBAUD) { |
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| 223 | default: baud = -1; break; |
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| 224 | case B50: baud = 50; break; |
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| 225 | case B75: baud = 75; break; |
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| 226 | case B110: baud = 110; break; |
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| 227 | case B134: baud = 134; break; |
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| 228 | case B150: baud = 150; break; |
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| 229 | case B200: baud = 200; break; |
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| 230 | case B300: baud = 300; break; |
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| 231 | case B600: baud = 600; break; |
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| 232 | case B1200: baud = 1200; break; |
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| 233 | case B1800: baud = 1800; break; |
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| 234 | case B2400: baud = 2400; break; |
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| 235 | case B4800: baud = 4800; break; |
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| 236 | case B9600: baud = 9600; break; |
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| 237 | case B19200: baud = 19200; break; |
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| 238 | case B38400: baud = 38400; break; |
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| 239 | case B57600: baud = 57600; break; |
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| 240 | case B115200: baud = 115200; break; |
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| 241 | case B230400: baud = 230400; break; |
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| 242 | case B460800: baud = 460800; break; |
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| 243 | } |
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| 244 | if (baud > 0) { |
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| 245 | spiBaudSet(baud); |
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| 246 | } |
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| 247 | return 0; |
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| 248 | } |
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| 249 | |
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| 250 | static int |
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| 251 | spiPollRead (int minor) |
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| 252 | { |
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| 253 | |
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| 254 | /* Wait for character */ |
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| 255 | while ((port->LSR & LSR_RSR)==0);; |
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| 256 | |
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| 257 | return port->RBR; |
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| 258 | } |
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| 259 | |
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| 260 | |
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| 261 | static int |
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| 262 | spiPollWrite(int minor,const char *buf,int len) |
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| 263 | { |
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| 264 | |
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| 265 | while (len-- > 0) { |
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| 266 | while (!(port->LSR & LSR_THE));; |
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| 267 | port->THR = *buf++; |
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| 268 | } |
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| 269 | return 0; |
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| 270 | } |
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| 271 | |
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| 272 | /* |
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| 273 | * enable/disable RTS line to start/stop remote transmitter |
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| 274 | */ |
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| 275 | static int |
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| 276 | spiStartRemoteTx (int minor) |
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| 277 | { |
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| 278 | /* Not implemented ! |
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| 279 | rtems_interrupt_level level; |
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| 280 | |
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| 281 | rtems_interrupt_disable (level); |
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| 282 | port->SPCTL |= CRRts; activate RTS |
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| 283 | rtems_interrupt_enable (level); |
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| 284 | */ |
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| 285 | return 0; |
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| 286 | } |
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| 287 | |
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| 288 | static int |
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| 289 | spiStopRemoteTx (int minor) |
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| 290 | { |
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| 291 | /* Not implemented ! |
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| 292 | rtems_interrupt_level level; |
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| 293 | |
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| 294 | rtems_interrupt_disable (level); |
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| 295 | port->SPCTL &= ~CRRts; deactivate RTS |
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| 296 | rtems_interrupt_enable (level); |
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| 297 | */ |
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| 298 | return 0; |
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| 299 | } |
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| 300 | |
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| 301 | static int InterruptWrite (int minor, const char *buf, int len) |
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| 302 | { |
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| 303 | port->IER |= IER_XMT; /* always enable tx interrupt */ |
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| 304 | port->THR = *buf; /* write char to send */ |
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| 305 | return 0; |
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| 306 | } |
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| 307 | |
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| 308 | static rtems_isr serial_ISR(rtems_vector_number v) |
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| 309 | { |
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| 310 | unsigned char _isr; |
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| 311 | char ch; |
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| 312 | int res; |
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| 313 | |
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| 314 | _isr=port->ISR & 0x0E; |
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| 315 | |
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| 316 | if ((_isr == ISR_Rx) || (_isr==ISR_RxTO)) { |
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| 317 | ch = port->RBR; |
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| 318 | rtems_termios_enqueue_raw_characters (spittyp,&ch,1); |
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| 319 | } |
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| 320 | |
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| 321 | if (_isr == ISR_Tx) { |
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| 322 | res = rtems_termios_dequeue_characters (spittyp,1); |
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| 323 | if (res==0) { |
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| 324 | port->IER &= ~IER_XMT; |
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| 325 | } |
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| 326 | |
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| 327 | } |
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| 328 | } |
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| 329 | |
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| 330 | |
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| 331 | /* |
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| 332 | * |
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| 333 | * deinit SPI |
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| 334 | * |
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| 335 | */ |
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| 336 | void |
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| 337 | spiDeInit(void) |
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| 338 | { |
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| 339 | /* |
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| 340 | * disable interrupts for serial port |
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| 341 | * set it to state to work with polling boot monitor, if any... |
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| 342 | */ |
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| 343 | |
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| 344 | |
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| 345 | /* set up baud rate to original state */ |
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| 346 | spiBaudSet(rtems_cpu_configuration_get_serial_rate()); |
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| 347 | |
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| 348 | port->IER = 0; |
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| 349 | |
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| 350 | } |
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| 351 | |
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| 352 | /* |
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| 353 | * |
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| 354 | * init SPI |
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| 355 | * |
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| 356 | */ |
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| 357 | rtems_status_code |
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| 358 | spiInitialize(void) |
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| 359 | { |
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| 360 | register unsigned tmp; |
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| 361 | rtems_isr_entry previous_isr; /* this is a dummy */ |
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| 362 | unsigned char _ier; |
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| 363 | |
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| 364 | /* |
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| 365 | * Initialise the serial port |
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| 366 | */ |
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| 367 | |
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| 368 | /* |
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| 369 | * Select clock source and set uart internal clock divisor |
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| 370 | */ |
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| 371 | |
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| 372 | asm volatile ("mfdcr %0, 0x0b1" : "=r" (tmp)); /* CPC_CR0 0x0b1 */ |
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| 373 | |
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| 374 | /* UART0 bit 24 0x80, UART1 bit 25 0x40 */ |
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| 375 | tmp |= (rtems_cpu_configuration_get_serial_external_clock() ? (USE_UART ? 0x40 : 0x80) : 0); |
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| 376 | |
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| 377 | tmp |= (rtems_cpu_configuration_get_serial_external_clock() ? 0: ((UART_INTERNAL_CLOCK_DIVISOR -1) << 1)); |
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| 378 | |
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| 379 | asm volatile ("mtdcr 0x0b1, %0" : "=r" (tmp) : "0" (tmp)); /* CPC_CR0 0x0b1*/ |
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| 380 | |
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| 381 | /* Disable port interrupts while changing hardware */ |
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| 382 | _ier = port->IER; |
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| 383 | port->IER = 0; |
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| 384 | |
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| 385 | /* set up port control: 8 bit,1 stop,no parity */ |
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| 386 | port->LCR = LCR_WL8 | LCR_SB1 | LCR_PN; |
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| 387 | |
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| 388 | /* set up baud rate */ |
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| 389 | spiBaudSet(rtems_cpu_configuration_get_serial_rate()); |
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| 390 | |
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| 391 | if (ppc403_spi_interrupt) { |
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| 392 | |
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| 393 | /* add rx/tx isr to vector table */ |
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| 394 | if (USE_UART==0) |
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| 395 | ictrl_set_vector(serial_ISR,PPC_IRQ_EXT_UART0,&previous_isr); |
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| 396 | else |
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| 397 | ictrl_set_vector(serial_ISR,PPC_IRQ_EXT_UART1,&previous_isr); |
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| 398 | |
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| 399 | /* Enable and clear FIFO */ |
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| 400 | port->FCR = FCR_FE | FCR_CRF | FCR_CTF | FCR_RT8; |
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| 401 | |
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| 402 | /* Enable recive interrupts, don't enable TxInt yet */ |
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| 403 | port->IER=IER_RCV; |
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| 404 | } |
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| 405 | else { |
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| 406 | port->IER=_ier; |
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| 407 | } |
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| 408 | |
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| 409 | atexit(spiDeInit); |
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| 410 | |
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| 411 | return RTEMS_SUCCESSFUL; |
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| 412 | } |
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| 413 | |
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| 414 | /* |
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| 415 | *************** |
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| 416 | * BOILERPLATE * |
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| 417 | *************** |
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| 418 | */ |
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| 419 | |
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| 420 | /* console_initialize |
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| 421 | * |
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| 422 | * This routine initializes the console IO driver. |
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| 423 | * |
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| 424 | * Input parameters: NONE |
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| 425 | * |
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| 426 | * Output parameters: NONE |
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| 427 | * |
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| 428 | * Return values: |
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| 429 | */ |
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| 430 | |
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| 431 | rtems_device_driver console_initialize( |
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| 432 | rtems_device_major_number major, |
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| 433 | rtems_device_minor_number minor, |
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| 434 | void *arg |
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| 435 | ) |
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| 436 | { |
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| 437 | rtems_status_code status; |
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| 438 | |
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| 439 | /* |
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| 440 | * Set up TERMIOS |
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| 441 | */ |
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| 442 | rtems_termios_initialize (); |
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| 443 | |
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| 444 | /* |
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| 445 | * Do device-specific initialization |
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| 446 | */ |
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| 447 | spiInitialize (); |
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| 448 | |
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| 449 | /* |
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| 450 | * Register the device |
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| 451 | */ |
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| 452 | status = rtems_io_register_name ("/dev/console", major, 0); |
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| 453 | if (status != RTEMS_SUCCESSFUL) |
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| 454 | rtems_fatal_error_occurred (status); |
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| 455 | return RTEMS_SUCCESSFUL; |
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| 456 | } |
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| 457 | |
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| 458 | |
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| 459 | /* |
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| 460 | * Open entry point |
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| 461 | */ |
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| 462 | |
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| 463 | rtems_device_driver console_open( |
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| 464 | rtems_device_major_number major, |
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| 465 | rtems_device_minor_number minor, |
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| 466 | void * arg |
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| 467 | ) |
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| 468 | { |
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| 469 | rtems_status_code sc; |
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| 470 | static const rtems_termios_callbacks intrCallbacks = { |
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| 471 | NULL, /* firstOpen */ |
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| 472 | NULL, /* lastClose */ |
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| 473 | NULL, /* pollRead */ |
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| 474 | InterruptWrite, /* write */ |
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| 475 | spiSetAttributes, /* setAttributes */ |
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| 476 | spiStopRemoteTx, /* stopRemoteTx */ |
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| 477 | spiStartRemoteTx, /* startRemoteTx */ |
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| 478 | 1 /* outputUsesInterrupts */ |
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| 479 | }; |
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| 480 | |
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| 481 | static const rtems_termios_callbacks pollCallbacks = { |
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| 482 | NULL, /* firstOpen */ |
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| 483 | NULL, /* lastClose */ |
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| 484 | spiPollRead, /* pollRead */ |
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| 485 | spiPollWrite, /* write */ |
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| 486 | spiSetAttributes, /* setAttributes */ |
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| 487 | spiStopRemoteTx, /* stopRemoteTx */ |
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| 488 | spiStartRemoteTx, /* startRemoteTx */ |
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| 489 | 0 /* outputUsesInterrupts */ |
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| 490 | }; |
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| 491 | |
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| 492 | if (ppc403_spi_interrupt) { |
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| 493 | rtems_libio_open_close_args_t *args = arg; |
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| 494 | sc = rtems_termios_open (major, minor, arg, &intrCallbacks); |
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| 495 | spittyp = args->iop->data1; |
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| 496 | } |
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| 497 | else { |
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| 498 | sc = rtems_termios_open (major, minor, arg, &pollCallbacks); |
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| 499 | } |
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| 500 | return sc; |
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| 501 | } |
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| 502 | |
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| 503 | /* |
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| 504 | * Close entry point |
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| 505 | */ |
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| 506 | |
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| 507 | rtems_device_driver console_close( |
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| 508 | rtems_device_major_number major, |
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| 509 | rtems_device_minor_number minor, |
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| 510 | void * arg |
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| 511 | ) |
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| 512 | { |
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| 513 | return rtems_termios_close (arg); |
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| 514 | } |
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| 515 | |
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| 516 | /* |
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| 517 | * read bytes from the serial port. We only have stdin. |
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| 518 | */ |
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| 519 | |
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| 520 | rtems_device_driver console_read( |
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| 521 | rtems_device_major_number major, |
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| 522 | rtems_device_minor_number minor, |
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| 523 | void * arg |
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| 524 | ) |
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| 525 | { |
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| 526 | return rtems_termios_read (arg); |
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| 527 | } |
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| 528 | |
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| 529 | /* |
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| 530 | * write bytes to the serial port. Stdout and stderr are the same. |
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| 531 | */ |
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| 532 | |
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| 533 | rtems_device_driver console_write( |
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| 534 | rtems_device_major_number major, |
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| 535 | rtems_device_minor_number minor, |
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| 536 | void * arg |
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| 537 | ) |
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| 538 | { |
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| 539 | return rtems_termios_write (arg); |
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| 540 | } |
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| 541 | |
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| 542 | /* |
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| 543 | * IO Control entry point |
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| 544 | */ |
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| 545 | |
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| 546 | rtems_device_driver console_control( |
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| 547 | rtems_device_major_number major, |
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| 548 | rtems_device_minor_number minor, |
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| 549 | void * arg |
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| 550 | ) |
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| 551 | { |
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| 552 | return rtems_termios_ioctl (arg); |
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| 553 | } |
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| 554 | |
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