1 | /* clock.c |
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2 | * |
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3 | * This routine initializes the interval timer on the |
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4 | * PowerPC 405 CPU. The tick frequency is specified by the bsp. |
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5 | * |
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6 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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7 | * |
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8 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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9 | * |
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10 | * To anyone who acknowledges that this file is provided "AS IS" |
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11 | * without any express or implied warranty: |
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12 | * permission to use, copy, modify, and distribute this file |
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13 | * for any purpose is hereby granted without fee, provided that |
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14 | * the above copyright notice and this notice appears in all |
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15 | * copies, and that the name of i-cubed limited not be used in |
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16 | * advertising or publicity pertaining to distribution of the |
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17 | * software without specific, written prior permission. |
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18 | * i-cubed limited makes no representations about the suitability |
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19 | * of this software for any purpose. |
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20 | * |
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21 | * Derived from c/src/lib/libcpu/hppa1.1/clock/clock.c: |
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22 | * |
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23 | * Modifications for deriving timer clock from cpu system clock by |
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24 | * Thomas Doerfler <td@imd.m.isar.de> |
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25 | * for these modifications: |
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26 | * COPYRIGHT (c) 1997 by IMD, Puchheim, Germany. |
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27 | * |
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28 | * COPYRIGHT (c) 1989-2007. |
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29 | * On-Line Applications Research Corporation (OAR). |
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30 | * |
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31 | * The license and distribution terms for this file may be |
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32 | * found in the file LICENSE in this distribution or at |
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33 | * http://www.rtems.com/license/LICENSE. |
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34 | * |
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35 | * Modifications for PPC405GP by Dennis Ehlin |
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36 | * |
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37 | * Further modifications for PPC405GP/EX by Michael Hamel |
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38 | * |
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39 | * $Id$ |
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40 | */ |
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41 | |
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42 | #include <rtems.h> |
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43 | #include <rtems/clockdrv.h> |
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44 | #include <rtems/libio.h> |
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45 | #include <stdlib.h> /* for atexit() */ |
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46 | #include <rtems/bspIo.h> |
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47 | #include <ppc405common.h> |
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48 | #include <libcpu/cpuIdent.h> |
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49 | #include <bsp/irq.h> |
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50 | |
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51 | |
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52 | |
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53 | /* PPC405GP */ |
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54 | #define CPC0_CR1 0xB2 |
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55 | #define CR1_CETE 0x00800000 |
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56 | |
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57 | /* PPC405EX */ |
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58 | #define SDR0_C405 0x180 |
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59 | #define SDR_CETE 0x02000000 |
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60 | |
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61 | volatile uint32_t Clock_driver_ticks; |
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62 | static uint32_t pit_value, tick_time; |
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63 | |
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64 | void Clock_exit( void ); |
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65 | |
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66 | rtems_isr_entry set_vector( /* returns old vector */ |
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67 | rtems_isr_entry handler, /* isr routine */ |
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68 | rtems_vector_number vector, /* vector number */ |
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69 | int type /* RTEMS or RAW intr */ |
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70 | ); |
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71 | |
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72 | /* Defined in bspstart.c */ |
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73 | extern uint32_t bsp_clicks_per_usec; |
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74 | extern boolean bsp_timer_internal_clock; |
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75 | |
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76 | /* |
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77 | * These are set by clock driver during its init |
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78 | */ |
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79 | |
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80 | rtems_device_major_number rtems_clock_major = ~0; |
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81 | rtems_device_minor_number rtems_clock_minor; |
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82 | |
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83 | /* |
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84 | * ISR Handler |
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85 | */ |
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86 | |
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87 | void Clock_isr(void* handle) |
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88 | { |
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89 | Clock_driver_ticks++; |
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90 | rtems_clock_tick(); |
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91 | } |
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92 | |
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93 | int ClockIsOn(const rtems_irq_connect_data* unused) |
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94 | { |
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95 | return ((mfspr(TCR) & PIE) != 0); |
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96 | } |
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97 | |
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98 | |
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99 | void ClockOff(const rtems_irq_connect_data* unused) |
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100 | { |
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101 | register uint32_t r; |
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102 | |
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103 | r = mfspr(TCR); |
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104 | mtspr(TCR, r & ~(PIE | ARE) ); |
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105 | } |
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106 | |
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107 | void ClockOn(const rtems_irq_connect_data* unused) |
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108 | { |
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109 | uint32_t iocr, r; |
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110 | ppc_cpu_id_t cpu; |
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111 | Clock_driver_ticks = 0; |
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112 | |
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113 | cpu = get_ppc_cpu_type(); |
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114 | if (cpu==PPC_405GP) { |
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115 | iocr = mfdcr(CPC0_CR1); |
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116 | if (bsp_timer_internal_clock) iocr &= ~CR1_CETE ;/* timer clocked from system clock */ |
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117 | else iocr |= CR1_CETE; /* select external timer clock */ |
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118 | mtdcr(CPC0_CR1,iocr); |
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119 | } else if (cpu==PPC_405EX) { |
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120 | mfsdr(SDR0_C405,iocr); |
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121 | if (bsp_timer_internal_clock) iocr &= ~SDR_CETE ;/* timer clocked from system clock */ |
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122 | else iocr |= SDR_CETE; /* select external timer clock */ |
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123 | mtsdr(SDR0_C405,iocr); |
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124 | } else { |
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125 | printk("clock.c:unrecognised CPU"); |
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126 | rtems_fatal_error_occurred(1); |
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127 | } |
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128 | |
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129 | pit_value = rtems_configuration_get_microseconds_per_tick() * bsp_clicks_per_usec; |
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130 | mtspr(PIT,pit_value); |
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131 | |
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132 | tick_time = mfspr(TBL) + pit_value; |
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133 | r = mfspr(TCR); |
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134 | mtspr(TCR, r | PIE | ARE); |
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135 | } |
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136 | |
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137 | |
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138 | |
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139 | void Install_clock(void (*clock_isr)(void *)) |
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140 | { |
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141 | |
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142 | /* |
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143 | * initialize the interval here |
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144 | * First tick is set to right amount of time in the future |
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145 | * Future ticks will be incremented over last value set |
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146 | * in order to provide consistent clicks in the face of |
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147 | * interrupt overhead |
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148 | */ |
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149 | |
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150 | rtems_irq_connect_data clockIrqConnData; |
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151 | |
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152 | Clock_driver_ticks = 0; |
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153 | clockIrqConnData.on = ClockOn; |
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154 | clockIrqConnData.off = ClockOff; |
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155 | clockIrqConnData.isOn = ClockIsOn; |
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156 | clockIrqConnData.name = BSP_PIT; |
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157 | clockIrqConnData.hdl = clock_isr; |
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158 | if ( ! BSP_install_rtems_irq_handler (&clockIrqConnData)) { |
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159 | printk("Unable to connect Clock Irq handler\n"); |
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160 | rtems_fatal_error_occurred(1); |
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161 | } |
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162 | atexit(Clock_exit); |
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163 | } |
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164 | |
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165 | void |
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166 | ReInstall_clock(void (*new_clock_isr)(void *)) |
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167 | { |
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168 | uint32_t isrlevel = 0; |
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169 | rtems_irq_connect_data clockIrqConnData; |
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170 | |
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171 | rtems_interrupt_disable(isrlevel); |
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172 | clockIrqConnData.name = BSP_PIT; |
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173 | if ( ! BSP_get_current_rtems_irq_handler(&clockIrqConnData)) { |
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174 | printk("Unable to stop system clock\n"); |
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175 | rtems_fatal_error_occurred(1); |
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176 | } |
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177 | |
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178 | BSP_remove_rtems_irq_handler (&clockIrqConnData); |
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179 | clockIrqConnData.on = ClockOn; |
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180 | clockIrqConnData.off = ClockOff; |
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181 | clockIrqConnData.isOn = ClockIsOn; |
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182 | clockIrqConnData.name = BSP_PIT; |
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183 | clockIrqConnData.hdl = new_clock_isr; |
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184 | if (!BSP_install_rtems_irq_handler (&clockIrqConnData)) { |
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185 | printk("Unable to connect Clock Irq handler\n"); |
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186 | rtems_fatal_error_occurred(1); |
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187 | } |
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188 | rtems_interrupt_enable(isrlevel); |
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189 | } |
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190 | |
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191 | |
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192 | /* |
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193 | * Called via atexit() |
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194 | * Remove the clock interrupt handler by setting handler to NULL |
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195 | * |
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196 | * This will not work on the 405GP because |
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197 | * when bit's are set in TCR they can only be unset by a reset |
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198 | */ |
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199 | |
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200 | void Clock_exit(void) |
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201 | { |
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202 | rtems_irq_connect_data clockIrqConnData; |
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203 | |
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204 | clockIrqConnData.name = BSP_PIT; |
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205 | if (!BSP_get_current_rtems_irq_handler(&clockIrqConnData)) { |
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206 | printk("Unable to stop system clock\n"); |
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207 | rtems_fatal_error_occurred(1); |
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208 | } |
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209 | BSP_remove_rtems_irq_handler (&clockIrqConnData); |
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210 | } |
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211 | |
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212 | |
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213 | rtems_device_driver Clock_initialize( |
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214 | rtems_device_major_number major, |
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215 | rtems_device_minor_number minor, |
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216 | void *pargp |
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217 | ) |
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218 | { |
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219 | Install_clock( Clock_isr ); |
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220 | |
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221 | /* |
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222 | * make major/minor avail to others such as shared memory driver |
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223 | */ |
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224 | rtems_clock_major = major; |
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225 | rtems_clock_minor = minor; |
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226 | |
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227 | return RTEMS_SUCCESSFUL; |
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228 | } |
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