source: rtems/c/src/lib/libcpu/powerpc/ppc403/clock/clock.c @ f9acc33

4.115
Last change on this file since f9acc33 was f9acc33, checked in by Ralf Corsepius <ralf.corsepius@…>, on 02/11/11 at 09:46:53

2011-02-11 Ralf Corsépius <ralf.corsepius@…>

  • e500/mmu/mmu.c, mpc505/ictrl/ictrl.c, mpc505/timer/timer.c, mpc5xx/ictrl/ictrl.c, mpc5xx/timer/timer.c, mpc6xx/altivec/vec_sup.c, mpc6xx/clock/c_clock.c, mpc6xx/mmu/bat.c, mpc6xx/mmu/bat.h, mpc6xx/mmu/pte121.c, mpc8260/timer/timer.c, mpc8xx/timer/timer.c, new-exceptions/cpu.c, new-exceptions/bspsupport/ppc_exc_initialize.c, ppc403/clock/clock.c, ppc403/console/console.c, ppc403/console/console.c.polled, ppc403/console/console405.c, ppc403/irq/ictrl.c, ppc403/tty_drv/tty_drv.c, rtems/powerpc/cache.h, shared/include/powerpc-utility.h, shared/src/cache.c: Use "asm" instead of "asm" for improved c99-compliance.
  • Property mode set to 100644
File size: 9.2 KB
Line 
1/*  clock.c
2 *
3 *  This routine initializes the interval timer on the
4 *  PowerPC 403 CPU.  The tick frequency is specified by the bsp.
5 *
6 *  Author: Andrew Bray <andy@i-cubed.co.uk>
7 *
8 *  COPYRIGHT (c) 1995 by i-cubed ltd.
9 *
10 *  To anyone who acknowledges that this file is provided "AS IS"
11 *  without any express or implied warranty:
12 *      permission to use, copy, modify, and distribute this file
13 *      for any purpose is hereby granted without fee, provided that
14 *      the above copyright notice and this notice appears in all
15 *      copies, and that the name of i-cubed limited not be used in
16 *      advertising or publicity pertaining to distribution of the
17 *      software without specific, written prior permission.
18 *      i-cubed limited makes no representations about the suitability
19 *      of this software for any purpose.
20 *
21 *  Derived from c/src/lib/libcpu/hppa1.1/clock/clock.c:
22 *
23 *  Modifications for deriving timer clock from cpu system clock by
24 *              Thomas Doerfler <td@imd.m.isar.de>
25 *  for these modifications:
26 *  COPYRIGHT (c) 1997 by IMD, Puchheim, Germany.
27 *
28 *  COPYRIGHT (c) 1989-2007.
29 *  On-Line Applications Research Corporation (OAR).
30 *
31 *  The license and distribution terms for this file may be
32 *  found in the file LICENSE in this distribution or at
33 *  http://www.rtems.com/license/LICENSE.
34 *
35 *  Modifications for PPC405GP by Dennis Ehlin
36 *
37 *  $Id$
38 */
39
40#include <rtems.h>
41#include <rtems/clockdrv.h>
42#include <rtems/libio.h>
43#include <stdlib.h>                     /* for atexit() */
44#include <rtems/bspIo.h>
45#include <rtems/powerpc/powerpc.h>
46
47/*
48 * check, which exception handling code is present
49 */
50
51#include <bsp.h>
52
53#include <bsp/vectors.h>
54#include <bsp/irq.h>
55
56extern uint32_t bsp_clicks_per_usec;
57extern bool bsp_timer_internal_clock;
58
59volatile uint32_t   Clock_driver_ticks;
60static uint32_t   pit_value, tick_time;
61static bool auto_restart;
62
63void Clock_exit( void );
64
65rtems_isr_entry set_vector(                    /* returns old vector */
66  rtems_isr_entry     handler,                  /* isr routine        */
67  rtems_vector_number vector,                   /* vector number      */
68  int                 type                      /* RTEMS or RAW intr  */
69);
70
71static inline uint32_t   get_itimer(void)
72{
73    register uint32_t   rc;
74
75#ifndef ppc405 /* this is a ppc403 */
76    __asm__ volatile ("mfspr %0, 0x3dd" : "=r" ((rc))); /* TBLO */
77#else /* ppc405 */
78    __asm__ volatile ("mfspr %0, 0x10c" : "=r" ((rc))); /* 405GP TBL */
79#endif /* ppc405 */
80
81    return rc;
82}
83
84/*
85 *  ISR Handler
86 */
87
88void Clock_isr(void* handle)
89{
90    uint32_t   clicks_til_next_interrupt;
91#if defined(BSP_PPC403_CLOCK_ISR_IRQ_LEVEL)
92        uint32_t   l_orig = _ISR_Get_level();
93#endif
94    if (!auto_restart)
95    {
96      uint32_t   itimer_value;
97      /*
98       * setup for next interrupt; making sure the new value is reasonably
99       * in the future.... in case we lost out on an interrupt somehow
100       */
101
102      itimer_value = get_itimer();
103      tick_time += pit_value;
104
105      /*
106       * how far away is next interrupt *really*
107       * It may be a long time; this subtraction works even if
108       * Clock_clicks_interrupt < Clock_clicks_low_order via
109       * the miracle of unsigned math.
110       */
111      clicks_til_next_interrupt = tick_time - itimer_value;
112
113      /*
114       * If it is too soon then bump it up.
115       * This should only happen if CPU_HPPA_CLICKS_PER_TICK is too small.
116       * But setting it low is useful for debug, so...
117       */
118
119      if (clicks_til_next_interrupt < 400)
120      {
121        tick_time = itimer_value + 1000;
122        clicks_til_next_interrupt = 1000;
123        /* XXX: count these! this should be rare */
124      }
125
126      /*
127       * If it is too late, that means we missed the interrupt somehow.
128       * Rather than wait 35-50s for a wrap, we just fudge it here.
129       */
130
131      if (clicks_til_next_interrupt > pit_value)
132      {
133        tick_time = itimer_value + 1000;
134        clicks_til_next_interrupt = 1000;
135        /* XXX: count these! this should never happen :-) */
136      }
137
138      __asm__ volatile ("mtspr 0x3db, %0" :: "r"
139                         (clicks_til_next_interrupt)); /* PIT */
140  }
141
142    __asm__ volatile ( "mtspr 0x3d8, %0" :: "r" (0x08000000)); /* TSR */
143
144    Clock_driver_ticks++;
145
146        /* Give BSP a chance to say if they want to re-enable interrupts */
147
148#if defined(BSP_PPC403_CLOCK_ISR_IRQ_LEVEL)
149        _ISR_Set_level(BSP_PPC403_CLOCK_ISR_IRQ_LEVEL);
150#endif
151
152    rtems_clock_tick();
153
154#if defined(BSP_PPC403_CLOCK_ISR_IRQ_LEVEL)
155        _ISR_Set_level(l_orig)
156#endif
157}
158
159int ClockIsOn(const rtems_irq_connect_data* unused)
160{
161    register uint32_t   tcr;
162
163    __asm__ volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
164
165    return (tcr & 0x04000000) != 0;
166}
167
168void ClockOff(
169              const rtems_irq_connect_data* unused
170)
171{
172    register uint32_t   tcr;
173
174    __asm__ volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
175
176    tcr &= ~ 0x04400000;
177
178    __asm__ volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
179}
180
181void ClockOn(
182              const rtems_irq_connect_data* unused
183)
184{
185    uint32_t   iocr;
186    register uint32_t   tcr;
187#ifdef ppc403
188    uint32_t   pvr;
189#endif /* ppc403 */
190
191    Clock_driver_ticks = 0;
192
193#ifndef ppc405 /* this is a ppc403 */
194    __asm__ volatile ("mfdcr %0, 0xa0" : "=r" (iocr)); /* IOCR */
195    if (bsp_timer_internal_clock) {
196        iocr &= ~4; /* timer clocked from system clock */
197    }
198    else {
199        iocr |= 4; /* select external timer clock */
200    }
201    __asm__ volatile ("mtdcr 0xa0, %0" : "=r" (iocr) : "0" (iocr)); /* IOCR */
202
203    __asm__ volatile ("mfspr %0, 0x11f" : "=r" ((pvr))); /* PVR */
204    if (((pvr & 0xffff0000) >> 16) != 0x0020)
205      return; /* Not a ppc403 */
206
207    if ((pvr & 0xff00) == 0x0000) /* 403GA */
208#if 0 /* FIXME: in which processor versions will "autoload" work properly? */
209      auto_restart = (pvr & 0x00f0) > 0x0000 ? true : false;
210#else
211    /* no known chip version supports auto restart of timer... */
212    auto_restart = false;
213#endif
214    else if ((pvr & 0xff00) == 0x0100) /* 403GB */
215      auto_restart = true;
216
217#else /* ppc405 */
218    __asm__ volatile ("mfdcr %0, 0x0b2" : "=r" (iocr));  /*405GP CPC0_CR1 */
219    if (bsp_timer_internal_clock) {
220        iocr &=~0x800000        ;/* timer clocked from system clock CETE*/
221    }
222    else {
223        iocr |= 0x800000; /* select external timer clock CETE*/
224    }
225    __asm__ volatile ("mtdcr 0x0b2, %0" : "=r" (iocr) : "0" (iocr)); /* 405GP CPC0_CR1 */
226
227     /*
228      * Enable auto restart
229      */
230
231    auto_restart=true;
232
233#endif /* ppc405 */
234    pit_value = rtems_configuration_get_microseconds_per_tick() *
235      bsp_clicks_per_usec;
236
237     /*
238      * Set PIT value
239      */
240
241    __asm__ volatile ("mtspr 0x3db, %0" : : "r" (pit_value)); /* PIT */
242
243     /*
244      * Set timer to autoreload, bit TCR->ARE = 1  0x0400000
245      * Enable PIT interrupt, bit TCR->PIE = 1     0x4000000
246      */
247    tick_time = get_itimer() + pit_value;
248
249    __asm__ volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */
250    tcr = (tcr & ~0x04400000) | (auto_restart ? 0x04400000 : 0x04000000);
251#if 1
252    __asm__ volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */
253#endif
254
255}
256
257
258
259void Install_clock(
260  void (*clock_isr)(void *)
261)
262{
263   rtems_irq_connect_data clockIrqConnData;
264
265#ifdef ppc403
266    uint32_t   pvr;
267#endif /* ppc403 */
268
269    Clock_driver_ticks = 0;
270
271    /*
272     * initialize the interval here
273     * First tick is set to right amount of time in the future
274     * Future ticks will be incremented over last value set
275     * in order to provide consistent clicks in the face of
276     * interrupt overhead
277     */
278
279   clockIrqConnData.on   = ClockOn;
280   clockIrqConnData.off  = ClockOff;
281   clockIrqConnData.isOn = ClockIsOn;
282   clockIrqConnData.name = BSP_PIT;
283   clockIrqConnData.hdl  = clock_isr;
284   if (!BSP_install_rtems_irq_handler (&clockIrqConnData)) {
285     printk("Unable to connect Clock Irq handler\n");
286     rtems_fatal_error_occurred(1);
287   }
288
289   atexit(Clock_exit);
290}
291
292void
293ReInstall_clock(
294  void (*new_clock_isr)(void *)
295)
296{
297  uint32_t   isrlevel = 0;
298  rtems_irq_connect_data clockIrqConnData;
299
300  rtems_interrupt_disable(isrlevel);
301
302
303  clockIrqConnData.name = BSP_PIT;
304  if (!BSP_get_current_rtems_irq_handler(&clockIrqConnData)) {
305    printk("Unable to stop system clock\n");
306    rtems_fatal_error_occurred(1);
307  }
308
309  BSP_remove_rtems_irq_handler (&clockIrqConnData);
310
311  clockIrqConnData.on   = ClockOn;
312  clockIrqConnData.off  = ClockOff;
313  clockIrqConnData.isOn = ClockIsOn;
314  clockIrqConnData.name = BSP_PIT;
315  clockIrqConnData.hdl  = new_clock_isr;
316
317  if (!BSP_install_rtems_irq_handler (&clockIrqConnData)) {
318    printk("Unable to connect Clock Irq handler\n");
319    rtems_fatal_error_occurred(1);
320  }
321
322  rtems_interrupt_enable(isrlevel);
323}
324
325
326/*
327 * Called via atexit()
328 * Remove the clock interrupt handler by setting handler to NULL
329 *
330 * This will not work on the 405GP because
331 * when bit's are set in TCR they can only be unset by a reset
332 */
333
334void Clock_exit(void)
335{
336  rtems_irq_connect_data clockIrqConnData;
337
338  clockIrqConnData.name = BSP_PIT;
339  if (!BSP_get_current_rtems_irq_handler(&clockIrqConnData)) {
340    printk("Unable to stop system clock\n");
341    rtems_fatal_error_occurred(1);
342  }
343
344  BSP_remove_rtems_irq_handler (&clockIrqConnData);
345}
346
347rtems_device_driver Clock_initialize(
348  rtems_device_major_number major,
349  rtems_device_minor_number minor,
350  void *pargp
351)
352{
353  Install_clock( Clock_isr );
354
355  return RTEMS_SUCCESSFUL;
356}
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