1 | /* clock.c |
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2 | * |
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3 | * This routine initializes the interval timer on the |
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4 | * PowerPC 403 CPU. The tick frequency is specified by the bsp. |
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5 | * |
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6 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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7 | * |
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8 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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9 | * |
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10 | * To anyone who acknowledges that this file is provided "AS IS" |
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11 | * without any express or implied warranty: |
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12 | * permission to use, copy, modify, and distribute this file |
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13 | * for any purpose is hereby granted without fee, provided that |
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14 | * the above copyright notice and this notice appears in all |
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15 | * copies, and that the name of i-cubed limited not be used in |
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16 | * advertising or publicity pertaining to distribution of the |
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17 | * software without specific, written prior permission. |
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18 | * i-cubed limited makes no representations about the suitability |
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19 | * of this software for any purpose. |
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20 | * |
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21 | * Derived from c/src/lib/libcpu/hppa1.1/clock/clock.c: |
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22 | * |
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23 | * Modifications for deriving timer clock from cpu system clock by |
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24 | * Thomas Doerfler <td@imd.m.isar.de> |
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25 | * for these modifications: |
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26 | * COPYRIGHT (c) 1997 by IMD, Puchheim, Germany. |
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27 | * |
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28 | * COPYRIGHT (c) 1989-2007. |
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29 | * On-Line Applications Research Corporation (OAR). |
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30 | * |
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31 | * The license and distribution terms for this file may be |
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32 | * found in the file LICENSE in this distribution or at |
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33 | * http://www.rtems.com/license/LICENSE. |
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34 | * |
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35 | * Modifications for PPC405GP by Dennis Ehlin |
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36 | * |
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37 | * $Id$ |
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38 | */ |
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39 | |
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40 | #include <rtems.h> |
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41 | #include <rtems/clockdrv.h> |
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42 | #include <rtems/libio.h> |
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43 | #include <stdlib.h> /* for atexit() */ |
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44 | #include <rtems/bspIo.h> |
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45 | #include <rtems/powerpc/powerpc.h> |
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46 | /* |
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47 | * check, which exception handling code is present |
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48 | */ |
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49 | #if !defined(ppc405) |
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50 | #define PPC_HAS_CLASSIC_EXCEPTIONS TRUE |
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51 | #else |
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52 | #define PPC_HAS_CLASSIC_EXCEPTIONS FALSE |
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53 | #include <bsp/irq.h> |
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54 | #endif |
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55 | |
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56 | volatile uint32_t Clock_driver_ticks; |
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57 | static uint32_t pit_value, tick_time; |
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58 | static rtems_boolean auto_restart; |
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59 | |
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60 | void Clock_exit( void ); |
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61 | |
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62 | rtems_isr_entry set_vector( /* returns old vector */ |
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63 | rtems_isr_entry handler, /* isr routine */ |
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64 | rtems_vector_number vector, /* vector number */ |
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65 | int type /* RTEMS or RAW intr */ |
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66 | ); |
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67 | |
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68 | /* |
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69 | * These are set by clock driver during its init |
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70 | */ |
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71 | |
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72 | rtems_device_major_number rtems_clock_major = ~0; |
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73 | rtems_device_minor_number rtems_clock_minor; |
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74 | |
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75 | static inline uint32_t get_itimer(void) |
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76 | { |
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77 | register uint32_t rc; |
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78 | |
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79 | #ifndef ppc405 /* this is a ppc403 */ |
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80 | asm volatile ("mfspr %0, 0x3dd" : "=r" ((rc))); /* TBLO */ |
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81 | #else /* ppc405 */ |
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82 | asm volatile ("mfspr %0, 0x10c" : "=r" ((rc))); /* 405GP TBL */ |
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83 | #endif /* ppc405 */ |
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84 | |
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85 | return rc; |
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86 | } |
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87 | |
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88 | /* |
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89 | * ISR Handler |
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90 | */ |
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91 | |
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92 | #if PPC_HAS_CLASSIC_EXCEPTIONS |
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93 | rtems_isr Clock_isr(rtems_vector_number vector) |
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94 | #else |
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95 | void Clock_isr(void* handle) |
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96 | #endif |
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97 | { |
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98 | uint32_t clicks_til_next_interrupt; |
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99 | if (!auto_restart) |
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100 | { |
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101 | uint32_t itimer_value; |
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102 | /* |
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103 | * setup for next interrupt; making sure the new value is reasonably |
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104 | * in the future.... in case we lost out on an interrupt somehow |
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105 | */ |
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106 | |
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107 | itimer_value = get_itimer(); |
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108 | tick_time += pit_value; |
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109 | |
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110 | /* |
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111 | * how far away is next interrupt *really* |
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112 | * It may be a long time; this subtraction works even if |
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113 | * Clock_clicks_interrupt < Clock_clicks_low_order via |
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114 | * the miracle of unsigned math. |
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115 | */ |
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116 | clicks_til_next_interrupt = tick_time - itimer_value; |
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117 | |
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118 | /* |
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119 | * If it is too soon then bump it up. |
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120 | * This should only happen if CPU_HPPA_CLICKS_PER_TICK is too small. |
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121 | * But setting it low is useful for debug, so... |
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122 | */ |
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123 | |
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124 | if (clicks_til_next_interrupt < 400) |
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125 | { |
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126 | tick_time = itimer_value + 1000; |
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127 | clicks_til_next_interrupt = 1000; |
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128 | /* XXX: count these! this should be rare */ |
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129 | } |
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130 | |
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131 | /* |
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132 | * If it is too late, that means we missed the interrupt somehow. |
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133 | * Rather than wait 35-50s for a wrap, we just fudge it here. |
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134 | */ |
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135 | |
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136 | if (clicks_til_next_interrupt > pit_value) |
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137 | { |
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138 | tick_time = itimer_value + 1000; |
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139 | clicks_til_next_interrupt = 1000; |
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140 | /* XXX: count these! this should never happen :-) */ |
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141 | } |
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142 | |
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143 | asm volatile ("mtspr 0x3db, %0" :: "r" |
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144 | (clicks_til_next_interrupt)); /* PIT */ |
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145 | } |
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146 | |
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147 | asm volatile ( "mtspr 0x3d8, %0" :: "r" (0x08000000)); /* TSR */ |
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148 | |
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149 | Clock_driver_ticks++; |
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150 | |
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151 | rtems_clock_tick(); |
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152 | } |
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153 | |
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154 | #if !PPC_HAS_CLASSIC_EXCEPTIONS |
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155 | int ClockIsOn(const rtems_irq_connect_data* unused) |
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156 | { |
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157 | register uint32_t tcr; |
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158 | |
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159 | asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */ |
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160 | |
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161 | return (tcr & 0x04000000) != 0; |
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162 | } |
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163 | #endif |
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164 | |
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165 | void ClockOff( |
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166 | #if PPC_HAS_CLASSIC_EXCEPTIONS |
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167 | void |
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168 | #else |
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169 | const rtems_irq_connect_data* unused |
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170 | #endif |
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171 | ) |
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172 | { |
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173 | register uint32_t tcr; |
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174 | |
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175 | asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */ |
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176 | |
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177 | tcr &= ~ 0x04400000; |
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178 | |
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179 | asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */ |
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180 | } |
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181 | |
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182 | void ClockOn( |
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183 | #if PPC_HAS_CLASSIC_EXCEPTIONS |
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184 | void |
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185 | #else |
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186 | const rtems_irq_connect_data* unused |
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187 | #endif |
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188 | ) |
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189 | { |
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190 | uint32_t iocr; |
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191 | register uint32_t tcr; |
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192 | extern uint32_t bsp_clicks_per_usec; |
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193 | extern boolean bsp_timer_internal_clock; |
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194 | #ifdef ppc403 |
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195 | uint32_t pvr; |
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196 | #endif /* ppc403 */ |
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197 | |
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198 | Clock_driver_ticks = 0; |
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199 | |
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200 | #ifndef ppc405 /* this is a ppc403 */ |
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201 | asm volatile ("mfdcr %0, 0xa0" : "=r" (iocr)); /* IOCR */ |
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202 | if (bsp_timer_internal_clock) { |
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203 | iocr &= ~4; /* timer clocked from system clock */ |
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204 | } |
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205 | else { |
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206 | iocr |= 4; /* select external timer clock */ |
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207 | } |
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208 | asm volatile ("mtdcr 0xa0, %0" : "=r" (iocr) : "0" (iocr)); /* IOCR */ |
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209 | |
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210 | asm volatile ("mfspr %0, 0x11f" : "=r" ((pvr))); /* PVR */ |
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211 | if (((pvr & 0xffff0000) >> 16) != 0x0020) |
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212 | return; /* Not a ppc403 */ |
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213 | |
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214 | if ((pvr & 0xff00) == 0x0000) /* 403GA */ |
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215 | #if 0 /* FIXME: in which processor versions will "autoload" work properly? */ |
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216 | auto_restart = (pvr & 0x00f0) > 0x0000 ? 1 : 0; |
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217 | #else |
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218 | /* no known chip version supports auto restart of timer... */ |
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219 | auto_restart = 0; |
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220 | #endif |
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221 | else if ((pvr & 0xff00) == 0x0100) /* 403GB */ |
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222 | auto_restart = 1; |
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223 | |
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224 | #else /* ppc405 */ |
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225 | asm volatile ("mfdcr %0, 0x0b2" : "=r" (iocr)); /*405GP CPC0_CR1 */ |
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226 | if (bsp_timer_internal_clock) { |
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227 | iocr &=~0x800000 ;/* timer clocked from system clock CETE*/ |
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228 | } |
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229 | else { |
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230 | iocr |= 0x800000; /* select external timer clock CETE*/ |
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231 | } |
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232 | asm volatile ("mtdcr 0x0b2, %0" : "=r" (iocr) : "0" (iocr)); /* 405GP CPC0_CR1 */ |
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233 | |
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234 | /* |
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235 | * Enable auto restart |
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236 | */ |
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237 | |
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238 | auto_restart=1; |
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239 | |
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240 | #endif /* ppc405 */ |
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241 | pit_value = rtems_configuration_get_microseconds_per_tick() * |
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242 | bsp_clicks_per_usec; |
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243 | |
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244 | /* |
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245 | * Set PIT value |
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246 | */ |
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247 | |
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248 | asm volatile ("mtspr 0x3db, %0" : : "r" (pit_value)); /* PIT */ |
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249 | |
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250 | /* |
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251 | * Set timer to autoreload, bit TCR->ARE = 1 0x0400000 |
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252 | * Enable PIT interrupt, bit TCR->PIE = 1 0x4000000 |
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253 | */ |
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254 | tick_time = get_itimer() + pit_value; |
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255 | |
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256 | asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */ |
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257 | tcr = (tcr & ~0x04400000) | (auto_restart ? 0x04400000 : 0x04000000); |
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258 | #if 1 |
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259 | asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */ |
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260 | #endif |
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261 | |
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262 | } |
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263 | |
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264 | |
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265 | |
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266 | void Install_clock( |
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267 | #if PPC_HAS_CLASSIC_EXCEPTIONS |
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268 | rtems_isr_entry clock_isr |
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269 | #else |
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270 | void (*clock_isr)(void *) |
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271 | #endif |
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272 | ) |
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273 | { |
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274 | #ifdef ppc403 |
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275 | uint32_t pvr; |
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276 | #endif /* ppc403 */ |
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277 | |
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278 | Clock_driver_ticks = 0; |
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279 | |
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280 | /* |
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281 | * initialize the interval here |
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282 | * First tick is set to right amount of time in the future |
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283 | * Future ticks will be incremented over last value set |
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284 | * in order to provide consistent clicks in the face of |
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285 | * interrupt overhead |
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286 | */ |
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287 | |
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288 | #if PPC_HAS_CLASSIC_EXCEPTIONS |
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289 | { |
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290 | rtems_isr_entry previous_isr; |
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291 | rtems_interrupt_catch(clock_isr, PPC_IRQ_PIT, &previous_isr); |
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292 | ClockOn(); |
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293 | } |
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294 | #else |
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295 | { |
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296 | rtems_irq_connect_data clockIrqConnData; |
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297 | clockIrqConnData.on = ClockOn; |
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298 | clockIrqConnData.off = ClockOff; |
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299 | clockIrqConnData.isOn = ClockIsOn; |
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300 | clockIrqConnData.name = BSP_PIT; |
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301 | clockIrqConnData.hdl = clock_isr; |
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302 | if (!BSP_install_rtems_irq_handler (&clockIrqConnData)) { |
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303 | printk("Unable to connect Clock Irq handler\n"); |
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304 | rtems_fatal_error_occurred(1); |
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305 | } |
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306 | } |
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307 | #endif |
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308 | atexit(Clock_exit); |
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309 | } |
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310 | |
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311 | void |
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312 | ReInstall_clock( |
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313 | #if PPC_HAS_CLASSIC_EXCEPTIONS |
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314 | rtems_isr_entry new_clock_isr |
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315 | #else |
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316 | void (*new_clock_isr)(void *) |
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317 | #endif |
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318 | ) |
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319 | { |
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320 | uint32_t isrlevel = 0; |
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321 | |
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322 | rtems_interrupt_disable(isrlevel); |
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323 | |
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324 | #if PPC_HAS_CLASSIC_EXCEPTIONS |
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325 | { |
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326 | rtems_isr_entry previous_isr; |
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327 | rtems_interrupt_catch(new_clock_isr, PPC_IRQ_PIT, &previous_isr); |
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328 | ClockOn(); |
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329 | } |
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330 | #else |
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331 | { |
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332 | rtems_irq_connect_data clockIrqConnData; |
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333 | |
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334 | clockIrqConnData.name = BSP_PIT; |
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335 | if (!BSP_get_current_rtems_irq_handler(&clockIrqConnData)) { |
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336 | printk("Unable to stop system clock\n"); |
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337 | rtems_fatal_error_occurred(1); |
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338 | } |
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339 | |
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340 | BSP_remove_rtems_irq_handler (&clockIrqConnData); |
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341 | |
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342 | clockIrqConnData.on = ClockOn; |
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343 | clockIrqConnData.off = ClockOff; |
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344 | clockIrqConnData.isOn = ClockIsOn; |
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345 | clockIrqConnData.name = BSP_PIT; |
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346 | clockIrqConnData.hdl = new_clock_isr; |
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347 | |
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348 | if (!BSP_install_rtems_irq_handler (&clockIrqConnData)) { |
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349 | printk("Unable to connect Clock Irq handler\n"); |
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350 | rtems_fatal_error_occurred(1); |
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351 | } |
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352 | } |
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353 | #endif |
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354 | |
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355 | rtems_interrupt_enable(isrlevel); |
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356 | } |
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357 | |
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358 | |
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359 | /* |
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360 | * Called via atexit() |
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361 | * Remove the clock interrupt handler by setting handler to NULL |
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362 | * |
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363 | * This will not work on the 405GP because |
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364 | * when bit's are set in TCR they can only be unset by a reset |
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365 | */ |
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366 | |
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367 | void Clock_exit(void) |
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368 | { |
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369 | #if PPC_HAS_CLASSIC_EXCEPTIONS |
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370 | ClockOff(); |
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371 | |
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372 | (void) set_vector(0, PPC_IRQ_PIT, 1); |
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373 | #else |
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374 | { |
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375 | rtems_irq_connect_data clockIrqConnData; |
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376 | |
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377 | clockIrqConnData.name = BSP_PIT; |
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378 | if (!BSP_get_current_rtems_irq_handler(&clockIrqConnData)) { |
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379 | printk("Unable to stop system clock\n"); |
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380 | rtems_fatal_error_occurred(1); |
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381 | } |
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382 | |
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383 | BSP_remove_rtems_irq_handler (&clockIrqConnData); |
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384 | } |
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385 | #endif |
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386 | } |
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387 | |
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388 | rtems_device_driver Clock_initialize( |
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389 | rtems_device_major_number major, |
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390 | rtems_device_minor_number minor, |
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391 | void *pargp |
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392 | ) |
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393 | { |
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394 | Install_clock( Clock_isr ); |
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395 | |
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396 | /* |
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397 | * make major/minor avail to others such as shared memory driver |
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398 | */ |
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399 | |
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400 | rtems_clock_major = major; |
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401 | rtems_clock_minor = minor; |
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402 | |
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403 | return RTEMS_SUCCESSFUL; |
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404 | } |
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405 | |
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406 | rtems_device_driver Clock_control( |
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407 | rtems_device_major_number major, |
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408 | rtems_device_minor_number minor, |
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409 | void *pargp |
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410 | ) |
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411 | { |
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412 | rtems_libio_ioctl_args_t *args = pargp; |
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413 | |
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414 | if (args == 0) |
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415 | goto done; |
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416 | |
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417 | /* |
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418 | * This is hokey, but until we get a defined interface |
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419 | * to do this, it will just be this simple... |
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420 | */ |
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421 | |
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422 | if (args->command == rtems_build_name('I', 'S', 'R', ' ')) |
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423 | { |
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424 | #if PPC_HAS_CLASSIC_EXCEPTIONS |
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425 | Clock_isr(PPC_IRQ_PIT); |
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426 | #else |
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427 | Clock_isr(NULL); |
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428 | #endif |
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429 | } |
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430 | else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) |
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431 | { |
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432 | ReInstall_clock(args->buffer); |
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433 | } |
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434 | |
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435 | done: |
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436 | return RTEMS_SUCCESSFUL; |
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437 | } |
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