[3235ad9] | 1 | /* clock.c |
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| 2 | * |
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| 3 | * This routine initializes the interval timer on the |
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| 4 | * PowerPC 403 CPU. The tick frequency is specified by the bsp. |
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| 5 | * |
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[e57b0e2] | 6 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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[3235ad9] | 7 | * |
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| 8 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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| 9 | * |
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| 10 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 11 | * without any express or implied warranty: |
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| 12 | * permission to use, copy, modify, and distribute this file |
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| 13 | * for any purpose is hereby granted without fee, provided that |
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| 14 | * the above copyright notice and this notice appears in all |
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| 15 | * copies, and that the name of i-cubed limited not be used in |
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| 16 | * advertising or publicity pertaining to distribution of the |
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| 17 | * software without specific, written prior permission. |
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| 18 | * i-cubed limited makes no representations about the suitability |
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| 19 | * of this software for any purpose. |
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| 20 | * |
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[3ec7bfc] | 21 | * Derived from c/src/lib/libcpu/hppa1.1/clock/clock.c: |
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[3235ad9] | 22 | * |
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[aecfa2b] | 23 | * Modifications for deriving timer clock from cpu system clock by |
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| 24 | * Thomas Doerfler <td@imd.m.isar.de> |
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| 25 | * for these modifications: |
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| 26 | * COPYRIGHT (c) 1997 by IMD, Puchheim, Germany. |
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| 27 | * |
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| 28 | * |
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[08311cc3] | 29 | * COPYRIGHT (c) 1989-1999. |
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[3235ad9] | 30 | * On-Line Applications Research Corporation (OAR). |
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| 31 | * |
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[98e4ebf5] | 32 | * The license and distribution terms for this file may be |
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| 33 | * found in the file LICENSE in this distribution or at |
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[03f2154e] | 34 | * http://www.OARcorp.com/rtems/license.html. |
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[3235ad9] | 35 | * |
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[879a047] | 36 | * $Id$ |
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[3235ad9] | 37 | */ |
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| 38 | |
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[f817b02] | 39 | #include <rtems.h> |
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[3235ad9] | 40 | #include <clockdrv.h> |
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[3a4ae6c] | 41 | #include <rtems/libio.h> |
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[3235ad9] | 42 | |
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| 43 | #include <stdlib.h> /* for atexit() */ |
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| 44 | |
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| 45 | volatile rtems_unsigned32 Clock_driver_ticks; |
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| 46 | static rtems_unsigned32 pit_value, tick_time; |
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| 47 | static rtems_boolean auto_restart; |
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| 48 | |
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[3a4ae6c] | 49 | void Clock_exit( void ); |
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| 50 | |
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| 51 | /* |
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| 52 | * These are set by clock driver during its init |
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| 53 | */ |
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| 54 | |
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| 55 | rtems_device_major_number rtems_clock_major = ~0; |
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| 56 | rtems_device_minor_number rtems_clock_minor; |
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| 57 | |
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[93bea77] | 58 | static inline rtems_unsigned32 get_itimer(void) |
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[3235ad9] | 59 | { |
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[3a4ae6c] | 60 | register rtems_unsigned32 rc; |
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[3235ad9] | 61 | |
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[e57b0e2] | 62 | asm volatile ("mfspr %0, 0x3dd" : "=r" ((rc))); /* TBLO */ |
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[3235ad9] | 63 | |
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[3a4ae6c] | 64 | return rc; |
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| 65 | } |
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| 66 | |
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| 67 | /* |
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| 68 | * ISR Handler |
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| 69 | */ |
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| 70 | |
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| 71 | rtems_isr |
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| 72 | Clock_isr(rtems_vector_number vector) |
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[3235ad9] | 73 | { |
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[3a4ae6c] | 74 | if (!auto_restart) |
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[e57b0e2] | 75 | { |
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| 76 | rtems_unsigned32 clicks_til_next_interrupt; |
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| 77 | rtems_unsigned32 itimer_value; |
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| 78 | |
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| 79 | /* |
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| 80 | * setup for next interrupt; making sure the new value is reasonably |
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| 81 | * in the future.... in case we lost out on an interrupt somehow |
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| 82 | */ |
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| 83 | |
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| 84 | itimer_value = get_itimer(); |
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| 85 | tick_time += pit_value; |
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| 86 | |
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| 87 | /* |
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| 88 | * how far away is next interrupt *really* |
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| 89 | * It may be a long time; this subtraction works even if |
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| 90 | * Clock_clicks_interrupt < Clock_clicks_low_order via |
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| 91 | * the miracle of unsigned math. |
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| 92 | */ |
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| 93 | clicks_til_next_interrupt = tick_time - itimer_value; |
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| 94 | |
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| 95 | /* |
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| 96 | * If it is too soon then bump it up. |
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| 97 | * This should only happen if CPU_HPPA_CLICKS_PER_TICK is too small. |
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| 98 | * But setting it low is useful for debug, so... |
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| 99 | */ |
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| 100 | |
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| 101 | if (clicks_til_next_interrupt < 400) |
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| 102 | { |
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| 103 | tick_time = itimer_value + 1000; |
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| 104 | clicks_til_next_interrupt = 1000; |
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| 105 | /* XXX: count these! this should be rare */ |
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| 106 | } |
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| 107 | |
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| 108 | /* |
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| 109 | * If it is too late, that means we missed the interrupt somehow. |
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| 110 | * Rather than wait 35-50s for a wrap, we just fudge it here. |
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| 111 | */ |
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| 112 | |
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| 113 | if (clicks_til_next_interrupt > pit_value) |
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| 114 | { |
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| 115 | tick_time = itimer_value + 1000; |
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| 116 | clicks_til_next_interrupt = 1000; |
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| 117 | /* XXX: count these! this should never happen :-) */ |
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| 118 | } |
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| 119 | |
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| 120 | asm volatile ("mtspr 0x3db, %0" :: "r" |
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| 121 | (clicks_til_next_interrupt)); /* PIT */ |
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| 122 | } |
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| 123 | |
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| 124 | asm volatile ( "mtspr 0x3d8, %0" :: "r" (0x08000000)); /* TSR */ |
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| 125 | |
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[3a4ae6c] | 126 | Clock_driver_ticks++; |
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[e57b0e2] | 127 | |
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[3a4ae6c] | 128 | rtems_clock_tick(); |
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[3235ad9] | 129 | } |
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| 130 | |
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| 131 | void Install_clock(rtems_isr_entry clock_isr) |
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| 132 | { |
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| 133 | rtems_isr_entry previous_isr; |
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| 134 | rtems_unsigned32 pvr, iocr; |
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[0dd1d44] | 135 | register rtems_unsigned32 tcr; |
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[e57b0e2] | 136 | |
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[3235ad9] | 137 | Clock_driver_ticks = 0; |
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[e57b0e2] | 138 | |
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| 139 | asm volatile ("mfdcr %0, 0xa0" : "=r" (iocr)); /* IOCR */ |
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[aecfa2b] | 140 | |
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[458bd34] | 141 | if (rtems_cpu_configuration_get_timer_internal_clock()) { |
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[aecfa2b] | 142 | iocr &= ~4; /* timer clocked from system clock */ |
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| 143 | } |
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| 144 | else { |
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| 145 | iocr |= 4; /* select external timer clock */ |
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| 146 | } |
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| 147 | |
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[e57b0e2] | 148 | asm volatile ("mtdcr 0xa0, %0" : "=r" (iocr) : "0" (iocr)); /* IOCR */ |
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| 149 | |
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| 150 | asm volatile ("mfspr %0, 0x11f" : "=r" ((pvr))); /* PVR */ |
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| 151 | |
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[3235ad9] | 152 | if (((pvr & 0xffff0000) >> 16) != 0x0020) |
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[e57b0e2] | 153 | return; /* Not a ppc403 */ |
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| 154 | |
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[3235ad9] | 155 | if ((pvr & 0xff00) == 0x0000) /* 403GA */ |
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[aecfa2b] | 156 | #if 0 /* FIXME: in which processor versions will "autoload" work properly? */ |
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[e57b0e2] | 157 | auto_restart = (pvr & 0x00f0) > 0x0000 ? 1 : 0; |
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[aecfa2b] | 158 | #else |
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| 159 | /* no known chip version supports auto restart of timer... */ |
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| 160 | auto_restart = 0; |
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| 161 | #endif |
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[3235ad9] | 162 | else if ((pvr & 0xff00) == 0x0100) /* 403GB */ |
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[e57b0e2] | 163 | auto_restart = 1; |
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| 164 | |
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[f817b02] | 165 | pit_value = rtems_configuration_get_microseconds_per_tick() * |
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[458bd34] | 166 | rtems_cpu_configuration_get_clicks_per_usec(); |
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[e57b0e2] | 167 | |
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| 168 | |
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[0dd1d44] | 169 | /* |
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| 170 | * initialize the interval here |
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| 171 | * First tick is set to right amount of time in the future |
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| 172 | * Future ticks will be incremented over last value set |
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| 173 | * in order to provide consistent clicks in the face of |
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| 174 | * interrupt overhead |
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| 175 | */ |
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| 176 | |
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| 177 | rtems_interrupt_catch(clock_isr, PPC_IRQ_PIT, &previous_isr); |
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| 178 | |
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| 179 | asm volatile ("mtspr 0x3db, %0" : : "r" (pit_value)); /* PIT */ |
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[e57b0e2] | 180 | |
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[0dd1d44] | 181 | asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */ |
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[e57b0e2] | 182 | |
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[0dd1d44] | 183 | tcr &= ~ 0x04400000; |
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[e57b0e2] | 184 | |
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[0dd1d44] | 185 | tcr |= (auto_restart ? 0x04400000 : 0x04000000); |
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[e57b0e2] | 186 | |
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[0dd1d44] | 187 | tick_time = get_itimer() + pit_value; |
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[e57b0e2] | 188 | |
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[0dd1d44] | 189 | asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */ |
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| 190 | |
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[3235ad9] | 191 | atexit(Clock_exit); |
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| 192 | } |
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| 193 | |
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[3a4ae6c] | 194 | void |
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| 195 | ReInstall_clock(rtems_isr_entry new_clock_isr) |
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[3235ad9] | 196 | { |
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[3a4ae6c] | 197 | rtems_isr_entry previous_isr; |
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| 198 | rtems_unsigned32 isrlevel = 0; |
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[3235ad9] | 199 | |
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[3a4ae6c] | 200 | rtems_interrupt_disable(isrlevel); |
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| 201 | |
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[e57b0e2] | 202 | rtems_interrupt_catch(new_clock_isr, PPC_IRQ_PIT, &previous_isr); |
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[3235ad9] | 203 | |
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[3a4ae6c] | 204 | rtems_interrupt_enable(isrlevel); |
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[3235ad9] | 205 | } |
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| 206 | |
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[3a4ae6c] | 207 | |
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[3235ad9] | 208 | /* |
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| 209 | * Called via atexit() |
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| 210 | * Remove the clock interrupt handler by setting handler to NULL |
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| 211 | */ |
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| 212 | |
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| 213 | void |
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| 214 | Clock_exit(void) |
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| 215 | { |
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[0dd1d44] | 216 | register rtems_unsigned32 tcr; |
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[e57b0e2] | 217 | |
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[0dd1d44] | 218 | asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */ |
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[e57b0e2] | 219 | |
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[0dd1d44] | 220 | tcr &= ~ 0x04400000; |
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[e57b0e2] | 221 | |
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[0dd1d44] | 222 | asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */ |
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[e57b0e2] | 223 | |
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[0dd1d44] | 224 | (void) set_vector(0, PPC_IRQ_PIT, 1); |
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[3235ad9] | 225 | } |
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| 226 | |
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[3a4ae6c] | 227 | rtems_device_driver Clock_initialize( |
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| 228 | rtems_device_major_number major, |
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| 229 | rtems_device_minor_number minor, |
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| 230 | void *pargp |
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| 231 | ) |
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| 232 | { |
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| 233 | Install_clock( Clock_isr ); |
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| 234 | |
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| 235 | /* |
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| 236 | * make major/minor avail to others such as shared memory driver |
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| 237 | */ |
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| 238 | |
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| 239 | rtems_clock_major = major; |
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| 240 | rtems_clock_minor = minor; |
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| 241 | |
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| 242 | return RTEMS_SUCCESSFUL; |
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| 243 | } |
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| 244 | |
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| 245 | rtems_device_driver Clock_control( |
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| 246 | rtems_device_major_number major, |
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| 247 | rtems_device_minor_number minor, |
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| 248 | void *pargp |
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| 249 | ) |
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| 250 | { |
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| 251 | rtems_libio_ioctl_args_t *args = pargp; |
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| 252 | |
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| 253 | if (args == 0) |
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| 254 | goto done; |
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| 255 | |
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| 256 | /* |
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| 257 | * This is hokey, but until we get a defined interface |
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| 258 | * to do this, it will just be this simple... |
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| 259 | */ |
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| 260 | |
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| 261 | if (args->command == rtems_build_name('I', 'S', 'R', ' ')) |
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| 262 | { |
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| 263 | Clock_isr(PPC_IRQ_PIT); |
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| 264 | } |
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| 265 | else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) |
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| 266 | { |
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| 267 | ReInstall_clock(args->buffer); |
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| 268 | } |
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| 269 | |
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| 270 | done: |
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| 271 | return RTEMS_SUCCESSFUL; |
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| 272 | } |
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| 273 | |
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