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cpu_asm.S @ a982e0c6

4.104.114.84.95

Last change on this file since a982e0c6 was a982e0c6, checked in by Joel Sherrill <joel.sherrill@…>, on 10/18/00 at 18:24:43

2000-10-18 Sergei Organov <osv@…>

Added full support for MPC505.
mpc505/ictrl: New directory.
configure.in, mpc505/Makefile.am: Modified to reflect ictrl addition.
mpc505/ictrl/.cvsignore, mpc505/ictrl/Makefile.am, mpc505/ictrl/ictrl.c, mpc505/ictrl/ictrl.h: New files.
mpc505/timer/timer.c: Use <rtems.h>, not "rtems.h".
mpc505/vectors/Makefile.am: alignment exception handler now included.
mpc505/vectors/vectors.S: Now use constants for exception numbers.
old_exception_processing/ppc_offs.h: New file.
old_exception_processing/Makefile.am: Account for ppc_offs.h.
old_exception_processing/cpu.h: Make Nest and Disable levels volatile.
old_exception_processing/cpu_asm.S: Offsets moved to ppc_offs.h.

Property mode set to 100644

File size: 13.7 KB

Line
1
2	/* cpu_asm.s 1.1 - 95/12/04
3	*
4	* This file contains the assembly code for the PowerPC implementation
5	* of RTEMS.
6	*
7	* Author: Andrew Bray <andy@i-cubed.co.uk>
8	*
9	* COPYRIGHT (c) 1995 by i-cubed ltd.
10	*
11	* To anyone who acknowledges that this file is provided "AS IS"
12	* without any express or implied warranty:
13	* permission to use, copy, modify, and distribute this file
14	* for any purpose is hereby granted without fee, provided that
15	* the above copyright notice and this notice appears in all
16	* copies, and that the name of i-cubed limited not be used in
17	* advertising or publicity pertaining to distribution of the
18	* software without specific, written prior permission.
19	* i-cubed limited makes no representations about the suitability
20	* of this software for any purpose.
21	*
22	* Derived from c/src/exec/cpu/no_cpu/cpu_asm.c:
23	*
24	* COPYRIGHT (c) 1989-1997.
25	* On-Line Applications Research Corporation (OAR).
26	* Copyright assigned to U.S. Government, 1994.
27	*
28	* The license and distribution terms for this file may in
29	* the file LICENSE in this distribution or at
30	* http://www.OARcorp.com/rtems/license.html.
31	*
32	* $Id$
33	*/
34
35	#include <asm.h>
36	#include "ppc_offs.h"
37
38	BEGIN_CODE
39	/*
40	* _CPU_Context_save_fp_context
41	*
42	* This routine is responsible for saving the FP context
43	* at *fp_context_ptr. If the point to load the FP context
44	* from is changed then the pointer is modified by this routine.
45	*
46	* Sometimes a macro implementation of this is in cpu.h which dereferences
47	* the ** and a similarly named routine in this file is passed something
48	* like a (Context_Control_fp *). The general rule on making this decision
49	* is to avoid writing assembly language.
50	*/
51
52	ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
53	PUBLIC_PROC (_CPU_Context_save_fp)
54	PROC (_CPU_Context_save_fp):
55	#if (PPC_HAS_FPU == 1)
56	lwz r3, 0(r3)
57	#if (PPC_HAS_DOUBLE == 1)
58	stfd f0, FP_0(r3)
59	stfd f1, FP_1(r3)
60	stfd f2, FP_2(r3)
61	stfd f3, FP_3(r3)
62	stfd f4, FP_4(r3)
63	stfd f5, FP_5(r3)
64	stfd f6, FP_6(r3)
65	stfd f7, FP_7(r3)
66	stfd f8, FP_8(r3)
67	stfd f9, FP_9(r3)
68	stfd f10, FP_10(r3)
69	stfd f11, FP_11(r3)
70	stfd f12, FP_12(r3)
71	stfd f13, FP_13(r3)
72	stfd f14, FP_14(r3)
73	stfd f15, FP_15(r3)
74	stfd f16, FP_16(r3)
75	stfd f17, FP_17(r3)
76	stfd f18, FP_18(r3)
77	stfd f19, FP_19(r3)
78	stfd f20, FP_20(r3)
79	stfd f21, FP_21(r3)
80	stfd f22, FP_22(r3)
81	stfd f23, FP_23(r3)
82	stfd f24, FP_24(r3)
83	stfd f25, FP_25(r3)
84	stfd f26, FP_26(r3)
85	stfd f27, FP_27(r3)
86	stfd f28, FP_28(r3)
87	stfd f29, FP_29(r3)
88	stfd f30, FP_30(r3)
89	stfd f31, FP_31(r3)
90	mffs f2
91	stfd f2, FP_FPSCR(r3)
92	#else
93	stfs f0, FP_0(r3)
94	stfs f1, FP_1(r3)
95	stfs f2, FP_2(r3)
96	stfs f3, FP_3(r3)
97	stfs f4, FP_4(r3)
98	stfs f5, FP_5(r3)
99	stfs f6, FP_6(r3)
100	stfs f7, FP_7(r3)
101	stfs f8, FP_8(r3)
102	stfs f9, FP_9(r3)
103	stfs f10, FP_10(r3)
104	stfs f11, FP_11(r3)
105	stfs f12, FP_12(r3)
106	stfs f13, FP_13(r3)
107	stfs f14, FP_14(r3)
108	stfs f15, FP_15(r3)
109	stfs f16, FP_16(r3)
110	stfs f17, FP_17(r3)
111	stfs f18, FP_18(r3)
112	stfs f19, FP_19(r3)
113	stfs f20, FP_20(r3)
114	stfs f21, FP_21(r3)
115	stfs f22, FP_22(r3)
116	stfs f23, FP_23(r3)
117	stfs f24, FP_24(r3)
118	stfs f25, FP_25(r3)
119	stfs f26, FP_26(r3)
120	stfs f27, FP_27(r3)
121	stfs f28, FP_28(r3)
122	stfs f29, FP_29(r3)
123	stfs f30, FP_30(r3)
124	stfs f31, FP_31(r3)
125	mffs f2
126	stfs f2, FP_FPSCR(r3)
127	#endif
128	#endif
129	blr
130
131	/*
132	* _CPU_Context_restore_fp_context
133	*
134	* This routine is responsible for restoring the FP context
135	* at *fp_context_ptr. If the point to load the FP context
136	* from is changed then the pointer is modified by this routine.
137	*
138	* Sometimes a macro implementation of this is in cpu.h which dereferences
139	* the ** and a similarly named routine in this file is passed something
140	* like a (Context_Control_fp *). The general rule on making this decision
141	* is to avoid writing assembly language.
142	*/
143
144	ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
145	PUBLIC_PROC (_CPU_Context_restore_fp)
146	PROC (_CPU_Context_restore_fp):
147	#if (PPC_HAS_FPU == 1)
148	lwz r3, 0(r3)
149	#if (PPC_HAS_DOUBLE == 1)
150	lfd f2, FP_FPSCR(r3)
151	mtfsf 255, f2
152	lfd f0, FP_0(r3)
153	lfd f1, FP_1(r3)
154	lfd f2, FP_2(r3)
155	lfd f3, FP_3(r3)
156	lfd f4, FP_4(r3)
157	lfd f5, FP_5(r3)
158	lfd f6, FP_6(r3)
159	lfd f7, FP_7(r3)
160	lfd f8, FP_8(r3)
161	lfd f9, FP_9(r3)
162	lfd f10, FP_10(r3)
163	lfd f11, FP_11(r3)
164	lfd f12, FP_12(r3)
165	lfd f13, FP_13(r3)
166	lfd f14, FP_14(r3)
167	lfd f15, FP_15(r3)
168	lfd f16, FP_16(r3)
169	lfd f17, FP_17(r3)
170	lfd f18, FP_18(r3)
171	lfd f19, FP_19(r3)
172	lfd f20, FP_20(r3)
173	lfd f21, FP_21(r3)
174	lfd f22, FP_22(r3)
175	lfd f23, FP_23(r3)
176	lfd f24, FP_24(r3)
177	lfd f25, FP_25(r3)
178	lfd f26, FP_26(r3)
179	lfd f27, FP_27(r3)
180	lfd f28, FP_28(r3)
181	lfd f29, FP_29(r3)
182	lfd f30, FP_30(r3)
183	lfd f31, FP_31(r3)
184	#else
185	lfs f2, FP_FPSCR(r3)
186	mtfsf 255, f2
187	lfs f0, FP_0(r3)
188	lfs f1, FP_1(r3)
189	lfs f2, FP_2(r3)
190	lfs f3, FP_3(r3)
191	lfs f4, FP_4(r3)
192	lfs f5, FP_5(r3)
193	lfs f6, FP_6(r3)
194	lfs f7, FP_7(r3)
195	lfs f8, FP_8(r3)
196	lfs f9, FP_9(r3)
197	lfs f10, FP_10(r3)
198	lfs f11, FP_11(r3)
199	lfs f12, FP_12(r3)
200	lfs f13, FP_13(r3)
201	lfs f14, FP_14(r3)
202	lfs f15, FP_15(r3)
203	lfs f16, FP_16(r3)
204	lfs f17, FP_17(r3)
205	lfs f18, FP_18(r3)
206	lfs f19, FP_19(r3)
207	lfs f20, FP_20(r3)
208	lfs f21, FP_21(r3)
209	lfs f22, FP_22(r3)
210	lfs f23, FP_23(r3)
211	lfs f24, FP_24(r3)
212	lfs f25, FP_25(r3)
213	lfs f26, FP_26(r3)
214	lfs f27, FP_27(r3)
215	lfs f28, FP_28(r3)
216	lfs f29, FP_29(r3)
217	lfs f30, FP_30(r3)
218	lfs f31, FP_31(r3)
219	#endif
220	#endif
221	blr
222
223
224	/* _CPU_Context_switch
225	*
226	* This routine performs a normal non-FP context switch.
227	*/
228	ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
229	PUBLIC_PROC (_CPU_Context_switch)
230	PROC (_CPU_Context_switch):
231	sync
232	isync
233	#if (PPC_CACHE_ALIGNMENT == 4) /* No cache */
234	stw r1, GP_1(r3)
235	lwz r1, GP_1(r4)
236	stw r2, GP_2(r3)
237	lwz r2, GP_2(r4)
238	#if (PPC_USE_MULTIPLE == 1)
239	stmw r13, GP_13(r3)
240	lmw r13, GP_13(r4)
241	#else
242	stw r13, GP_13(r3)
243	lwz r13, GP_13(r4)
244	stw r14, GP_14(r3)
245	lwz r14, GP_14(r4)
246	stw r15, GP_15(r3)
247	lwz r15, GP_15(r4)
248	stw r16, GP_16(r3)
249	lwz r16, GP_16(r4)
250	stw r17, GP_17(r3)
251	lwz r17, GP_17(r4)
252	stw r18, GP_18(r3)
253	lwz r18, GP_18(r4)
254	stw r19, GP_19(r3)
255	lwz r19, GP_19(r4)
256	stw r20, GP_20(r3)
257	lwz r20, GP_20(r4)
258	stw r21, GP_21(r3)
259	lwz r21, GP_21(r4)
260	stw r22, GP_22(r3)
261	lwz r22, GP_22(r4)
262	stw r23, GP_23(r3)
263	lwz r23, GP_23(r4)
264	stw r24, GP_24(r3)
265	lwz r24, GP_24(r4)
266	stw r25, GP_25(r3)
267	lwz r25, GP_25(r4)
268	stw r26, GP_26(r3)
269	lwz r26, GP_26(r4)
270	stw r27, GP_27(r3)
271	lwz r27, GP_27(r4)
272	stw r28, GP_28(r3)
273	lwz r28, GP_28(r4)
274	stw r29, GP_29(r3)
275	lwz r29, GP_29(r4)
276	stw r30, GP_30(r3)
277	lwz r30, GP_30(r4)
278	stw r31, GP_31(r3)
279	lwz r31, GP_31(r4)
280	#endif
281	mfcr r5
282	stw r5, GP_CR(r3)
283	lwz r5, GP_CR(r4)
284	mflr r6
285	mtcrf 255, r5
286	stw r6, GP_PC(r3)
287	lwz r6, GP_PC(r4)
288	mfmsr r7
289	mtlr r6
290	stw r7, GP_MSR(r3)
291	lwz r7, GP_MSR(r4)
292	mtmsr r7
293	#endif
294	#if (PPC_CACHE_ALIGNMENT == 16)
295	/* This assumes that all the registers are in the given order */
296	li r5, 16
297	addi r3,r3,-4
298	#if ( PPC_USE_DATA_CACHE )
299	dcbz r5, r3
300	#endif
301	stw r1, GP_1+4(r3)
302	stw r2, GP_2+4(r3)
303	#if (PPC_USE_MULTIPLE == 1)
304	addi r3, r3, GP_14+4
305	#if ( PPC_USE_DATA_CACHE )
306	dcbz r5, r3
307	#endif
308
309	addi r3, r3, GP_18-GP_14
310	#if ( PPC_USE_DATA_CACHE )
311	dcbz r5, r3
312	#endif
313	addi r3, r3, GP_22-GP_18
314	#if ( PPC_USE_DATA_CACHE )
315	dcbz r5, r3
316	#endif
317	addi r3, r3, GP_26-GP_22
318	#if ( PPC_USE_DATA_CACHE )
319	dcbz r5, r3
320	#endif
321	stmw r13, GP_13-GP_26(r3)
322	#else
323	stw r13, GP_13+4(r3)
324	stwu r14, GP_14+4(r3)
325	#if ( PPC_USE_DATA_CACHE )
326	dcbz r5, r3
327	#endif
328	stw r15, GP_15-GP_14(r3)
329	stw r16, GP_16-GP_14(r3)
330	stw r17, GP_17-GP_14(r3)
331	stwu r18, GP_18-GP_14(r3)
332	#if ( PPC_USE_DATA_CACHE )
333	dcbz r5, r3
334	#endif
335	stw r19, GP_19-GP_18(r3)
336	stw r20, GP_20-GP_18(r3)
337	stw r21, GP_21-GP_18(r3)
338	stwu r22, GP_22-GP_18(r3)
339	#if ( PPC_USE_DATA_CACHE )
340	dcbz r5, r3
341	#endif
342	stw r23, GP_23-GP_22(r3)
343	stw r24, GP_24-GP_22(r3)
344	stw r25, GP_25-GP_22(r3)
345	stwu r26, GP_26-GP_22(r3)
346	#if ( PPC_USE_DATA_CACHE )
347	dcbz r5, r3
348	#endif
349	stw r27, GP_27-GP_26(r3)
350	stw r28, GP_28-GP_26(r3)
351	stw r29, GP_29-GP_26(r3)
352	stw r30, GP_30-GP_26(r3)
353	stw r31, GP_31-GP_26(r3)
354	#endif
355	#if ( PPC_USE_DATA_CACHE )
356	dcbt r0, r4
357	#endif
358	mfcr r6
359	stw r6, GP_CR-GP_26(r3)
360	mflr r7
361	stw r7, GP_PC-GP_26(r3)
362	mfmsr r8
363	stw r8, GP_MSR-GP_26(r3)
364
365	#if ( PPC_USE_DATA_CACHE )
366	dcbt r5, r4
367	#endif
368	lwz r1, GP_1(r4)
369	lwz r2, GP_2(r4)
370	#if (PPC_USE_MULTIPLE == 1)
371	addi r4, r4, GP_15
372	#if ( PPC_USE_DATA_CACHE )
373	dcbt r5, r4
374	#endif
375	addi r4, r4, GP_19-GP_15
376	#if ( PPC_USE_DATA_CACHE )
377	dcbt r5, r4
378	#endif
379	addi r4, r4, GP_23-GP_19
380	#if ( PPC_USE_DATA_CACHE )
381	dcbt r5, r4
382	#endif
383	addi r4, r4, GP_27-GP_23
384	#if ( PPC_USE_DATA_CACHE )
385	dcbt r5, r4
386	#endif
387	lmw r13, GP_13-GP_27(r4)
388	#else
389	lwz r13, GP_13(r4)
390	lwz r14, GP_14(r4)
391	lwzu r15, GP_15(r4)
392	#if ( PPC_USE_DATA_CACHE )
393	dcbt r5, r4
394	#endif
395	lwz r16, GP_16-GP_15(r4)
396	lwz r17, GP_17-GP_15(r4)
397	lwz r18, GP_18-GP_15(r4)
398	lwzu r19, GP_19-GP_15(r4)
399	#if ( PPC_USE_DATA_CACHE )
400	dcbt r5, r4
401	#endif
402	lwz r20, GP_20-GP_19(r4)
403	lwz r21, GP_21-GP_19(r4)
404	lwz r22, GP_22-GP_19(r4)
405	lwzu r23, GP_23-GP_19(r4)
406	#if ( PPC_USE_DATA_CACHE )
407	dcbt r5, r4
408	#endif
409	lwz r24, GP_24-GP_23(r4)
410	lwz r25, GP_25-GP_23(r4)
411	lwz r26, GP_26-GP_23(r4)
412	lwzu r27, GP_27-GP_23(r4)
413	#if ( PPC_USE_DATA_CACHE )
414	dcbt r5, r4
415	#endif
416	lwz r28, GP_28-GP_27(r4)
417	lwz r29, GP_29-GP_27(r4)
418	lwz r30, GP_30-GP_27(r4)
419	lwz r31, GP_31-GP_27(r4)
420	#endif
421	lwz r6, GP_CR-GP_27(r4)
422	lwz r7, GP_PC-GP_27(r4)
423	lwz r8, GP_MSR-GP_27(r4)
424	mtcrf 255, r6
425	mtlr r7
426	mtmsr r8
427	#endif
428	#if (PPC_CACHE_ALIGNMENT == 32)
429	/* This assumes that all the registers are in the given order */
430	li r5, 32
431	addi r3,r3,-4
432	#if ( PPC_USE_DATA_CACHE )
433	dcbz r5, r3
434	#endif
435	stw r1, GP_1+4(r3)
436	stw r2, GP_2+4(r3)
437	#if (PPC_USE_MULTIPLE == 1)
438	addi r3, r3, GP_18+4
439	#if ( PPC_USE_DATA_CACHE )
440	dcbz r5, r3
441	#endif
442	stmw r13, GP_13-GP_18(r3)
443	#else
444	stw r13, GP_13+4(r3)
445	stw r14, GP_14+4(r3)
446	stw r15, GP_15+4(r3)
447	stw r16, GP_16+4(r3)
448	stw r17, GP_17+4(r3)
449	stwu r18, GP_18+4(r3)
450	#if ( PPC_USE_DATA_CACHE )
451	dcbz r5, r3
452	#endif
453	stw r19, GP_19-GP_18(r3)
454	stw r20, GP_20-GP_18(r3)
455	stw r21, GP_21-GP_18(r3)
456	stw r22, GP_22-GP_18(r3)
457	stw r23, GP_23-GP_18(r3)
458	stw r24, GP_24-GP_18(r3)
459	stw r25, GP_25-GP_18(r3)
460	stw r26, GP_26-GP_18(r3)
461	stw r27, GP_27-GP_18(r3)
462	stw r28, GP_28-GP_18(r3)
463	stw r29, GP_29-GP_18(r3)
464	stw r30, GP_30-GP_18(r3)
465	stw r31, GP_31-GP_18(r3)
466	#endif
467	#if ( PPC_USE_DATA_CACHE )
468	dcbt r0, r4
469	#endif
470	mfcr r6
471	stw r6, GP_CR-GP_18(r3)
472	mflr r7
473	stw r7, GP_PC-GP_18(r3)
474	mfmsr r8
475	stw r8, GP_MSR-GP_18(r3)
476
477	#if ( PPC_USE_DATA_CACHE )
478	dcbt r5, r4
479	#endif
480	lwz r1, GP_1(r4)
481	lwz r2, GP_2(r4)
482	#if (PPC_USE_MULTIPLE == 1)
483	addi r4, r4, GP_19
484	#if ( PPC_USE_DATA_CACHE )
485	dcbt r5, r4
486	#endif
487	lmw r13, GP_13-GP_19(r4)
488	#else
489	lwz r13, GP_13(r4)
490	lwz r14, GP_14(r4)
491	lwz r15, GP_15(r4)
492	lwz r16, GP_16(r4)
493	lwz r17, GP_17(r4)
494	lwz r18, GP_18(r4)
495	lwzu r19, GP_19(r4)
496	#if ( PPC_USE_DATA_CACHE )
497	dcbt r5, r4
498	#endif
499	lwz r20, GP_20-GP_19(r4)
500	lwz r21, GP_21-GP_19(r4)
501	lwz r22, GP_22-GP_19(r4)
502	lwz r23, GP_23-GP_19(r4)
503	lwz r24, GP_24-GP_19(r4)
504	lwz r25, GP_25-GP_19(r4)
505	lwz r26, GP_26-GP_19(r4)
506	lwz r27, GP_27-GP_19(r4)
507	lwz r28, GP_28-GP_19(r4)
508	lwz r29, GP_29-GP_19(r4)
509	lwz r30, GP_30-GP_19(r4)
510	lwz r31, GP_31-GP_19(r4)
511	#endif
512	lwz r6, GP_CR-GP_19(r4)
513	lwz r7, GP_PC-GP_19(r4)
514	lwz r8, GP_MSR-GP_19(r4)
515	mtcrf 255, r6
516	mtlr r7
517	mtmsr r8
518	#endif
519	blr
520
521	/*
522	* _CPU_Context_restore
523	*
524	* This routine is generallu used only to restart self in an
525	* efficient manner. It may simply be a label in _CPU_Context_switch.
526	*
527	* NOTE: May be unnecessary to reload some registers.
528	*/
529	/*
530	* ACB: Don't worry about cache optimisation here - this is not THAT critical.
531	*/
532	ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
533	PUBLIC_PROC (_CPU_Context_restore)
534	PROC (_CPU_Context_restore):
535	lwz r5, GP_CR(r3)
536	lwz r6, GP_PC(r3)
537	lwz r7, GP_MSR(r3)
538	mtcrf 255, r5
539	mtlr r6
540	mtmsr r7
541	lwz r1, GP_1(r3)
542	lwz r2, GP_2(r3)
543	#if (PPC_USE_MULTIPLE == 1)
544	lmw r13, GP_13(r3)
545	#else
546	lwz r13, GP_13(r3)
547	lwz r14, GP_14(r3)
548	lwz r15, GP_15(r3)
549	lwz r16, GP_16(r3)
550	lwz r17, GP_17(r3)
551	lwz r18, GP_18(r3)
552	lwz r19, GP_19(r3)
553	lwz r20, GP_20(r3)
554	lwz r21, GP_21(r3)
555	lwz r22, GP_22(r3)
556	lwz r23, GP_23(r3)
557	lwz r24, GP_24(r3)
558	lwz r25, GP_25(r3)
559	lwz r26, GP_26(r3)
560	lwz r27, GP_27(r3)
561	lwz r28, GP_28(r3)
562	lwz r29, GP_29(r3)
563	lwz r30, GP_30(r3)
564	lwz r31, GP_31(r3)
565	#endif
566
567	blr
568
569	/* Individual interrupt prologues look like this:
570	* #if (PPC_ABI == PPC_ABI_POWEROPEN \|\| PPC_ABI == PPC_ABI_GCC27)
571	* #if (PPC_HAS_FPU)
572	* stwu r1, -(204 + 188 + IP_END)(r1)
573	* #else
574	* stwu r1, -(20*4 + IP_END)(r1)
575	* #endif
576	* #else
577	* stwu r1, -(IP_END)(r1)
578	* #endif
579	* stw r0, IP_0(r1)
580	*
581	* li r0, vectornum
582	* b PROC (_ISR_Handler{,C})
583	*/
584
585	/* void __ISR_Handler()
586	*
587	* This routine provides the RTEMS interrupt management.
588	* The vector number is in r0. R0 has already been stacked.
589	*
590	*/
591	ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
592	PUBLIC_PROC (_ISR_Handler)
593	PROC (_ISR_Handler):
594	#define LABEL(x) x
595	/* XXX ??
596	#define MTSAVE(x) mtspr sprg0, x
597	#define MFSAVE(x) mfspr x, sprg0
598	*/
599	#define MTPC(x) mtspr srr0, x
600	#define MFPC(x) mfspr x, srr0
601	#define MTMSR(x) mtspr srr1, x
602	#define MFMSR(x) mfspr x, srr1
603
604	#include "irq_stub.S"
605	rfi
606
607	#if (PPC_HAS_RFCI == 1)
608	/* void __ISR_HandlerC()
609	*
610	* This routine provides the RTEMS interrupt management.
611	* For critical interrupts
612	*
613	*/
614	ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER)
615	PUBLIC_PROC (_ISR_HandlerC)
616	PROC (_ISR_HandlerC):
617	#undef LABEL
618	#undef MTSAVE
619	#undef MFSAVE
620	#undef MTPC
621	#undef MFPC
622	#undef MTMSR
623	#undef MFMSR
624	#define LABEL(x) x##_C
625	/* XXX??
626	#define MTSAVE(x) mtspr sprg1, x
627	#define MFSAVE(x) mfspr x, sprg1
628	*/
629	#define MTPC(x) mtspr srr2, x
630	#define MFPC(x) mfspr x, srr2
631	#define MTMSR(x) mtspr srr3, x
632	#define MFMSR(x) mfspr x, srr3
633	#include "irq_stub.S"
634	rfci
635	#endif
636
637	/* PowerOpen descriptors for indirect function calls.
638	*/
639
640	#if (PPC_ABI == PPC_ABI_POWEROPEN)
641	DESCRIPTOR (_CPU_Context_save_fp)
642	DESCRIPTOR (_CPU_Context_restore_fp)
643	DESCRIPTOR (_CPU_Context_switch)
644	DESCRIPTOR (_CPU_Context_restore)
645	DESCRIPTOR (_ISR_Handler)
646	#if (PPC_HAS_RFCI == 1)
647	DESCRIPTOR (_ISR_HandlerC)
648	#endif
649	#endif

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