source: rtems/c/src/lib/libcpu/powerpc/old-exceptions/ppccache.c @ d3d9ef37

4.104.114.84.95
Last change on this file since d3d9ef37 was f05b2ac, checked in by Ralf Corsepius <ralf.corsepius@…>, on Apr 21, 2004 at 4:01:48 PM

Remove duplicate white lines.

  • Property mode set to 100644
File size: 990 bytes
Line 
1/*
2 *  PowerPC Cache enable routines
3 *
4 *  $Id$
5 */
6
7#include <rtems/system.h>
8
9#define PPC_Get_HID0( _value ) \
10  do { \
11      _value = 0;        /* to avoid warnings */ \
12      asm volatile( \
13          "mfspr %0, 0x3f0;"     /* get HID0 */ \
14          "isync" \
15          : "=r" (_value) \
16          : "0" (_value) \
17      ); \
18  } while (0)
19
20#define PPC_Set_HID0( _value ) \
21  do { \
22      asm volatile( \
23          "isync;" \
24          "mtspr 0x3f0, %0;"     /* load HID0 */ \
25          "isync" \
26          : "=r" (_value) \
27          : "0" (_value) \
28      ); \
29  } while (0)
30
31void powerpc_instruction_cache_enable ()
32{
33  uint32_t   value;
34
35  /*
36   * Enable the instruction cache
37   */
38
39  PPC_Get_HID0( value );
40
41  value |= 0x00008000;       /* Set ICE bit */
42
43  PPC_Set_HID0( value );
44}
45
46void powerpc_data_cache_enable ()
47{
48  uint32_t   value;
49
50  /*
51   * enable data cache
52   */
53
54  PPC_Get_HID0( value );
55
56  value |= 0x00004000;        /* set DCE bit */
57
58  PPC_Set_HID0( value );
59}
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