[acc25ee] | 1 | /* |
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| 2 | * This file contains the interrupt handler assembly code for the PowerPC |
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| 3 | * implementation of RTEMS. It is #included from cpu_asm.s. |
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| 4 | * |
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| 5 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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| 6 | * |
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| 7 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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| 8 | * |
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| 9 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 10 | * without any express or implied warranty: |
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| 11 | * permission to use, copy, modify, and distribute this file |
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| 12 | * for any purpose is hereby granted without fee, provided that |
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| 13 | * the above copyright notice and this notice appears in all |
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| 14 | * copies, and that the name of i-cubed limited not be used in |
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| 15 | * advertising or publicity pertaining to distribution of the |
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| 16 | * software without specific, written prior permission. |
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| 17 | * i-cubed limited makes no representations about the suitability |
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| 18 | * of this software for any purpose. |
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| 19 | * |
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| 20 | * $Id$ |
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| 21 | */ |
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| 22 | |
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[39fb164] | 23 | /* |
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| 24 | * FIXME: this file is bsp dependent. |
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| 25 | */ |
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| 26 | #include <bspopts.h> |
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[3e5a93cc] | 27 | #include <rtems/powerpc/powerpc.h> |
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[39fb164] | 28 | |
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[acc25ee] | 29 | /* void __ISR_Handler() |
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| 30 | * |
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| 31 | * This routine provides the RTEMS interrupt management. |
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| 32 | * The vector number is in r0. R0 has already been stacked. |
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| 33 | * |
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| 34 | */ |
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| 35 | PUBLIC_VAR (_CPU_IRQ_info ) |
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| 36 | |
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| 37 | /* Finish off the interrupt frame */ |
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| 38 | stw r2, IP_2(r1) |
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| 39 | stw r3, IP_3(r1) |
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| 40 | stw r4, IP_4(r1) |
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| 41 | stw r5, IP_5(r1) |
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| 42 | stw r6, IP_6(r1) |
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| 43 | stw r7, IP_7(r1) |
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| 44 | stw r8, IP_8(r1) |
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| 45 | stw r9, IP_9(r1) |
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| 46 | stw r10, IP_10(r1) |
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| 47 | stw r11, IP_11(r1) |
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| 48 | stw r12, IP_12(r1) |
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| 49 | stw r13, IP_13(r1) |
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| 50 | stmw r28, IP_28(r1) |
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| 51 | mfcr r5 |
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| 52 | mfctr r6 |
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| 53 | mfxer r7 |
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| 54 | mflr r8 |
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| 55 | MFPC (r9) |
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| 56 | MFMSR (r10) |
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| 57 | /* Establish addressing */ |
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| 58 | #if (PPC_USE_SPRG) |
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| 59 | mfspr r11, sprg3 |
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| 60 | #else |
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| 61 | lis r11,_CPU_IRQ_info@ha |
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| 62 | addi r11,r11,_CPU_IRQ_info@l |
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| 63 | #endif |
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[df49c60] | 64 | #if ( PPC_USE_DATA_CACHE ) |
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[acc25ee] | 65 | dcbt r0, r11 |
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[df49c60] | 66 | #endif |
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[acc25ee] | 67 | stw r5, IP_CR(r1) |
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| 68 | stw r6, IP_CTR(r1) |
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| 69 | stw r7, IP_XER(r1) |
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| 70 | stw r8, IP_LR(r1) |
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| 71 | stw r9, IP_PC(r1) |
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| 72 | stw r10, IP_MSR(r1) |
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| 73 | |
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| 74 | lwz r30, Vector_table(r11) |
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| 75 | slwi r4,r0,2 |
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| 76 | lwz r28, Nest_level(r11) |
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| 77 | add r4, r4, r30 |
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[6128a4a] | 78 | |
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[acc25ee] | 79 | lwz r30, 0(r28) |
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| 80 | mr r3, r0 |
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| 81 | lwz r31, Stack(r11) |
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| 82 | /* |
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| 83 | * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) |
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| 84 | * if ( _ISR_Nest_level == 0 ) |
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| 85 | * switch to software interrupt stack |
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| 86 | * #endif |
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| 87 | */ |
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| 88 | /* Switch stacks, here we must prevent ALL interrupts */ |
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| 89 | #if (PPC_USE_SPRG) |
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[6128a4a] | 90 | mfmsr r5 |
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| 91 | mfspr r6, sprg2 |
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| 92 | #else |
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[acc25ee] | 93 | lwz r6,msr_initial(r11) |
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| 94 | lis r5,~PPC_MSR_DISABLE_MASK@ha |
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| 95 | ori r5,r5,~PPC_MSR_DISABLE_MASK@l |
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| 96 | and r6,r6,r5 |
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[6128a4a] | 97 | mfmsr r5 |
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[acc25ee] | 98 | #endif |
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| 99 | mtmsr r6 |
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| 100 | cmpwi r30, 0 |
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| 101 | lwz r29, Disable_level(r11) |
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| 102 | subf r31,r1,r31 |
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| 103 | bne LABEL (nested) |
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| 104 | stwux r1,r1,r31 |
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| 105 | LABEL (nested): |
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| 106 | /* |
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| 107 | * _ISR_Nest_level++; |
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| 108 | */ |
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| 109 | lwz r31, 0(r29) |
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| 110 | addi r30,r30,1 |
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| 111 | stw r30,0(r28) |
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| 112 | /* From here on out, interrupts can be re-enabled. RTEMS |
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| 113 | * convention says not. |
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| 114 | */ |
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| 115 | lwz r4,0(r4) |
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| 116 | /* |
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| 117 | * _Thread_Dispatch_disable_level++; |
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| 118 | */ |
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| 119 | addi r31,r31,1 |
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| 120 | stw r31, 0(r29) |
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| 121 | /* SCE 980217 |
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| 122 | * |
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| 123 | * We need address translation ON when we call our ISR routine |
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| 124 | |
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| 125 | mtmsr r5 |
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| 126 | |
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| 127 | */ |
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| 128 | |
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| 129 | /* |
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| 130 | * (*_ISR_Vector_table[ vector ])( vector ); |
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| 131 | */ |
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| 132 | #if (PPC_ABI == PPC_ABI_SVR4 || PPC_ABI == PPC_ABI_EABI) |
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| 133 | mtlr r4 |
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| 134 | lwz r2, Default_r2(r11) |
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| 135 | lwz r13, Default_r13(r11) |
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| 136 | #lwz r2, 0(r2) |
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| 137 | #lwz r13, 0(r13) |
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| 138 | #endif |
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| 139 | mr r4,r1 |
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| 140 | blrl |
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| 141 | /* NOP marker for debuggers */ |
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| 142 | or r6,r6,r6 |
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| 143 | |
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| 144 | /* We must re-disable the interrupts */ |
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| 145 | #if (PPC_USE_SPRG) |
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| 146 | mfspr r11, sprg3 |
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[6128a4a] | 147 | mfspr r0, sprg2 |
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[acc25ee] | 148 | #else |
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| 149 | lis r11,_CPU_IRQ_info@ha |
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[6128a4a] | 150 | addi r11,r11,_CPU_IRQ_info@l |
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[acc25ee] | 151 | lwz r0,msr_initial(r11) |
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| 152 | lis r30,~PPC_MSR_DISABLE_MASK@ha |
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| 153 | ori r30,r30,~PPC_MSR_DISABLE_MASK@l |
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| 154 | and r0,r0,r30 |
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| 155 | #endif |
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| 156 | mtmsr r0 |
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| 157 | lwz r30, 0(r28) |
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| 158 | lwz r31, 0(r29) |
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| 159 | |
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| 160 | /* |
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| 161 | * if (--Thread_Dispatch_disable,--_ISR_Nest_level) |
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| 162 | * goto easy_exit; |
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| 163 | */ |
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| 164 | addi r30, r30, -1 |
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| 165 | cmpwi r30, 0 |
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| 166 | addi r31, r31, -1 |
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| 167 | stw r30, 0(r28) |
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| 168 | stw r31, 0(r29) |
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| 169 | bne LABEL (easy_exit) |
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| 170 | cmpwi r31, 0 |
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| 171 | |
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| 172 | lwz r30, Switch_necessary(r11) |
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| 173 | |
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| 174 | /* |
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| 175 | * #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE ) |
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| 176 | * restore stack |
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| 177 | * #endif |
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| 178 | */ |
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| 179 | lwz r1,0(r1) |
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| 180 | bne LABEL (easy_exit) |
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| 181 | lwz r30, 0(r30) |
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| 182 | lwz r31, Signal(r11) |
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[6128a4a] | 183 | |
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| 184 | /* |
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[acc25ee] | 185 | * if ( _Context_Switch_necessary ) |
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| 186 | * goto switch |
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| 187 | */ |
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| 188 | cmpwi r30, 0 |
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| 189 | lwz r28, 0(r31) |
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| 190 | li r6,0 |
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| 191 | bne LABEL (switch) |
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[6128a4a] | 192 | /* |
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[acc25ee] | 193 | * if ( !_ISR_Signals_to_thread_executing ) |
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| 194 | * goto easy_exit |
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| 195 | * _ISR_Signals_to_thread_executing = 0; |
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| 196 | */ |
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| 197 | cmpwi r28, 0 |
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| 198 | beq LABEL (easy_exit) |
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| 199 | |
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| 200 | /* |
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| 201 | * switch: |
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| 202 | * call _Thread_Dispatch() or prepare to return to _ISR_Dispatch |
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| 203 | */ |
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| 204 | LABEL (switch): |
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| 205 | stw r6, 0(r31) |
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| 206 | /* Re-enable interrupts */ |
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| 207 | lwz r0, IP_MSR(r1) |
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| 208 | /* R2 and R13 still hold their values from the last call */ |
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| 209 | mtmsr r0 |
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| 210 | bl SYM (_Thread_Dispatch) |
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| 211 | /* NOP marker for debuggers */ |
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| 212 | or r6,r6,r6 |
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| 213 | /* |
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| 214 | * prepare to get out of interrupt |
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| 215 | */ |
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| 216 | /* Re-disable IRQs */ |
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| 217 | #if (PPC_USE_SPRG) |
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| 218 | mfspr r0, sprg2 |
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| 219 | #else |
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| 220 | lis r11,_CPU_IRQ_info@ha |
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[6128a4a] | 221 | addi r11,r11,_CPU_IRQ_info@l |
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[acc25ee] | 222 | lwz r0,msr_initial(r11) |
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| 223 | lis r5,~PPC_MSR_DISABLE_MASK@ha |
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| 224 | ori r5,r5,~PPC_MSR_DISABLE_MASK@l |
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| 225 | and r0,r0,r5 |
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| 226 | #endif |
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| 227 | mtmsr r0 |
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[6128a4a] | 228 | |
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[acc25ee] | 229 | /* |
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| 230 | * easy_exit: |
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| 231 | * prepare to get out of interrupt |
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| 232 | * return from interrupt |
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| 233 | */ |
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| 234 | LABEL (easy_exit): |
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| 235 | lwz r5, IP_CR(r1) |
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| 236 | lwz r6, IP_CTR(r1) |
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| 237 | lwz r7, IP_XER(r1) |
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| 238 | lwz r8, IP_LR(r1) |
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| 239 | lwz r9, IP_PC(r1) |
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| 240 | lwz r10, IP_MSR(r1) |
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| 241 | mtcrf 255,r5 |
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| 242 | mtctr r6 |
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| 243 | mtxer r7 |
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| 244 | mtlr r8 |
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| 245 | MTPC (r9) |
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| 246 | MTMSR (r10) |
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| 247 | lwz r0, IP_0(r1) |
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| 248 | lwz r2, IP_2(r1) |
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| 249 | lwz r3, IP_3(r1) |
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| 250 | lwz r4, IP_4(r1) |
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| 251 | lwz r5, IP_5(r1) |
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| 252 | lwz r6, IP_6(r1) |
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| 253 | lwz r7, IP_7(r1) |
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| 254 | lwz r8, IP_8(r1) |
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| 255 | lwz r9, IP_9(r1) |
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| 256 | lwz r10, IP_10(r1) |
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| 257 | lwz r11, IP_11(r1) |
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| 258 | lwz r12, IP_12(r1) |
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| 259 | lwz r13, IP_13(r1) |
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| 260 | lmw r28, IP_28(r1) |
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| 261 | lwz r1, 0(r1) |
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