[acc25ee] | 1 | |
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| 2 | /* cpu_asm.s 1.1 - 95/12/04 |
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| 3 | * |
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| 4 | * This file contains the assembly code for the PowerPC implementation |
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| 5 | * of RTEMS. |
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| 6 | * |
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| 7 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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| 8 | * |
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| 9 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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| 10 | * |
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| 11 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 12 | * without any express or implied warranty: |
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| 13 | * permission to use, copy, modify, and distribute this file |
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| 14 | * for any purpose is hereby granted without fee, provided that |
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| 15 | * the above copyright notice and this notice appears in all |
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| 16 | * copies, and that the name of i-cubed limited not be used in |
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| 17 | * advertising or publicity pertaining to distribution of the |
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| 18 | * software without specific, written prior permission. |
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| 19 | * i-cubed limited makes no representations about the suitability |
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| 20 | * of this software for any purpose. |
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| 21 | * |
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| 22 | * Derived from c/src/exec/cpu/no_cpu/cpu_asm.c: |
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| 23 | * |
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| 24 | * COPYRIGHT (c) 1989-1997. |
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| 25 | * On-Line Applications Research Corporation (OAR). |
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| 26 | * Copyright assigned to U.S. Government, 1994. |
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| 27 | * |
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| 28 | * The license and distribution terms for this file may in |
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| 29 | * the file LICENSE in this distribution or at |
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| 30 | * http://www.OARcorp.com/rtems/license.html. |
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| 31 | * |
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| 32 | * $Id$ |
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| 33 | */ |
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| 34 | |
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| 35 | #include <asm.h> |
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| 36 | |
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| 37 | /* |
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| 38 | * Offsets for various Contexts |
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| 39 | */ |
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| 40 | .set GP_1, 0 |
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| 41 | .set GP_2, (GP_1 + 4) |
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| 42 | .set GP_13, (GP_2 + 4) |
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| 43 | .set GP_14, (GP_13 + 4) |
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| 44 | |
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| 45 | .set GP_15, (GP_14 + 4) |
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| 46 | .set GP_16, (GP_15 + 4) |
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| 47 | .set GP_17, (GP_16 + 4) |
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| 48 | .set GP_18, (GP_17 + 4) |
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| 49 | |
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| 50 | .set GP_19, (GP_18 + 4) |
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| 51 | .set GP_20, (GP_19 + 4) |
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| 52 | .set GP_21, (GP_20 + 4) |
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| 53 | .set GP_22, (GP_21 + 4) |
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| 54 | |
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| 55 | .set GP_23, (GP_22 + 4) |
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| 56 | .set GP_24, (GP_23 + 4) |
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| 57 | .set GP_25, (GP_24 + 4) |
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| 58 | .set GP_26, (GP_25 + 4) |
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| 59 | |
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| 60 | .set GP_27, (GP_26 + 4) |
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| 61 | .set GP_28, (GP_27 + 4) |
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| 62 | .set GP_29, (GP_28 + 4) |
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| 63 | .set GP_30, (GP_29 + 4) |
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| 64 | |
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| 65 | .set GP_31, (GP_30 + 4) |
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| 66 | .set GP_CR, (GP_31 + 4) |
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| 67 | .set GP_PC, (GP_CR + 4) |
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| 68 | .set GP_MSR, (GP_PC + 4) |
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| 69 | |
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| 70 | #if (PPC_HAS_DOUBLE == 1) |
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| 71 | .set FP_0, 0 |
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| 72 | .set FP_1, (FP_0 + 8) |
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| 73 | .set FP_2, (FP_1 + 8) |
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| 74 | .set FP_3, (FP_2 + 8) |
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| 75 | .set FP_4, (FP_3 + 8) |
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| 76 | .set FP_5, (FP_4 + 8) |
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| 77 | .set FP_6, (FP_5 + 8) |
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| 78 | .set FP_7, (FP_6 + 8) |
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| 79 | .set FP_8, (FP_7 + 8) |
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| 80 | .set FP_9, (FP_8 + 8) |
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| 81 | .set FP_10, (FP_9 + 8) |
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| 82 | .set FP_11, (FP_10 + 8) |
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| 83 | .set FP_12, (FP_11 + 8) |
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| 84 | .set FP_13, (FP_12 + 8) |
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| 85 | .set FP_14, (FP_13 + 8) |
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| 86 | .set FP_15, (FP_14 + 8) |
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| 87 | .set FP_16, (FP_15 + 8) |
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| 88 | .set FP_17, (FP_16 + 8) |
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| 89 | .set FP_18, (FP_17 + 8) |
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| 90 | .set FP_19, (FP_18 + 8) |
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| 91 | .set FP_20, (FP_19 + 8) |
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| 92 | .set FP_21, (FP_20 + 8) |
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| 93 | .set FP_22, (FP_21 + 8) |
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| 94 | .set FP_23, (FP_22 + 8) |
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| 95 | .set FP_24, (FP_23 + 8) |
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| 96 | .set FP_25, (FP_24 + 8) |
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| 97 | .set FP_26, (FP_25 + 8) |
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| 98 | .set FP_27, (FP_26 + 8) |
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| 99 | .set FP_28, (FP_27 + 8) |
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| 100 | .set FP_29, (FP_28 + 8) |
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| 101 | .set FP_30, (FP_29 + 8) |
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| 102 | .set FP_31, (FP_30 + 8) |
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| 103 | .set FP_FPSCR, (FP_31 + 8) |
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| 104 | #else |
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| 105 | .set FP_0, 0 |
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| 106 | .set FP_1, (FP_0 + 4) |
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| 107 | .set FP_2, (FP_1 + 4) |
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| 108 | .set FP_3, (FP_2 + 4) |
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| 109 | .set FP_4, (FP_3 + 4) |
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| 110 | .set FP_5, (FP_4 + 4) |
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| 111 | .set FP_6, (FP_5 + 4) |
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| 112 | .set FP_7, (FP_6 + 4) |
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| 113 | .set FP_8, (FP_7 + 4) |
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| 114 | .set FP_9, (FP_8 + 4) |
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| 115 | .set FP_10, (FP_9 + 4) |
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| 116 | .set FP_11, (FP_10 + 4) |
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| 117 | .set FP_12, (FP_11 + 4) |
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| 118 | .set FP_13, (FP_12 + 4) |
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| 119 | .set FP_14, (FP_13 + 4) |
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| 120 | .set FP_15, (FP_14 + 4) |
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| 121 | .set FP_16, (FP_15 + 4) |
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| 122 | .set FP_17, (FP_16 + 4) |
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| 123 | .set FP_18, (FP_17 + 4) |
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| 124 | .set FP_19, (FP_18 + 4) |
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| 125 | .set FP_20, (FP_19 + 4) |
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| 126 | .set FP_21, (FP_20 + 4) |
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| 127 | .set FP_22, (FP_21 + 4) |
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| 128 | .set FP_23, (FP_22 + 4) |
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| 129 | .set FP_24, (FP_23 + 4) |
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| 130 | .set FP_25, (FP_24 + 4) |
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| 131 | .set FP_26, (FP_25 + 4) |
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| 132 | .set FP_27, (FP_26 + 4) |
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| 133 | .set FP_28, (FP_27 + 4) |
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| 134 | .set FP_29, (FP_28 + 4) |
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| 135 | .set FP_30, (FP_29 + 4) |
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| 136 | .set FP_31, (FP_30 + 4) |
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| 137 | .set FP_FPSCR, (FP_31 + 4) |
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| 138 | #endif |
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| 139 | |
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| 140 | .set IP_LINK, 0 |
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| 141 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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| 142 | .set IP_0, (IP_LINK + 56) |
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| 143 | #else |
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| 144 | .set IP_0, (IP_LINK + 8) |
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| 145 | #endif |
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| 146 | .set IP_2, (IP_0 + 4) |
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| 147 | |
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| 148 | .set IP_3, (IP_2 + 4) |
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| 149 | .set IP_4, (IP_3 + 4) |
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| 150 | .set IP_5, (IP_4 + 4) |
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| 151 | .set IP_6, (IP_5 + 4) |
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| 152 | |
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| 153 | .set IP_7, (IP_6 + 4) |
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| 154 | .set IP_8, (IP_7 + 4) |
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| 155 | .set IP_9, (IP_8 + 4) |
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| 156 | .set IP_10, (IP_9 + 4) |
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| 157 | |
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| 158 | .set IP_11, (IP_10 + 4) |
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| 159 | .set IP_12, (IP_11 + 4) |
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| 160 | .set IP_13, (IP_12 + 4) |
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| 161 | .set IP_28, (IP_13 + 4) |
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| 162 | |
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| 163 | .set IP_29, (IP_28 + 4) |
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| 164 | .set IP_30, (IP_29 + 4) |
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| 165 | .set IP_31, (IP_30 + 4) |
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| 166 | .set IP_CR, (IP_31 + 4) |
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| 167 | |
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| 168 | .set IP_CTR, (IP_CR + 4) |
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| 169 | .set IP_XER, (IP_CTR + 4) |
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| 170 | .set IP_LR, (IP_XER + 4) |
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| 171 | .set IP_PC, (IP_LR + 4) |
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| 172 | |
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| 173 | .set IP_MSR, (IP_PC + 4) |
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| 174 | .set IP_END, (IP_MSR + 16) |
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| 175 | |
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| 176 | /* _CPU_IRQ_info offsets */ |
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| 177 | |
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| 178 | /* These must be in this order */ |
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| 179 | .set Nest_level, 0 |
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| 180 | .set Disable_level, 4 |
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| 181 | .set Vector_table, 8 |
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| 182 | .set Stack, 12 |
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| 183 | #if (PPC_ABI == PPC_ABI_POWEROPEN) |
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| 184 | .set Dispatch_r2, 16 |
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| 185 | .set Switch_necessary, 20 |
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| 186 | #else |
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| 187 | .set Default_r2, 16 |
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| 188 | #if (PPC_ABI != PPC_ABI_GCC27) |
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| 189 | .set Default_r13, 20 |
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| 190 | .set Switch_necessary, 24 |
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| 191 | #else |
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| 192 | .set Switch_necessary, 20 |
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| 193 | #endif |
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| 194 | #endif |
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| 195 | .set Signal, Switch_necessary + 4 |
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| 196 | .set msr_initial, Signal + 4 |
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| 197 | |
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| 198 | BEGIN_CODE |
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| 199 | /* |
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| 200 | * _CPU_Context_save_fp_context |
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| 201 | * |
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| 202 | * This routine is responsible for saving the FP context |
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| 203 | * at *fp_context_ptr. If the point to load the FP context |
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| 204 | * from is changed then the pointer is modified by this routine. |
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| 205 | * |
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| 206 | * Sometimes a macro implementation of this is in cpu.h which dereferences |
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| 207 | * the ** and a similarly named routine in this file is passed something |
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| 208 | * like a (Context_Control_fp *). The general rule on making this decision |
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| 209 | * is to avoid writing assembly language. |
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| 210 | */ |
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| 211 | |
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| 212 | ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) |
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| 213 | PUBLIC_PROC (_CPU_Context_save_fp) |
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| 214 | PROC (_CPU_Context_save_fp): |
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| 215 | #if (PPC_HAS_FPU == 1) |
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| 216 | lwz r3, 0(r3) |
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| 217 | #if (PPC_HAS_DOUBLE == 1) |
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| 218 | stfd f0, FP_0(r3) |
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| 219 | stfd f1, FP_1(r3) |
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| 220 | stfd f2, FP_2(r3) |
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| 221 | stfd f3, FP_3(r3) |
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| 222 | stfd f4, FP_4(r3) |
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| 223 | stfd f5, FP_5(r3) |
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| 224 | stfd f6, FP_6(r3) |
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| 225 | stfd f7, FP_7(r3) |
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| 226 | stfd f8, FP_8(r3) |
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| 227 | stfd f9, FP_9(r3) |
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| 228 | stfd f10, FP_10(r3) |
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| 229 | stfd f11, FP_11(r3) |
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| 230 | stfd f12, FP_12(r3) |
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| 231 | stfd f13, FP_13(r3) |
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| 232 | stfd f14, FP_14(r3) |
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| 233 | stfd f15, FP_15(r3) |
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| 234 | stfd f16, FP_16(r3) |
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| 235 | stfd f17, FP_17(r3) |
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| 236 | stfd f18, FP_18(r3) |
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| 237 | stfd f19, FP_19(r3) |
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| 238 | stfd f20, FP_20(r3) |
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| 239 | stfd f21, FP_21(r3) |
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| 240 | stfd f22, FP_22(r3) |
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| 241 | stfd f23, FP_23(r3) |
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| 242 | stfd f24, FP_24(r3) |
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| 243 | stfd f25, FP_25(r3) |
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| 244 | stfd f26, FP_26(r3) |
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| 245 | stfd f27, FP_27(r3) |
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| 246 | stfd f28, FP_28(r3) |
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| 247 | stfd f29, FP_29(r3) |
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| 248 | stfd f30, FP_30(r3) |
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| 249 | stfd f31, FP_31(r3) |
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| 250 | mffs f2 |
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| 251 | stfd f2, FP_FPSCR(r3) |
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| 252 | #else |
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| 253 | stfs f0, FP_0(r3) |
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| 254 | stfs f1, FP_1(r3) |
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| 255 | stfs f2, FP_2(r3) |
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| 256 | stfs f3, FP_3(r3) |
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| 257 | stfs f4, FP_4(r3) |
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| 258 | stfs f5, FP_5(r3) |
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| 259 | stfs f6, FP_6(r3) |
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| 260 | stfs f7, FP_7(r3) |
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| 261 | stfs f8, FP_8(r3) |
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| 262 | stfs f9, FP_9(r3) |
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| 263 | stfs f10, FP_10(r3) |
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| 264 | stfs f11, FP_11(r3) |
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| 265 | stfs f12, FP_12(r3) |
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| 266 | stfs f13, FP_13(r3) |
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| 267 | stfs f14, FP_14(r3) |
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| 268 | stfs f15, FP_15(r3) |
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| 269 | stfs f16, FP_16(r3) |
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| 270 | stfs f17, FP_17(r3) |
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| 271 | stfs f18, FP_18(r3) |
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| 272 | stfs f19, FP_19(r3) |
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| 273 | stfs f20, FP_20(r3) |
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| 274 | stfs f21, FP_21(r3) |
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| 275 | stfs f22, FP_22(r3) |
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| 276 | stfs f23, FP_23(r3) |
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| 277 | stfs f24, FP_24(r3) |
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| 278 | stfs f25, FP_25(r3) |
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| 279 | stfs f26, FP_26(r3) |
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| 280 | stfs f27, FP_27(r3) |
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| 281 | stfs f28, FP_28(r3) |
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| 282 | stfs f29, FP_29(r3) |
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| 283 | stfs f30, FP_30(r3) |
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| 284 | stfs f31, FP_31(r3) |
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| 285 | mffs f2 |
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| 286 | stfs f2, FP_FPSCR(r3) |
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| 287 | #endif |
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| 288 | #endif |
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| 289 | blr |
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| 290 | |
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| 291 | /* |
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| 292 | * _CPU_Context_restore_fp_context |
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| 293 | * |
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| 294 | * This routine is responsible for restoring the FP context |
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| 295 | * at *fp_context_ptr. If the point to load the FP context |
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| 296 | * from is changed then the pointer is modified by this routine. |
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| 297 | * |
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| 298 | * Sometimes a macro implementation of this is in cpu.h which dereferences |
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| 299 | * the ** and a similarly named routine in this file is passed something |
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| 300 | * like a (Context_Control_fp *). The general rule on making this decision |
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| 301 | * is to avoid writing assembly language. |
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| 302 | */ |
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| 303 | |
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| 304 | ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) |
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| 305 | PUBLIC_PROC (_CPU_Context_restore_fp) |
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| 306 | PROC (_CPU_Context_restore_fp): |
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| 307 | #if (PPC_HAS_FPU == 1) |
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| 308 | lwz r3, 0(r3) |
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| 309 | #if (PPC_HAS_DOUBLE == 1) |
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| 310 | lfd f2, FP_FPSCR(r3) |
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| 311 | mtfsf 255, f2 |
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| 312 | lfd f0, FP_0(r3) |
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| 313 | lfd f1, FP_1(r3) |
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| 314 | lfd f2, FP_2(r3) |
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| 315 | lfd f3, FP_3(r3) |
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| 316 | lfd f4, FP_4(r3) |
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| 317 | lfd f5, FP_5(r3) |
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| 318 | lfd f6, FP_6(r3) |
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| 319 | lfd f7, FP_7(r3) |
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| 320 | lfd f8, FP_8(r3) |
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| 321 | lfd f9, FP_9(r3) |
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| 322 | lfd f10, FP_10(r3) |
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| 323 | lfd f11, FP_11(r3) |
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| 324 | lfd f12, FP_12(r3) |
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| 325 | lfd f13, FP_13(r3) |
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| 326 | lfd f14, FP_14(r3) |
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| 327 | lfd f15, FP_15(r3) |
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| 328 | lfd f16, FP_16(r3) |
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| 329 | lfd f17, FP_17(r3) |
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| 330 | lfd f18, FP_18(r3) |
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| 331 | lfd f19, FP_19(r3) |
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| 332 | lfd f20, FP_20(r3) |
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| 333 | lfd f21, FP_21(r3) |
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| 334 | lfd f22, FP_22(r3) |
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| 335 | lfd f23, FP_23(r3) |
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| 336 | lfd f24, FP_24(r3) |
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| 337 | lfd f25, FP_25(r3) |
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| 338 | lfd f26, FP_26(r3) |
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| 339 | lfd f27, FP_27(r3) |
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| 340 | lfd f28, FP_28(r3) |
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| 341 | lfd f29, FP_29(r3) |
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| 342 | lfd f30, FP_30(r3) |
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| 343 | lfd f31, FP_31(r3) |
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| 344 | #else |
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| 345 | lfs f2, FP_FPSCR(r3) |
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| 346 | mtfsf 255, f2 |
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| 347 | lfs f0, FP_0(r3) |
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| 348 | lfs f1, FP_1(r3) |
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| 349 | lfs f2, FP_2(r3) |
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| 350 | lfs f3, FP_3(r3) |
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| 351 | lfs f4, FP_4(r3) |
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| 352 | lfs f5, FP_5(r3) |
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| 353 | lfs f6, FP_6(r3) |
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| 354 | lfs f7, FP_7(r3) |
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| 355 | lfs f8, FP_8(r3) |
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| 356 | lfs f9, FP_9(r3) |
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| 357 | lfs f10, FP_10(r3) |
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| 358 | lfs f11, FP_11(r3) |
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| 359 | lfs f12, FP_12(r3) |
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| 360 | lfs f13, FP_13(r3) |
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| 361 | lfs f14, FP_14(r3) |
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| 362 | lfs f15, FP_15(r3) |
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| 363 | lfs f16, FP_16(r3) |
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| 364 | lfs f17, FP_17(r3) |
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| 365 | lfs f18, FP_18(r3) |
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| 366 | lfs f19, FP_19(r3) |
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| 367 | lfs f20, FP_20(r3) |
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| 368 | lfs f21, FP_21(r3) |
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| 369 | lfs f22, FP_22(r3) |
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| 370 | lfs f23, FP_23(r3) |
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| 371 | lfs f24, FP_24(r3) |
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| 372 | lfs f25, FP_25(r3) |
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| 373 | lfs f26, FP_26(r3) |
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| 374 | lfs f27, FP_27(r3) |
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| 375 | lfs f28, FP_28(r3) |
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| 376 | lfs f29, FP_29(r3) |
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| 377 | lfs f30, FP_30(r3) |
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| 378 | lfs f31, FP_31(r3) |
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| 379 | #endif |
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| 380 | #endif |
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| 381 | blr |
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| 382 | |
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| 383 | |
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| 384 | /* _CPU_Context_switch |
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| 385 | * |
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| 386 | * This routine performs a normal non-FP context switch. |
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| 387 | */ |
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| 388 | ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) |
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| 389 | PUBLIC_PROC (_CPU_Context_switch) |
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| 390 | PROC (_CPU_Context_switch): |
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| 391 | sync |
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| 392 | isync |
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| 393 | #if (PPC_CACHE_ALIGNMENT == 4) /* No cache */ |
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| 394 | stw r1, GP_1(r3) |
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| 395 | lwz r1, GP_1(r4) |
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| 396 | stw r2, GP_2(r3) |
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| 397 | lwz r2, GP_2(r4) |
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| 398 | #if (PPC_USE_MULTIPLE == 1) |
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| 399 | stmw r13, GP_13(r3) |
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| 400 | lmw r13, GP_13(r4) |
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| 401 | #else |
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| 402 | stw r13, GP_13(r3) |
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| 403 | lwz r13, GP_13(r4) |
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| 404 | stw r14, GP_14(r3) |
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| 405 | lwz r14, GP_14(r4) |
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| 406 | stw r15, GP_15(r3) |
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| 407 | lwz r15, GP_15(r4) |
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| 408 | stw r16, GP_16(r3) |
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| 409 | lwz r16, GP_16(r4) |
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| 410 | stw r17, GP_17(r3) |
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| 411 | lwz r17, GP_17(r4) |
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| 412 | stw r18, GP_18(r3) |
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| 413 | lwz r18, GP_18(r4) |
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| 414 | stw r19, GP_19(r3) |
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| 415 | lwz r19, GP_19(r4) |
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| 416 | stw r20, GP_20(r3) |
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| 417 | lwz r20, GP_20(r4) |
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| 418 | stw r21, GP_21(r3) |
---|
| 419 | lwz r21, GP_21(r4) |
---|
| 420 | stw r22, GP_22(r3) |
---|
| 421 | lwz r22, GP_22(r4) |
---|
| 422 | stw r23, GP_23(r3) |
---|
| 423 | lwz r23, GP_23(r4) |
---|
| 424 | stw r24, GP_24(r3) |
---|
| 425 | lwz r24, GP_24(r4) |
---|
| 426 | stw r25, GP_25(r3) |
---|
| 427 | lwz r25, GP_25(r4) |
---|
| 428 | stw r26, GP_26(r3) |
---|
| 429 | lwz r26, GP_26(r4) |
---|
| 430 | stw r27, GP_27(r3) |
---|
| 431 | lwz r27, GP_27(r4) |
---|
| 432 | stw r28, GP_28(r3) |
---|
| 433 | lwz r28, GP_28(r4) |
---|
| 434 | stw r29, GP_29(r3) |
---|
| 435 | lwz r29, GP_29(r4) |
---|
| 436 | stw r30, GP_30(r3) |
---|
| 437 | lwz r30, GP_30(r4) |
---|
| 438 | stw r31, GP_31(r3) |
---|
| 439 | lwz r31, GP_31(r4) |
---|
| 440 | #endif |
---|
| 441 | mfcr r5 |
---|
| 442 | stw r5, GP_CR(r3) |
---|
| 443 | lwz r5, GP_CR(r4) |
---|
| 444 | mflr r6 |
---|
| 445 | mtcrf 255, r5 |
---|
| 446 | stw r6, GP_PC(r3) |
---|
| 447 | lwz r6, GP_PC(r4) |
---|
| 448 | mfmsr r7 |
---|
| 449 | mtlr r6 |
---|
| 450 | stw r7, GP_MSR(r3) |
---|
| 451 | lwz r7, GP_MSR(r4) |
---|
| 452 | mtmsr r7 |
---|
| 453 | #endif |
---|
| 454 | #if (PPC_CACHE_ALIGNMENT == 16) |
---|
| 455 | /* This assumes that all the registers are in the given order */ |
---|
| 456 | li r5, 16 |
---|
| 457 | addi r3,r3,-4 |
---|
| 458 | #if ( PPC_USE_DATA_CACHE ) |
---|
| 459 | dcbz r5, r3 |
---|
| 460 | #endif |
---|
| 461 | stw r1, GP_1+4(r3) |
---|
| 462 | stw r2, GP_2+4(r3) |
---|
| 463 | #if (PPC_USE_MULTIPLE == 1) |
---|
| 464 | addi r3, r3, GP_14+4 |
---|
| 465 | #if ( PPC_USE_DATA_CACHE ) |
---|
| 466 | dcbz r5, r3 |
---|
| 467 | #endif |
---|
| 468 | |
---|
| 469 | addi r3, r3, GP_18-GP_14 |
---|
| 470 | #if ( PPC_USE_DATA_CACHE ) |
---|
| 471 | dcbz r5, r3 |
---|
| 472 | #endif |
---|
| 473 | addi r3, r3, GP_22-GP_18 |
---|
| 474 | #if ( PPC_USE_DATA_CACHE ) |
---|
| 475 | dcbz r5, r3 |
---|
| 476 | #endif |
---|
| 477 | addi r3, r3, GP_26-GP_22 |
---|
| 478 | #if ( PPC_USE_DATA_CACHE ) |
---|
| 479 | dcbz r5, r3 |
---|
| 480 | #endif |
---|
| 481 | stmw r13, GP_13-GP_26(r3) |
---|
| 482 | #else |
---|
| 483 | stw r13, GP_13+4(r3) |
---|
| 484 | stwu r14, GP_14+4(r3) |
---|
| 485 | #if ( PPC_USE_DATA_CACHE ) |
---|
| 486 | dcbz r5, r3 |
---|
| 487 | #endif |
---|
| 488 | stw r15, GP_15-GP_14(r3) |
---|
| 489 | stw r16, GP_16-GP_14(r3) |
---|
| 490 | stw r17, GP_17-GP_14(r3) |
---|
| 491 | stwu r18, GP_18-GP_14(r3) |
---|
| 492 | #if ( PPC_USE_DATA_CACHE ) |
---|
| 493 | dcbz r5, r3 |
---|
| 494 | #endif |
---|
| 495 | stw r19, GP_19-GP_18(r3) |
---|
| 496 | stw r20, GP_20-GP_18(r3) |
---|
| 497 | stw r21, GP_21-GP_18(r3) |
---|
| 498 | stwu r22, GP_22-GP_18(r3) |
---|
| 499 | #if ( PPC_USE_DATA_CACHE ) |
---|
| 500 | dcbz r5, r3 |
---|
| 501 | #endif |
---|
| 502 | stw r23, GP_23-GP_22(r3) |
---|
| 503 | stw r24, GP_24-GP_22(r3) |
---|
| 504 | stw r25, GP_25-GP_22(r3) |
---|
| 505 | stwu r26, GP_26-GP_22(r3) |
---|
| 506 | #if ( PPC_USE_DATA_CACHE ) |
---|
| 507 | dcbz r5, r3 |
---|
| 508 | #endif |
---|
| 509 | stw r27, GP_27-GP_26(r3) |
---|
| 510 | stw r28, GP_28-GP_26(r3) |
---|
| 511 | stw r29, GP_29-GP_26(r3) |
---|
| 512 | stw r30, GP_30-GP_26(r3) |
---|
| 513 | stw r31, GP_31-GP_26(r3) |
---|
| 514 | #endif |
---|
| 515 | #if ( PPC_USE_DATA_CACHE ) |
---|
| 516 | dcbt r0, r4 |
---|
| 517 | #endif |
---|
| 518 | mfcr r6 |
---|
| 519 | stw r6, GP_CR-GP_26(r3) |
---|
| 520 | mflr r7 |
---|
| 521 | stw r7, GP_PC-GP_26(r3) |
---|
| 522 | mfmsr r8 |
---|
| 523 | stw r8, GP_MSR-GP_26(r3) |
---|
| 524 | |
---|
| 525 | #if ( PPC_USE_DATA_CACHE ) |
---|
| 526 | dcbt r5, r4 |
---|
| 527 | #endif |
---|
| 528 | lwz r1, GP_1(r4) |
---|
| 529 | lwz r2, GP_2(r4) |
---|
| 530 | #if (PPC_USE_MULTIPLE == 1) |
---|
| 531 | addi r4, r4, GP_15 |
---|
| 532 | #if ( PPC_USE_DATA_CACHE ) |
---|
| 533 | dcbt r5, r4 |
---|
| 534 | #endif |
---|
| 535 | addi r4, r4, GP_19-GP_15 |
---|
| 536 | #if ( PPC_USE_DATA_CACHE ) |
---|
| 537 | dcbt r5, r4 |
---|
| 538 | #endif |
---|
| 539 | addi r4, r4, GP_23-GP_19 |
---|
| 540 | #if ( PPC_USE_DATA_CACHE ) |
---|
| 541 | dcbt r5, r4 |
---|
| 542 | #endif |
---|
| 543 | addi r4, r4, GP_27-GP_23 |
---|
| 544 | #if ( PPC_USE_DATA_CACHE ) |
---|
| 545 | dcbt r5, r4 |
---|
| 546 | #endif |
---|
| 547 | lmw r13, GP_13-GP_27(r4) |
---|
| 548 | #else |
---|
| 549 | lwz r13, GP_13(r4) |
---|
| 550 | lwz r14, GP_14(r4) |
---|
| 551 | lwzu r15, GP_15(r4) |
---|
| 552 | #if ( PPC_USE_DATA_CACHE ) |
---|
| 553 | dcbt r5, r4 |
---|
| 554 | #endif |
---|
| 555 | lwz r16, GP_16-GP_15(r4) |
---|
| 556 | lwz r17, GP_17-GP_15(r4) |
---|
| 557 | lwz r18, GP_18-GP_15(r4) |
---|
| 558 | lwzu r19, GP_19-GP_15(r4) |
---|
| 559 | #if ( PPC_USE_DATA_CACHE ) |
---|
| 560 | dcbt r5, r4 |
---|
| 561 | #endif |
---|
| 562 | lwz r20, GP_20-GP_19(r4) |
---|
| 563 | lwz r21, GP_21-GP_19(r4) |
---|
| 564 | lwz r22, GP_22-GP_19(r4) |
---|
| 565 | lwzu r23, GP_23-GP_19(r4) |
---|
| 566 | #if ( PPC_USE_DATA_CACHE ) |
---|
| 567 | dcbt r5, r4 |
---|
| 568 | #endif |
---|
| 569 | lwz r24, GP_24-GP_23(r4) |
---|
| 570 | lwz r25, GP_25-GP_23(r4) |
---|
| 571 | lwz r26, GP_26-GP_23(r4) |
---|
| 572 | lwzu r27, GP_27-GP_23(r4) |
---|
| 573 | #if ( PPC_USE_DATA_CACHE ) |
---|
| 574 | dcbt r5, r4 |
---|
| 575 | #endif |
---|
| 576 | lwz r28, GP_28-GP_27(r4) |
---|
| 577 | lwz r29, GP_29-GP_27(r4) |
---|
| 578 | lwz r30, GP_30-GP_27(r4) |
---|
| 579 | lwz r31, GP_31-GP_27(r4) |
---|
| 580 | #endif |
---|
| 581 | lwz r6, GP_CR-GP_27(r4) |
---|
| 582 | lwz r7, GP_PC-GP_27(r4) |
---|
| 583 | lwz r8, GP_MSR-GP_27(r4) |
---|
| 584 | mtcrf 255, r6 |
---|
| 585 | mtlr r7 |
---|
| 586 | mtmsr r8 |
---|
| 587 | #endif |
---|
| 588 | #if (PPC_CACHE_ALIGNMENT == 32) |
---|
| 589 | /* This assumes that all the registers are in the given order */ |
---|
| 590 | li r5, 32 |
---|
| 591 | addi r3,r3,-4 |
---|
| 592 | #if ( PPC_USE_DATA_CACHE ) |
---|
| 593 | dcbz r5, r3 |
---|
| 594 | #endif |
---|
| 595 | stw r1, GP_1+4(r3) |
---|
| 596 | stw r2, GP_2+4(r3) |
---|
| 597 | #if (PPC_USE_MULTIPLE == 1) |
---|
| 598 | addi r3, r3, GP_18+4 |
---|
| 599 | #if ( PPC_USE_DATA_CACHE ) |
---|
| 600 | dcbz r5, r3 |
---|
| 601 | #endif |
---|
| 602 | stmw r13, GP_13-GP_18(r3) |
---|
| 603 | #else |
---|
| 604 | stw r13, GP_13+4(r3) |
---|
| 605 | stw r14, GP_14+4(r3) |
---|
| 606 | stw r15, GP_15+4(r3) |
---|
| 607 | stw r16, GP_16+4(r3) |
---|
| 608 | stw r17, GP_17+4(r3) |
---|
| 609 | stwu r18, GP_18+4(r3) |
---|
| 610 | #if ( PPC_USE_DATA_CACHE ) |
---|
| 611 | dcbz r5, r3 |
---|
| 612 | #endif |
---|
| 613 | stw r19, GP_19-GP_18(r3) |
---|
| 614 | stw r20, GP_20-GP_18(r3) |
---|
| 615 | stw r21, GP_21-GP_18(r3) |
---|
| 616 | stw r22, GP_22-GP_18(r3) |
---|
| 617 | stw r23, GP_23-GP_18(r3) |
---|
| 618 | stw r24, GP_24-GP_18(r3) |
---|
| 619 | stw r25, GP_25-GP_18(r3) |
---|
| 620 | stw r26, GP_26-GP_18(r3) |
---|
| 621 | stw r27, GP_27-GP_18(r3) |
---|
| 622 | stw r28, GP_28-GP_18(r3) |
---|
| 623 | stw r29, GP_29-GP_18(r3) |
---|
| 624 | stw r30, GP_30-GP_18(r3) |
---|
| 625 | stw r31, GP_31-GP_18(r3) |
---|
| 626 | #endif |
---|
| 627 | #if ( PPC_USE_DATA_CACHE ) |
---|
| 628 | dcbt r0, r4 |
---|
| 629 | #endif |
---|
| 630 | mfcr r6 |
---|
| 631 | stw r6, GP_CR-GP_18(r3) |
---|
| 632 | mflr r7 |
---|
| 633 | stw r7, GP_PC-GP_18(r3) |
---|
| 634 | mfmsr r8 |
---|
| 635 | stw r8, GP_MSR-GP_18(r3) |
---|
| 636 | |
---|
| 637 | #if ( PPC_USE_DATA_CACHE ) |
---|
| 638 | dcbt r5, r4 |
---|
| 639 | #endif |
---|
| 640 | lwz r1, GP_1(r4) |
---|
| 641 | lwz r2, GP_2(r4) |
---|
| 642 | #if (PPC_USE_MULTIPLE == 1) |
---|
| 643 | addi r4, r4, GP_19 |
---|
| 644 | #if ( PPC_USE_DATA_CACHE ) |
---|
| 645 | dcbt r5, r4 |
---|
| 646 | #endif |
---|
| 647 | lmw r13, GP_13-GP_19(r4) |
---|
| 648 | #else |
---|
| 649 | lwz r13, GP_13(r4) |
---|
| 650 | lwz r14, GP_14(r4) |
---|
| 651 | lwz r15, GP_15(r4) |
---|
| 652 | lwz r16, GP_16(r4) |
---|
| 653 | lwz r17, GP_17(r4) |
---|
| 654 | lwz r18, GP_18(r4) |
---|
| 655 | lwzu r19, GP_19(r4) |
---|
| 656 | #if ( PPC_USE_DATA_CACHE ) |
---|
| 657 | dcbt r5, r4 |
---|
| 658 | #endif |
---|
| 659 | lwz r20, GP_20-GP_19(r4) |
---|
| 660 | lwz r21, GP_21-GP_19(r4) |
---|
| 661 | lwz r22, GP_22-GP_19(r4) |
---|
| 662 | lwz r23, GP_23-GP_19(r4) |
---|
| 663 | lwz r24, GP_24-GP_19(r4) |
---|
| 664 | lwz r25, GP_25-GP_19(r4) |
---|
| 665 | lwz r26, GP_26-GP_19(r4) |
---|
| 666 | lwz r27, GP_27-GP_19(r4) |
---|
| 667 | lwz r28, GP_28-GP_19(r4) |
---|
| 668 | lwz r29, GP_29-GP_19(r4) |
---|
| 669 | lwz r30, GP_30-GP_19(r4) |
---|
| 670 | lwz r31, GP_31-GP_19(r4) |
---|
| 671 | #endif |
---|
| 672 | lwz r6, GP_CR-GP_19(r4) |
---|
| 673 | lwz r7, GP_PC-GP_19(r4) |
---|
| 674 | lwz r8, GP_MSR-GP_19(r4) |
---|
| 675 | mtcrf 255, r6 |
---|
| 676 | mtlr r7 |
---|
| 677 | mtmsr r8 |
---|
| 678 | #endif |
---|
| 679 | blr |
---|
| 680 | |
---|
| 681 | /* |
---|
| 682 | * _CPU_Context_restore |
---|
| 683 | * |
---|
| 684 | * This routine is generallu used only to restart self in an |
---|
| 685 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
---|
| 686 | * |
---|
| 687 | * NOTE: May be unnecessary to reload some registers. |
---|
| 688 | */ |
---|
| 689 | /* |
---|
| 690 | * ACB: Don't worry about cache optimisation here - this is not THAT critical. |
---|
| 691 | */ |
---|
| 692 | ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) |
---|
| 693 | PUBLIC_PROC (_CPU_Context_restore) |
---|
| 694 | PROC (_CPU_Context_restore): |
---|
| 695 | lwz r5, GP_CR(r3) |
---|
| 696 | lwz r6, GP_PC(r3) |
---|
| 697 | lwz r7, GP_MSR(r3) |
---|
| 698 | mtcrf 255, r5 |
---|
| 699 | mtlr r6 |
---|
| 700 | mtmsr r7 |
---|
| 701 | lwz r1, GP_1(r3) |
---|
| 702 | lwz r2, GP_2(r3) |
---|
| 703 | #if (PPC_USE_MULTIPLE == 1) |
---|
| 704 | lmw r13, GP_13(r3) |
---|
| 705 | #else |
---|
| 706 | lwz r13, GP_13(r3) |
---|
| 707 | lwz r14, GP_14(r3) |
---|
| 708 | lwz r15, GP_15(r3) |
---|
| 709 | lwz r16, GP_16(r3) |
---|
| 710 | lwz r17, GP_17(r3) |
---|
| 711 | lwz r18, GP_18(r3) |
---|
| 712 | lwz r19, GP_19(r3) |
---|
| 713 | lwz r20, GP_20(r3) |
---|
| 714 | lwz r21, GP_21(r3) |
---|
| 715 | lwz r22, GP_22(r3) |
---|
| 716 | lwz r23, GP_23(r3) |
---|
| 717 | lwz r24, GP_24(r3) |
---|
| 718 | lwz r25, GP_25(r3) |
---|
| 719 | lwz r26, GP_26(r3) |
---|
| 720 | lwz r27, GP_27(r3) |
---|
| 721 | lwz r28, GP_28(r3) |
---|
| 722 | lwz r29, GP_29(r3) |
---|
| 723 | lwz r30, GP_30(r3) |
---|
| 724 | lwz r31, GP_31(r3) |
---|
| 725 | #endif |
---|
| 726 | |
---|
| 727 | blr |
---|
| 728 | |
---|
| 729 | /* Individual interrupt prologues look like this: |
---|
| 730 | * #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
---|
| 731 | * #if (PPC_HAS_FPU) |
---|
| 732 | * stwu r1, -(20*4 + 18*8 + IP_END)(r1) |
---|
| 733 | * #else |
---|
| 734 | * stwu r1, -(20*4 + IP_END)(r1) |
---|
| 735 | * #endif |
---|
| 736 | * #else |
---|
| 737 | * stwu r1, -(IP_END)(r1) |
---|
| 738 | * #endif |
---|
| 739 | * stw r0, IP_0(r1) |
---|
| 740 | * |
---|
| 741 | * li r0, vectornum |
---|
| 742 | * b PROC (_ISR_Handler{,C}) |
---|
| 743 | */ |
---|
| 744 | |
---|
| 745 | /* void __ISR_Handler() |
---|
| 746 | * |
---|
| 747 | * This routine provides the RTEMS interrupt management. |
---|
| 748 | * The vector number is in r0. R0 has already been stacked. |
---|
| 749 | * |
---|
| 750 | */ |
---|
| 751 | ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) |
---|
| 752 | PUBLIC_PROC (_ISR_Handler) |
---|
| 753 | PROC (_ISR_Handler): |
---|
| 754 | #define LABEL(x) x |
---|
| 755 | /* XXX ?? |
---|
| 756 | #define MTSAVE(x) mtspr sprg0, x |
---|
| 757 | #define MFSAVE(x) mfspr x, sprg0 |
---|
| 758 | */ |
---|
| 759 | #define MTPC(x) mtspr srr0, x |
---|
| 760 | #define MFPC(x) mfspr x, srr0 |
---|
| 761 | #define MTMSR(x) mtspr srr1, x |
---|
| 762 | #define MFMSR(x) mfspr x, srr1 |
---|
| 763 | |
---|
| 764 | #include "irq_stub.S" |
---|
| 765 | rfi |
---|
| 766 | |
---|
| 767 | #if (PPC_HAS_RFCI == 1) |
---|
| 768 | /* void __ISR_HandlerC() |
---|
| 769 | * |
---|
| 770 | * This routine provides the RTEMS interrupt management. |
---|
| 771 | * For critical interrupts |
---|
| 772 | * |
---|
| 773 | */ |
---|
| 774 | ALIGN (PPC_CACHE_ALIGNMENT, PPC_CACHE_ALIGN_POWER) |
---|
| 775 | PUBLIC_PROC (_ISR_HandlerC) |
---|
| 776 | PROC (_ISR_HandlerC): |
---|
| 777 | #undef LABEL |
---|
| 778 | #undef MTSAVE |
---|
| 779 | #undef MFSAVE |
---|
| 780 | #undef MTPC |
---|
| 781 | #undef MFPC |
---|
| 782 | #undef MTMSR |
---|
| 783 | #undef MFMSR |
---|
| 784 | #define LABEL(x) x##_C |
---|
| 785 | /* XXX?? |
---|
| 786 | #define MTSAVE(x) mtspr sprg1, x |
---|
| 787 | #define MFSAVE(x) mfspr x, sprg1 |
---|
| 788 | */ |
---|
| 789 | #define MTPC(x) mtspr srr2, x |
---|
| 790 | #define MFPC(x) mfspr x, srr2 |
---|
| 791 | #define MTMSR(x) mtspr srr3, x |
---|
| 792 | #define MFMSR(x) mfspr x, srr3 |
---|
| 793 | #include "irq_stub.S" |
---|
| 794 | rfci |
---|
| 795 | #endif |
---|
| 796 | |
---|
| 797 | /* PowerOpen descriptors for indirect function calls. |
---|
| 798 | */ |
---|
| 799 | |
---|
| 800 | #if (PPC_ABI == PPC_ABI_POWEROPEN) |
---|
| 801 | DESCRIPTOR (_CPU_Context_save_fp) |
---|
| 802 | DESCRIPTOR (_CPU_Context_restore_fp) |
---|
| 803 | DESCRIPTOR (_CPU_Context_switch) |
---|
| 804 | DESCRIPTOR (_CPU_Context_restore) |
---|
| 805 | DESCRIPTOR (_ISR_Handler) |
---|
| 806 | #if (PPC_HAS_RFCI == 1) |
---|
| 807 | DESCRIPTOR (_ISR_HandlerC) |
---|
| 808 | #endif |
---|
| 809 | #endif |
---|