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source: rtems/c/src/lib/libcpu/powerpc/old-exceptions/cpu.c @ db87589

4.104.114.84.95

Last change on this file since db87589 was ffe6331, checked in by Ralf Corsepius <ralf.corsepius@…>, on 03/31/04 at 03:46:24

2004-03-31 Ralf Corsepius <ralf_corsepius@…>

cpu.c, ppccache.c: Convert to using c99 fixed size types.

Property mode set to 100644

File size: 21.2 KB

Line
1	/*
2	* PowerPC CPU Dependent Source
3	*
4	* Author: Andrew Bray <andy@i-cubed.co.uk>
5	*
6	* COPYRIGHT (c) 1995 by i-cubed ltd.
7	*
8	* To anyone who acknowledges that this file is provided "AS IS"
9	* without any express or implied warranty:
10	* permission to use, copy, modify, and distribute this file
11	* for any purpose is hereby granted without fee, provided that
12	* the above copyright notice and this notice appears in all
13	* copies, and that the name of i-cubed limited not be used in
14	* advertising or publicity pertaining to distribution of the
15	* software without specific, written prior permission.
16	* i-cubed limited makes no representations about the suitability
17	* of this software for any purpose.
18	*
19	* Derived from c/src/exec/cpu/no_cpu/cpu.c:
20	*
21	* COPYRIGHT (c) 1989-1997.
22	* On-Line Applications Research Corporation (OAR).
23	*
24	* The license and distribution terms for this file may be found in
25	* the file LICENSE in this distribution or at
26	* http://www.rtems.com/license/LICENSE.
27	*
28	* $Id$
29	*/
30
31	#include <rtems/system.h>
32	#include <rtems/score/isr.h>
33	#include <rtems/score/context.h>
34	#include <rtems/score/thread.h>
35	#include <rtems/score/interr.h>
36
37	#include <rtems/powerpc/cache.h>
38
39	/*
40	* These are for testing purposes.
41	*/
42
43	/* _CPU_Initialize
44	*
45	* This routine performs processor dependent initialization.
46	*
47	* INPUT PARAMETERS:
48	* cpu_table - CPU table to initialize
49	* thread_dispatch - address of disptaching routine
50	*/
51
52	static void ppc_spurious(int, CPU_Interrupt_frame *);
53
54	int _CPU_spurious_count = 0;
55	int _CPU_last_spurious = 0;
56
57	void _CPU_Initialize(
58	rtems_cpu_table *cpu_table,
59	void (thread_dispatch) / ignored on this CPU */
60	)
61	{
62	#if (PPC_USE_SPRG)
63	int i;
64	#endif
65	#if (PPC_ABI != PPC_ABI_POWEROPEN)
66	register uint32_t r2 = 0;
67	#if (PPC_ABI != PPC_ABI_GCC27)
68	register uint32_t r13 = 0;
69
70	asm ("mr %0,13" : "=r" ((r13)) : "0" ((r13)));
71	_CPU_IRQ_info.Default_r13 = r13;
72	#endif
73
74	asm ("mr %0,2" : "=r" ((r2)) : "0" ((r2)));
75	_CPU_IRQ_info.Default_r2 = r2;
76	#endif
77
78	_CPU_IRQ_info.Nest_level = &_ISR_Nest_level;
79	_CPU_IRQ_info.Disable_level = &_Thread_Dispatch_disable_level;
80	/* fill in _CPU_IRQ_info.Vector_table later */
81	#if (PPC_ABI == PPC_ABI_POWEROPEN)
82	_CPU_IRQ_info.Dispatch_r2 = ((uint32_t*)_Thread_Dispatch)[1];
83	#endif
84	_CPU_IRQ_info.Switch_necessary = &_Context_Switch_necessary;
85	_CPU_IRQ_info.Signal = &_ISR_Signals_to_thread_executing;
86
87	#if (PPC_USE_SPRG)
88	i = (int)&_CPU_IRQ_info;
89	asm volatile("mtspr 0x113, %0" : "=r" (i) : "0" (i)); /* SPRG 3 */
90	#endif
91
92	/*
93	* Store Msr Value in the IRQ info structure.
94	*/
95	_CPU_MSR_Value(_CPU_IRQ_info.msr_initial);
96
97	#if (PPC_USE_SPRG)
98	i = _CPU_IRQ_info.msr_initial;
99	asm volatile("mtspr 0x112, %0" : "=r" (i) : "0" (i)); /* SPRG 2 */
100	#endif
101
102	_CPU_Table = *cpu_table;
103	}
104
105	/*
106	* _CPU_Initialize_vectors()
107	*
108	* Support routine to initialize the RTEMS vector table after it is allocated.
109	*
110	* PowerPC Specific Information:
111	*
112	* Complete initialization since the table is now allocated.
113	*/
114
115	void _CPU_Initialize_vectors(void)
116	{
117	int i;
118	proc_ptr handler = (proc_ptr)ppc_spurious;
119
120	_CPU_IRQ_info.Vector_table = _ISR_Vector_table;
121
122	if ( _CPU_Table.spurious_handler )
123	handler = (proc_ptr)_CPU_Table.spurious_handler;
124
125	for (i = 0; i < PPC_INTERRUPT_MAX; i++)
126	_ISR_Vector_table[i] = handler;
127
128	}
129
130	/*PAGE
131	*
132	* _CPU_ISR_Calculate_level
133	*
134	* The PowerPC puts its interrupt enable status in the MSR register
135	* which also contains things like endianness control. To be more
136	* awkward, the layout varies from processor to processor. This
137	* is why it was necessary to adopt a scheme which allowed the user
138	* to specify specifically which interrupt sources were enabled.
139	*/
140
141	uint32_t _CPU_ISR_Calculate_level(
142	uint32_t new_level
143	)
144	{
145	register uint32_t new_msr = 0;
146
147	/*
148	* Set the critical interrupt enable bit
149	*/
150
151	#if (PPC_HAS_RFCI)
152	if ( !(new_level & PPC_INTERRUPT_LEVEL_CE) )
153	new_msr \|= PPC_MSR_CE;
154	#endif
155
156	if ( !(new_level & PPC_INTERRUPT_LEVEL_ME) )
157	new_msr \|= PPC_MSR_ME;
158
159	if ( !(new_level & PPC_INTERRUPT_LEVEL_EE) )
160	new_msr \|= PPC_MSR_EE;
161
162	return new_msr;
163	}
164
165	/*PAGE
166	*
167	* _CPU_ISR_Set_level
168	*
169	* This routine sets the requested level in the MSR.
170	*/
171
172	void _CPU_ISR_Set_level(
173	uint32_t new_level
174	)
175	{
176	register uint32_t tmp = 0;
177	register uint32_t new_msr;
178
179	new_msr = _CPU_ISR_Calculate_level( new_level );
180
181	asm volatile (
182	"mfmsr %0; andc %0,%0,%1; and %2, %2, %1; or %0, %0, %2; mtmsr %0" :
183	"=&r" ((tmp)) :
184	"r" ((PPC_MSR_DISABLE_MASK)), "r" ((new_msr)), "0" ((tmp))
185	);
186	}
187
188	/*PAGE
189	*
190	* _CPU_ISR_Get_level
191	*
192	* This routine gets the current interrupt level from the MSR and
193	* converts it to an RTEMS interrupt level.
194	*/
195
196	uint32_t _CPU_ISR_Get_level( void )
197	{
198	uint32_t level = 0;
199	uint32_t msr;
200
201	asm volatile("mfmsr %0" : "=r" ((msr)));
202
203	msr &= PPC_MSR_DISABLE_MASK;
204
205	/*
206	* Set the critical interrupt enable bit
207	*/
208
209	#if (PPC_HAS_RFCI)
210	if ( !(msr & PPC_MSR_CE) )
211	level \|= PPC_INTERRUPT_LEVEL_CE;
212	#endif
213
214	if ( !(msr & PPC_MSR_ME) )
215	level \|= PPC_INTERRUPT_LEVEL_ME;
216
217	if ( !(msr & PPC_MSR_EE) )
218	level \|= PPC_INTERRUPT_LEVEL_EE;
219
220	return level;
221	}
222
223	/*PAGE
224	*
225	* _CPU_Context_Initialize
226	*/
227
228	#if (PPC_ABI == PPC_ABI_POWEROPEN)
229	#define CPU_MINIMUM_STACK_FRAME_SIZE 56
230	#else /* PPC_ABI_SVR4 or PPC_ABI_EABI */
231	#define CPU_MINIMUM_STACK_FRAME_SIZE 8
232	#endif
233
234	void _CPU_Context_Initialize(
235	Context_Control *the_context,
236	uint32_t *stack_base,
237	uint32_t size,
238	uint32_t new_level,
239	void *entry_point,
240	boolean is_fp
241	)
242	{
243	uint32_t msr_value;
244	uint32_t sp;
245
246	sp = (uint32_t)stack_base + size - CPU_MINIMUM_STACK_FRAME_SIZE;
247	((uint32_t)sp) = 0;
248	the_context->gpr1 = sp;
249
250	the_context->msr = _CPU_ISR_Calculate_level( new_level );
251
252	/*
253	* The FP bit of the MSR should only be enabled if this is a floating
254	* point task. Unfortunately, the vfprintf_r routine in newlib
255	* ends up pushing a floating point register regardless of whether or
256	* not a floating point number is being printed. Serious restructuring
257	* of vfprintf.c will be required to avoid this behavior. At this
258	* time (7 July 1997), this restructuring is not being done.
259	*/
260
261	/if ( is_fp ) /
262	the_context->msr \|= PPC_MSR_FP;
263
264	/*
265	* Calculate the task's MSR value:
266	*
267	* + Set the exception prefix bit to point to the exception table
268	* + Force the RI bit
269	* + Use the DR and IR bits
270	*/
271	_CPU_MSR_Value( msr_value );
272	the_context->msr \|= (msr_value & PPC_MSR_EP);
273	the_context->msr \|= PPC_MSR_RI;
274	the_context->msr \|= msr_value & (PPC_MSR_DR\|PPC_MSR_IR);
275
276	#if (PPC_ABI == PPC_ABI_POWEROPEN)
277	{ uint32_t desc = (uint32_t)entry_point;
278
279	the_context->pc = desc[0];
280	the_context->gpr2 = desc[1];
281	}
282	#endif
283
284	#if (PPC_ABI == PPC_ABI_SVR4)
285	{ unsigned r13 = 0;
286	asm volatile ("mr %0, 13" : "=r" ((r13)));
287
288	the_context->pc = (uint32_t)entry_point;
289	the_context->gpr13 = r13;
290	}
291	#endif
292
293	#if (PPC_ABI == PPC_ABI_EABI)
294	{ uint32_t r2 = 0;
295	unsigned r13 = 0;
296	asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
297
298	the_context->pc = (uint32_t)entry_point;
299	the_context->gpr2 = r2;
300	the_context->gpr13 = r13;
301	}
302	#endif
303	}
304
305
306	/* _CPU_ISR_install_vector
307	*
308	* This kernel routine installs the RTEMS handler for the
309	* specified vector.
310	*
311	* Input parameters:
312	* vector - interrupt vector number
313	* old_handler - former ISR for this vector number
314	* new_handler - replacement ISR for this vector number
315	*
316	* Output parameters: NONE
317	*
318	*/
319
320	void _CPU_ISR_install_vector(
321	uint32_t vector,
322	proc_ptr new_handler,
323	proc_ptr *old_handler
324	)
325	{
326	proc_ptr ignored;
327	*old_handler = _ISR_Vector_table[ vector ];
328
329	/*
330	* If the interrupt vector table is a table of pointer to isr entry
331	* points, then we need to install the appropriate RTEMS interrupt
332	* handler for this vector number.
333	*/
334
335	/*
336	* Install the wrapper so this ISR can be invoked properly.
337	*/
338	if (_CPU_Table.exceptions_in_RAM)
339	_CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
340
341	/*
342	* We put the actual user ISR address in '_ISR_vector_table'. This will
343	* be used by the _ISR_Handler so the user gets control.
344	*/
345
346	_ISR_Vector_table[ vector ] = new_handler ? (ISR_Handler_entry)new_handler :
347	_CPU_Table.spurious_handler ?
348	(ISR_Handler_entry)_CPU_Table.spurious_handler :
349	(ISR_Handler_entry)ppc_spurious;
350	}
351
352	/*PAGE
353	*
354	* _CPU_Install_interrupt_stack
355	*/
356
357	void _CPU_Install_interrupt_stack( void )
358	{
359	#if (PPC_ABI == PPC_ABI_POWEROPEN \|\| PPC_ABI == PPC_ABI_GCC27)
360	_CPU_IRQ_info.Stack = _CPU_Interrupt_stack_high - 56;
361	#else
362	_CPU_IRQ_info.Stack = _CPU_Interrupt_stack_high - 8;
363	#endif
364	}
365
366	/* Handle a spurious interrupt */
367	static void ppc_spurious(int v, CPU_Interrupt_frame *i)
368	{
369	#if 0
370	printf("Spurious interrupt on vector %d from %08.8x\n",
371	v, i->pc);
372	#endif
373	#if defined(ppc403) \|\| defined(ppc405)
374	if (v == PPC_IRQ_EXTERNAL)
375	{
376	register int r = 0;
377
378	asm volatile("mtdcr 0x42, %0" :
379	"=&r" ((r)) : "0" ((r))); /* EXIER */
380	}
381	else if (v == PPC_IRQ_PIT)
382	{
383	register int r = 0x08000000;
384
385	asm volatile("mtspr 0x3d8, %0" :
386	"=&r" ((r)) : "0" ((r))); /* TSR */
387	}
388	else if (v == PPC_IRQ_FIT)
389	{
390	register int r = 0x04000000;
391
392	asm volatile("mtspr 0x3d8, %0" :
393	"=&r" ((r)) : "0" ((r))); /* TSR */
394	}
395	#endif
396	++_CPU_spurious_count;
397	_CPU_last_spurious = v;
398	}
399
400	void _CPU_Fatal_error(uint32_t _error)
401	{
402	asm volatile ("mr 3, %0" : : "r" ((_error)));
403	asm volatile ("tweq 5,5");
404	asm volatile ("li 0,0; mtmsr 0");
405	while (1) ;
406	}
407
408	#define PPC_SYNCHRONOUS_TRAP_BIT_MASK 0x100
409	#define PPC_ASYNCHRONOUS_TRAP( _trap ) (_trap)
410	#define PPC_SYNCHRONOUS_TRAP ( _trap ) ((_trap)+PPC_SYNCHRONOUS_TRAP_BIT_MASK)
411	#define PPC_REAL_TRAP_NUMBER ( _trap ) ((_trap)%PPC_SYNCHRONOUS_TRAP_BIT_MASK)
412
413
414	const CPU_Trap_table_entry _CPU_Trap_slot_template = {
415
416	#if (PPC_ABI == PPC_ABI_POWEROPEN \|\| PPC_ABI == PPC_ABI_GCC27)
417	#error " Vector install not tested."
418	#if (PPC_HAS_FPU)
419	#error " Vector install not tested."
420	0x9421feb0, /* stwu r1, -(204 + 188 + IP_END)(r1) */
421	#else
422	#error " Vector install not tested."
423	0x9421ff40, /* stwu r1, -(204 + IP_END)(r1) /
424	#endif
425	#else
426	0x9421ff90, /* stwu r1, -(IP_END)(r1) */
427	#endif
428
429	0x90010008, /* stw %r0, IP_0(%r1) */
430	0x38000000, /* li %r0, PPC_IRQ */
431	0x48000002 /* ba PROC (_ISR_Handler) */
432	};
433
434	#if defined(mpc860) \|\| defined(mpc821)
435	const CPU_Trap_table_entry _CPU_Trap_slot_template_m860 = {
436	0x7c0803ac, /* mtlr %r0 */
437	0x81210028, /* lwz %r9, IP_9(%r1) */
438	0x38000000, /* li %r0, PPC_IRQ */
439	0x48000002 /* b PROC (_ISR_Handler) */
440	};
441	#endif /* mpc860 */
442
443	uint32_t ppc_exception_vector_addr(
444	uint32_t vector
445	);
446
447
448	/*PAGE
449	*
450	* _CPU_ISR_install_raw_handler
451	*
452	* This routine installs the specified handler as a "raw" non-executive
453	* supported trap handler (a.k.a. interrupt service routine).
454	*
455	* Input Parameters:
456	* vector - trap table entry number plus synchronous
457	* vs. asynchronous information
458	* new_handler - address of the handler to be installed
459	* old_handler - pointer to an address of the handler previously installed
460	*
461	* Output Parameters: NONE
462	* *new_handler - address of the handler previously installed
463	*
464	* NOTE:
465	*
466	* This routine is based on the SPARC routine _CPU_ISR_install_raw_handler.
467	* Install a software trap handler as an executive interrupt handler
468	* (which is desirable since RTEMS takes care of window and register issues),
469	* then the executive needs to know that the return address is to the trap
470	* rather than the instruction following the trap.
471	*
472	*/
473
474	void _CPU_ISR_install_raw_handler(
475	uint32_t vector,
476	proc_ptr new_handler,
477	proc_ptr *old_handler
478	)
479	{
480	uint32_t real_vector;
481	CPU_Trap_table_entry *slot;
482	uint32_t u32_handler=0;
483
484	/*
485	* Get the "real" trap number for this vector ignoring the synchronous
486	* versus asynchronous indicator included with our vector numbers.
487	*/
488
489	real_vector = vector;
490
491	/*
492	* Get the current base address of the trap table and calculate a pointer
493	* to the slot we are interested in.
494	*/
495	slot = (CPU_Trap_table_entry *)ppc_exception_vector_addr( real_vector );
496
497	/*
498	* Get the address of the old_handler from the trap table.
499	*
500	* NOTE: The old_handler returned will be bogus if it does not follow
501	* the RTEMS model.
502	*/
503
504	#define HIGH_BITS_MASK 0xFFFFFC00
505	#define HIGH_BITS_SHIFT 10
506	#define LOW_BITS_MASK 0x000003FF
507
508	if (slot->stwu_r1 == _CPU_Trap_slot_template.stwu_r1) {
509	/*
510	* Set u32_handler = to target address
511	*/
512	u32_handler = slot->b_Handler & 0x03fffffc;
513
514	/* IMD FIX: sign extend address fragment... */
515	if (u32_handler & 0x02000000) {
516	u32_handler \|= 0xfc000000;
517	}
518
519	*old_handler = (proc_ptr) u32_handler;
520	} else
521	/* There are two kinds of handlers for the MPC860. One is the 'standard'
522	* one like above. The other is for the cascaded interrupts from the SIU
523	* and CPM. Therefore we must check for the alternate one if the standard
524	* one is not present
525	*/
526	#if defined(mpc860) \|\| defined(mpc821)
527	if (slot->stwu_r1 == _CPU_Trap_slot_template_m860.stwu_r1) {
528	/*
529	* Set u32_handler = to target address
530	*/
531	u32_handler = slot->b_Handler & 0x03fffffc;
532	*old_handler = (proc_ptr) u32_handler;
533	} else
534	#endif /* mpc860 */
535
536	*old_handler = 0;
537
538	/*
539	* Copy the template to the slot and then fix it.
540	*/
541	#if defined(mpc860) \|\| defined(mpc821)
542	if (vector >= PPC_IRQ_IRQ0)
543	*slot = _CPU_Trap_slot_template_m860;
544	else
545	#endif /* mpc860 */
546	*slot = _CPU_Trap_slot_template;
547
548	u32_handler = (uint32_t) new_handler;
549
550	/*
551	* IMD FIX: insert address fragment only (bits 6..29)
552	* therefore check for proper address range
553	* and remove unwanted bits
554	*/
555	if ((u32_handler & 0xfc000000) == 0xfc000000) {
556	u32_handler &= ~0xfc000000;
557	}
558	else if ((u32_handler & 0xfc000000) != 0x00000000) {
559	_Internal_error_Occurred(INTERNAL_ERROR_CORE,
560	TRUE,
561	u32_handler);
562	}
563
564	slot->b_Handler \|= u32_handler;
565
566	slot->li_r0_IRQ \|= vector;
567
568	_CPU_Data_Cache_Block_Flush( slot );
569	}
570
571	uint32_t ppc_exception_vector_addr(
572	uint32_t vector
573	)
574	{
575	#if (!PPC_HAS_EVPR)
576	uint32_t Msr;
577	#endif
578	uint32_t Top = 0;
579	uint32_t Offset = 0x000;
580
581	#if (PPC_HAS_EXCEPTION_PREFIX)
582	_CPU_MSR_Value ( Msr );
583	if ( ( Msr & PPC_MSR_EP) != 0 ) /* Vectors at FFFx_xxxx */
584	Top = 0xfff00000;
585	#elif (PPC_HAS_EVPR)
586	asm volatile( "mfspr %0,0x3d6" : "=r" (Top)); /* EVPR */
587	Top = Top & 0xffff0000;
588	#endif
589
590	switch ( vector ) {
591	case PPC_IRQ_SYSTEM_RESET: /* on 40x aka PPC_IRQ_CRIT */
592	Offset = 0x00100;
593	break;
594	case PPC_IRQ_MCHECK:
595	Offset = 0x00200;
596	break;
597	case PPC_IRQ_PROTECT:
598	Offset = 0x00300;
599	break;
600	case PPC_IRQ_ISI:
601	Offset = 0x00400;
602	break;
603	case PPC_IRQ_EXTERNAL:
604	Offset = 0x00500;
605	break;
606	case PPC_IRQ_ALIGNMENT:
607	Offset = 0x00600;
608	break;
609	case PPC_IRQ_PROGRAM:
610	Offset = 0x00700;
611	break;
612	case PPC_IRQ_NOFP:
613	Offset = 0x00800;
614	break;
615	case PPC_IRQ_DECREMENTER:
616	Offset = 0x00900;
617	break;
618	case PPC_IRQ_RESERVED_A:
619	Offset = 0x00a00;
620	break;
621	case PPC_IRQ_RESERVED_B:
622	Offset = 0x00b00;
623	break;
624	case PPC_IRQ_SCALL:
625	Offset = 0x00c00;
626	break;
627	case PPC_IRQ_TRACE:
628	Offset = 0x00d00;
629	break;
630	case PPC_IRQ_FP_ASST:
631	Offset = 0x00e00;
632	break;
633
634	#if defined(ppc403) \|\| defined(ppc405)
635
636	/* PPC_IRQ_CRIT is the same vector as PPC_IRQ_RESET
637	case PPC_IRQ_CRIT:
638	Offset = 0x00100;
639	break;
640	*/
641	case PPC_IRQ_PIT:
642	Offset = 0x01000;
643	break;
644	case PPC_IRQ_FIT:
645	Offset = 0x01010;
646	break;
647	case PPC_IRQ_WATCHDOG:
648	Offset = 0x01020;
649	break;
650	case PPC_IRQ_DEBUG:
651	Offset = 0x02000;
652	break;
653
654	#elif defined(ppc601)
655	case PPC_IRQ_TRACE:
656	Offset = 0x02000;
657	break;
658
659	#elif defined(ppc603)
660	case PPC_IRQ_TRANS_MISS:
661	Offset = 0x1000;
662	break;
663	case PPC_IRQ_DATA_LOAD:
664	Offset = 0x1100;
665	break;
666	case PPC_IRQ_DATA_STORE:
667	Offset = 0x1200;
668	break;
669	case PPC_IRQ_ADDR_BRK:
670	Offset = 0x1300;
671	break;
672	case PPC_IRQ_SYS_MGT:
673	Offset = 0x1400;
674	break;
675
676	#elif defined(ppc603e)
677	case PPC_TLB_INST_MISS:
678	Offset = 0x1000;
679	break;
680	case PPC_TLB_LOAD_MISS:
681	Offset = 0x1100;
682	break;
683	case PPC_TLB_STORE_MISS:
684	Offset = 0x1200;
685	break;
686	case PPC_IRQ_ADDRBRK:
687	Offset = 0x1300;
688	break;
689	case PPC_IRQ_SYS_MGT:
690	Offset = 0x1400;
691	break;
692
693	#elif defined(mpc604)
694	case PPC_IRQ_ADDR_BRK:
695	Offset = 0x1300;
696	break;
697	case PPC_IRQ_SYS_MGT:
698	Offset = 0x1400;
699	break;
700
701	#elif defined(mpc860) \|\| defined(mpc821)
702	case PPC_IRQ_EMULATE:
703	Offset = 0x1000;
704	break;
705	case PPC_IRQ_INST_MISS:
706	Offset = 0x1100;
707	break;
708	case PPC_IRQ_DATA_MISS:
709	Offset = 0x1200;
710	break;
711	case PPC_IRQ_INST_ERR:
712	Offset = 0x1300;
713	break;
714	case PPC_IRQ_DATA_ERR:
715	Offset = 0x1400;
716	break;
717	case PPC_IRQ_DATA_BPNT:
718	Offset = 0x1c00;
719	break;
720	case PPC_IRQ_INST_BPNT:
721	Offset = 0x1d00;
722	break;
723	case PPC_IRQ_IO_BPNT:
724	Offset = 0x1e00;
725	break;
726	case PPC_IRQ_DEV_PORT:
727	Offset = 0x1f00;
728	break;
729	case PPC_IRQ_IRQ0:
730	Offset = 0x2000;
731	break;
732	case PPC_IRQ_LVL0:
733	Offset = 0x2040;
734	break;
735	case PPC_IRQ_IRQ1:
736	Offset = 0x2080;
737	break;
738	case PPC_IRQ_LVL1:
739	Offset = 0x20c0;
740	break;
741	case PPC_IRQ_IRQ2:
742	Offset = 0x2100;
743	break;
744	case PPC_IRQ_LVL2:
745	Offset = 0x2140;
746	break;
747	case PPC_IRQ_IRQ3:
748	Offset = 0x2180;
749	break;
750	case PPC_IRQ_LVL3:
751	Offset = 0x21c0;
752	break;
753	case PPC_IRQ_IRQ4:
754	Offset = 0x2200;
755	break;
756	case PPC_IRQ_LVL4:
757	Offset = 0x2240;
758	break;
759	case PPC_IRQ_IRQ5:
760	Offset = 0x2280;
761	break;
762	case PPC_IRQ_LVL5:
763	Offset = 0x22c0;
764	break;
765	case PPC_IRQ_IRQ6:
766	Offset = 0x2300;
767	break;
768	case PPC_IRQ_LVL6:
769	Offset = 0x2340;
770	break;
771	case PPC_IRQ_IRQ7:
772	Offset = 0x2380;
773	break;
774	case PPC_IRQ_LVL7:
775	Offset = 0x23c0;
776	break;
777	case PPC_IRQ_CPM_ERROR:
778	Offset = 0x2400;
779	break;
780	case PPC_IRQ_CPM_PC4:
781	Offset = 0x2410;
782	break;
783	case PPC_IRQ_CPM_PC5:
784	Offset = 0x2420;
785	break;
786	case PPC_IRQ_CPM_SMC2:
787	Offset = 0x2430;
788	break;
789	case PPC_IRQ_CPM_SMC1:
790	Offset = 0x2440;
791	break;
792	case PPC_IRQ_CPM_SPI:
793	Offset = 0x2450;
794	break;
795	case PPC_IRQ_CPM_PC6:
796	Offset = 0x2460;
797	break;
798	case PPC_IRQ_CPM_TIMER4:
799	Offset = 0x2470;
800	break;
801	case PPC_IRQ_CPM_RESERVED_8:
802	Offset = 0x2480;
803	break;
804	case PPC_IRQ_CPM_PC7:
805	Offset = 0x2490;
806	break;
807	case PPC_IRQ_CPM_PC8:
808	Offset = 0x24a0;
809	break;
810	case PPC_IRQ_CPM_PC9:
811	Offset = 0x24b0;
812	break;
813	case PPC_IRQ_CPM_TIMER3:
814	Offset = 0x24c0;
815	break;
816	case PPC_IRQ_CPM_RESERVED_D:
817	Offset = 0x24d0;
818	break;
819	case PPC_IRQ_CPM_PC10:
820	Offset = 0x24e0;
821	break;
822	case PPC_IRQ_CPM_PC11:
823	Offset = 0x24f0;
824	break;
825	case PPC_IRQ_CPM_I2C:
826	Offset = 0x2500;
827	break;
828	case PPC_IRQ_CPM_RISC_TIMER:
829	Offset = 0x2510;
830	break;
831	case PPC_IRQ_CPM_TIMER2:
832	Offset = 0x2520;
833	break;
834	case PPC_IRQ_CPM_RESERVED_13:
835	Offset = 0x2530;
836	break;
837	case PPC_IRQ_CPM_IDMA2:
838	Offset = 0x2540;
839	break;
840	case PPC_IRQ_CPM_IDMA1:
841	Offset = 0x2550;
842	break;
843	case PPC_IRQ_CPM_SDMA_ERROR:
844	Offset = 0x2560;
845	break;
846	case PPC_IRQ_CPM_PC12:
847	Offset = 0x2570;
848	break;
849	case PPC_IRQ_CPM_PC13:
850	Offset = 0x2580;
851	break;
852	case PPC_IRQ_CPM_TIMER1:
853	Offset = 0x2590;
854	break;
855	case PPC_IRQ_CPM_PC14:
856	Offset = 0x25a0;
857	break;
858	case PPC_IRQ_CPM_SCC4:
859	Offset = 0x25b0;
860	break;
861	case PPC_IRQ_CPM_SCC3:
862	Offset = 0x25c0;
863	break;
864	case PPC_IRQ_CPM_SCC2:
865	Offset = 0x25d0;
866	break;
867	case PPC_IRQ_CPM_SCC1:
868	Offset = 0x25e0;
869	break;
870	case PPC_IRQ_CPM_PC15:
871	Offset = 0x25f0;
872	break;
873	#endif
874
875	}
876	Top += Offset;
877	return Top;
878	}
879
880	/*PAGE
881	*
882	* This is the PowerPC specific implementation of the routine which
883	* returns TRUE if an interrupt is in progress.
884	*
885	* NOTE: This is the same as the generic version. But since the
886	* PowerPC is still supporting old and new exception processing
887	* models and the new exception processing model has a hardware
888	* way of doing this, we have to provide this capability here
889	* for symmetry.
890	*/
891
892	boolean _ISR_Is_in_progress( void )
893	{
894	return (_ISR_Nest_level != 0);
895	}

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