1 | /* |
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2 | * PowerPC CPU Dependent Source |
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3 | * |
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4 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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5 | * |
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6 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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7 | * |
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8 | * To anyone who acknowledges that this file is provided "AS IS" |
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9 | * without any express or implied warranty: |
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10 | * permission to use, copy, modify, and distribute this file |
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11 | * for any purpose is hereby granted without fee, provided that |
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12 | * the above copyright notice and this notice appears in all |
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13 | * copies, and that the name of i-cubed limited not be used in |
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14 | * advertising or publicity pertaining to distribution of the |
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15 | * software without specific, written prior permission. |
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16 | * i-cubed limited makes no representations about the suitability |
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17 | * of this software for any purpose. |
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18 | * |
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19 | * Derived from c/src/exec/cpu/no_cpu/cpu.c: |
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20 | * |
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21 | * COPYRIGHT (c) 1989-1997. |
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22 | * On-Line Applications Research Corporation (OAR). |
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23 | * |
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24 | * The license and distribution terms for this file may be found in |
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25 | * the file LICENSE in this distribution or at |
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26 | * http://www.rtems.com/license/LICENSE. |
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27 | * |
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28 | * $Id$ |
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29 | */ |
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30 | |
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31 | #include <bsp.h> |
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32 | #include <rtems/system.h> |
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33 | #include <rtems/score/isr.h> |
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34 | #include <rtems/score/context.h> |
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35 | #include <rtems/score/thread.h> |
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36 | #include <rtems/score/interr.h> |
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37 | |
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38 | #include <rtems/powerpc/cache.h> |
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39 | #include <rtems/powerpc/powerpc.h> |
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40 | |
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41 | /* |
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42 | * These are for testing purposes. |
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43 | */ |
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44 | |
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45 | /* _CPU_Initialize |
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46 | * |
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47 | * This routine performs processor dependent initialization. |
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48 | * |
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49 | * INPUT PARAMETERS: |
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50 | * cpu_table - CPU table to initialize |
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51 | * thread_dispatch - address of disptaching routine |
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52 | */ |
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53 | |
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54 | static void ppc_spurious(int, CPU_Interrupt_frame *); |
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55 | |
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56 | int _CPU_spurious_count = 0; |
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57 | int _CPU_last_spurious = 0; |
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58 | |
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59 | void _CPU_Initialize( |
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60 | rtems_cpu_table *cpu_table, |
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61 | void (*thread_dispatch) /* ignored on this CPU */ |
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62 | ) |
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63 | { |
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64 | #if (PPC_USE_SPRG) |
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65 | int i; |
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66 | #endif |
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67 | register uint32_t r2 = 0; |
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68 | register uint32_t r13 = 0; |
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69 | |
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70 | asm ("mr %0,13" : "=r" ((r13)) : "0" ((r13))); |
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71 | _CPU_IRQ_info.Default_r13 = r13; |
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72 | |
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73 | asm ("mr %0,2" : "=r" ((r2)) : "0" ((r2))); |
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74 | _CPU_IRQ_info.Default_r2 = r2; |
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75 | |
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76 | _CPU_IRQ_info.Nest_level = &_ISR_Nest_level; |
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77 | _CPU_IRQ_info.Disable_level = &_Thread_Dispatch_disable_level; |
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78 | /* fill in _CPU_IRQ_info.Vector_table later */ |
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79 | _CPU_IRQ_info.Switch_necessary = &_Context_Switch_necessary; |
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80 | _CPU_IRQ_info.Signal = &_ISR_Signals_to_thread_executing; |
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81 | |
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82 | #if (PPC_USE_SPRG) |
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83 | i = (int)&_CPU_IRQ_info; |
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84 | asm volatile("mtspr 0x113, %0" : "=r" (i) : "0" (i)); /* SPRG 3 */ |
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85 | #endif |
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86 | |
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87 | /* |
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88 | * Store Msr Value in the IRQ info structure. |
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89 | */ |
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90 | _CPU_MSR_GET(_CPU_IRQ_info.msr_initial); |
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91 | |
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92 | #if (PPC_USE_SPRG) |
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93 | i = _CPU_IRQ_info.msr_initial; |
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94 | asm volatile("mtspr 0x112, %0" : "=r" (i) : "0" (i)); /* SPRG 2 */ |
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95 | #endif |
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96 | |
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97 | _CPU_Table = *cpu_table; |
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98 | } |
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99 | |
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100 | /* |
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101 | * _CPU_Initialize_vectors() |
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102 | * |
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103 | * Support routine to initialize the RTEMS vector table after it is allocated. |
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104 | * |
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105 | * PowerPC Specific Information: |
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106 | * |
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107 | * Complete initialization since the table is now allocated. |
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108 | */ |
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109 | |
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110 | void _CPU_Initialize_vectors(void) |
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111 | { |
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112 | int i; |
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113 | proc_ptr handler = (proc_ptr)ppc_spurious; |
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114 | |
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115 | _CPU_IRQ_info.Vector_table = _ISR_Vector_table; |
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116 | |
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117 | if ( _CPU_Table.spurious_handler ) |
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118 | handler = (proc_ptr)_CPU_Table.spurious_handler; |
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119 | |
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120 | for (i = 0; i < PPC_INTERRUPT_MAX; i++) |
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121 | _ISR_Vector_table[i] = handler; |
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122 | |
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123 | } |
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124 | |
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125 | /*PAGE |
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126 | * |
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127 | * _CPU_ISR_Calculate_level |
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128 | * |
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129 | * The PowerPC puts its interrupt enable status in the MSR register |
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130 | * which also contains things like endianness control. To be more |
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131 | * awkward, the layout varies from processor to processor. This |
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132 | * is why it was necessary to adopt a scheme which allowed the user |
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133 | * to specify specifically which interrupt sources were enabled. |
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134 | */ |
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135 | |
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136 | uint32_t _CPU_ISR_Calculate_level( |
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137 | uint32_t new_level |
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138 | ) |
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139 | { |
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140 | register uint32_t new_msr = 0; |
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141 | |
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142 | /* |
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143 | * Set the critical interrupt enable bit |
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144 | */ |
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145 | |
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146 | #if (PPC_HAS_RFCI) |
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147 | if ( !(new_level & PPC_INTERRUPT_LEVEL_CE) ) |
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148 | new_msr |= PPC_MSR_CE; |
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149 | #endif |
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150 | |
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151 | if ( !(new_level & PPC_INTERRUPT_LEVEL_ME) ) |
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152 | new_msr |= PPC_MSR_ME; |
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153 | |
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154 | if ( !(new_level & PPC_INTERRUPT_LEVEL_EE) ) |
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155 | new_msr |= PPC_MSR_EE; |
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156 | |
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157 | return new_msr; |
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158 | } |
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159 | |
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160 | /*PAGE |
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161 | * |
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162 | * _CPU_ISR_Set_level |
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163 | * |
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164 | * This routine sets the requested level in the MSR. |
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165 | */ |
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166 | |
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167 | void _CPU_ISR_Set_level( |
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168 | uint32_t new_level |
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169 | ) |
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170 | { |
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171 | register uint32_t tmp = 0; |
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172 | register uint32_t new_msr; |
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173 | |
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174 | new_msr = _CPU_ISR_Calculate_level( new_level ); |
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175 | |
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176 | asm volatile ( |
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177 | "mfmsr %0; andc %0,%0,%1; and %2, %2, %1; or %0, %0, %2; mtmsr %0" : |
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178 | "=&r" ((tmp)) : |
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179 | "r" ((PPC_MSR_DISABLE_MASK)), "r" ((new_msr)), "0" ((tmp)) |
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180 | ); |
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181 | } |
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182 | |
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183 | /*PAGE |
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184 | * |
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185 | * _CPU_ISR_Get_level |
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186 | * |
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187 | * This routine gets the current interrupt level from the MSR and |
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188 | * converts it to an RTEMS interrupt level. |
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189 | */ |
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190 | |
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191 | uint32_t _CPU_ISR_Get_level( void ) |
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192 | { |
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193 | uint32_t level = 0; |
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194 | uint32_t msr; |
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195 | |
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196 | asm volatile("mfmsr %0" : "=r" ((msr))); |
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197 | |
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198 | msr &= PPC_MSR_DISABLE_MASK; |
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199 | |
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200 | /* |
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201 | * Set the critical interrupt enable bit |
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202 | */ |
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203 | |
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204 | #if (PPC_HAS_RFCI) |
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205 | if ( !(msr & PPC_MSR_CE) ) |
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206 | level |= PPC_INTERRUPT_LEVEL_CE; |
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207 | #endif |
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208 | |
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209 | if ( !(msr & PPC_MSR_ME) ) |
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210 | level |= PPC_INTERRUPT_LEVEL_ME; |
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211 | |
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212 | if ( !(msr & PPC_MSR_EE) ) |
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213 | level |= PPC_INTERRUPT_LEVEL_EE; |
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214 | |
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215 | return level; |
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216 | } |
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217 | |
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218 | /*PAGE |
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219 | * |
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220 | * _CPU_Context_Initialize |
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221 | */ |
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222 | |
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223 | void _CPU_Context_Initialize( |
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224 | Context_Control *the_context, |
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225 | uint32_t *stack_base, |
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226 | uint32_t size, |
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227 | uint32_t new_level, |
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228 | void *entry_point, |
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229 | boolean is_fp |
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230 | ) |
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231 | { |
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232 | uint32_t msr_value; |
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233 | uint32_t sp; |
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234 | |
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235 | sp = (uint32_t)stack_base + size - PPC_MINIMUM_STACK_FRAME_SIZE; |
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236 | *((uint32_t*)sp) = 0; |
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237 | the_context->gpr1 = sp; |
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238 | |
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239 | the_context->msr = _CPU_ISR_Calculate_level( new_level ); |
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240 | |
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241 | /* |
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242 | * The FP bit of the MSR should only be enabled if this is a floating |
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243 | * point task. Unfortunately, the vfprintf_r routine in newlib |
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244 | * ends up pushing a floating point register regardless of whether or |
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245 | * not a floating point number is being printed. Serious restructuring |
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246 | * of vfprintf.c will be required to avoid this behavior. At this |
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247 | * time (7 July 1997), this restructuring is not being done. |
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248 | */ |
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249 | |
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250 | /*if ( is_fp ) */ |
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251 | the_context->msr |= PPC_MSR_FP; |
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252 | |
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253 | /* |
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254 | * Calculate the task's MSR value: |
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255 | * |
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256 | * + Set the exception prefix bit to point to the exception table |
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257 | * + Force the RI bit |
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258 | * + Use the DR and IR bits |
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259 | */ |
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260 | _CPU_MSR_GET( msr_value ); |
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261 | the_context->msr |= (msr_value & PPC_MSR_EP); |
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262 | the_context->msr |= PPC_MSR_RI; |
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263 | the_context->msr |= msr_value & (PPC_MSR_DR|PPC_MSR_IR); |
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264 | |
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265 | #if (PPC_ABI == PPC_ABI_SVR4) |
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266 | { unsigned r13 = 0; |
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267 | asm volatile ("mr %0, 13" : "=r" ((r13))); |
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268 | |
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269 | the_context->pc = (uint32_t)entry_point; |
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270 | the_context->gpr13 = r13; |
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271 | } |
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272 | #endif |
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273 | |
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274 | #if (PPC_ABI == PPC_ABI_EABI) |
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275 | { uint32_t r2 = 0; |
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276 | unsigned r13 = 0; |
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277 | asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13))); |
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278 | |
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279 | the_context->pc = (uint32_t)entry_point; |
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280 | the_context->gpr2 = r2; |
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281 | the_context->gpr13 = r13; |
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282 | } |
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283 | #endif |
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284 | } |
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285 | |
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286 | /* _CPU_ISR_install_vector |
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287 | * |
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288 | * This kernel routine installs the RTEMS handler for the |
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289 | * specified vector. |
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290 | * |
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291 | * Input parameters: |
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292 | * vector - interrupt vector number |
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293 | * old_handler - former ISR for this vector number |
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294 | * new_handler - replacement ISR for this vector number |
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295 | * |
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296 | * Output parameters: NONE |
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297 | * |
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298 | */ |
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299 | |
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300 | void _CPU_ISR_install_vector( |
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301 | uint32_t vector, |
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302 | proc_ptr new_handler, |
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303 | proc_ptr *old_handler |
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304 | ) |
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305 | { |
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306 | proc_ptr ignored; |
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307 | *old_handler = _ISR_Vector_table[ vector ]; |
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308 | |
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309 | /* |
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310 | * If the interrupt vector table is a table of pointer to isr entry |
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311 | * points, then we need to install the appropriate RTEMS interrupt |
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312 | * handler for this vector number. |
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313 | */ |
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314 | |
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315 | /* |
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316 | * Install the wrapper so this ISR can be invoked properly. |
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317 | */ |
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318 | if (_CPU_Table.exceptions_in_RAM) |
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319 | _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); |
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320 | |
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321 | /* |
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322 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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323 | * be used by the _ISR_Handler so the user gets control. |
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324 | */ |
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325 | |
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326 | _ISR_Vector_table[ vector ] = new_handler ? (ISR_Handler_entry)new_handler : |
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327 | _CPU_Table.spurious_handler ? |
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328 | (ISR_Handler_entry)_CPU_Table.spurious_handler : |
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329 | (ISR_Handler_entry)ppc_spurious; |
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330 | } |
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331 | |
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332 | /*PAGE |
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333 | * |
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334 | * _CPU_Install_interrupt_stack |
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335 | */ |
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336 | |
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337 | void _CPU_Install_interrupt_stack( void ) |
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338 | { |
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339 | /* PPC_ABI_EABI */ |
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340 | _CPU_IRQ_info.Stack = _CPU_Interrupt_stack_high - 8; |
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341 | } |
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342 | |
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343 | /* Handle a spurious interrupt */ |
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344 | static void ppc_spurious(int v, CPU_Interrupt_frame *i) |
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345 | { |
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346 | #if 0 |
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347 | printf("Spurious interrupt on vector %d from %08.8x\n", |
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348 | v, i->pc); |
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349 | #endif |
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350 | #if defined(ppc403) || defined(ppc405) |
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351 | if (v == PPC_IRQ_EXTERNAL) |
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352 | { |
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353 | register int r = 0; |
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354 | |
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355 | asm volatile("mtdcr 0x42, %0" : |
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356 | "=&r" ((r)) : "0" ((r))); /* EXIER */ |
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357 | } |
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358 | else if (v == PPC_IRQ_PIT) |
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359 | { |
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360 | register int r = 0x08000000; |
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361 | |
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362 | asm volatile("mtspr 0x3d8, %0" : |
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363 | "=&r" ((r)) : "0" ((r))); /* TSR */ |
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364 | } |
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365 | else if (v == PPC_IRQ_FIT) |
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366 | { |
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367 | register int r = 0x04000000; |
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368 | |
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369 | asm volatile("mtspr 0x3d8, %0" : |
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370 | "=&r" ((r)) : "0" ((r))); /* TSR */ |
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371 | } |
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372 | #endif |
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373 | ++_CPU_spurious_count; |
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374 | _CPU_last_spurious = v; |
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375 | } |
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376 | |
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377 | void _CPU_Fatal_error(uint32_t _error) |
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378 | { |
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379 | asm volatile ("mr 3, %0" : : "r" ((_error))); |
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380 | asm volatile ("tweq 5,5"); |
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381 | asm volatile ("li 0,0; mtmsr 0"); |
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382 | while (1) ; |
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383 | } |
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384 | |
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385 | #define PPC_SYNCHRONOUS_TRAP_BIT_MASK 0x100 |
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386 | #define PPC_ASYNCHRONOUS_TRAP( _trap ) (_trap) |
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387 | #define PPC_SYNCHRONOUS_TRAP ( _trap ) ((_trap)+PPC_SYNCHRONOUS_TRAP_BIT_MASK) |
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388 | #define PPC_REAL_TRAP_NUMBER ( _trap ) ((_trap)%PPC_SYNCHRONOUS_TRAP_BIT_MASK) |
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389 | |
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390 | const CPU_Trap_table_entry _CPU_Trap_slot_template = { |
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391 | |
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392 | 0x9421ff90, /* stwu r1, -(IP_END)(r1) */ |
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393 | |
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394 | 0x90010008, /* stw %r0, IP_0(%r1) */ |
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395 | 0x38000000, /* li %r0, PPC_IRQ */ |
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396 | 0x48000002 /* ba PROC (_ISR_Handler) */ |
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397 | }; |
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398 | |
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399 | #if defined(mpc860) || defined(mpc821) |
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400 | const CPU_Trap_table_entry _CPU_Trap_slot_template_m860 = { |
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401 | 0x7c0803ac, /* mtlr %r0 */ |
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402 | 0x81210028, /* lwz %r9, IP_9(%r1) */ |
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403 | 0x38000000, /* li %r0, PPC_IRQ */ |
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404 | 0x48000002 /* b PROC (_ISR_Handler) */ |
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405 | }; |
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406 | #endif /* mpc860 */ |
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407 | |
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408 | uint32_t ppc_exception_vector_addr( |
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409 | uint32_t vector |
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410 | ); |
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411 | |
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412 | /*PAGE |
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413 | * |
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414 | * _CPU_ISR_install_raw_handler |
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415 | * |
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416 | * This routine installs the specified handler as a "raw" non-executive |
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417 | * supported trap handler (a.k.a. interrupt service routine). |
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418 | * |
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419 | * Input Parameters: |
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420 | * vector - trap table entry number plus synchronous |
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421 | * vs. asynchronous information |
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422 | * new_handler - address of the handler to be installed |
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423 | * old_handler - pointer to an address of the handler previously installed |
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424 | * |
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425 | * Output Parameters: NONE |
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426 | * *new_handler - address of the handler previously installed |
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427 | * |
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428 | * NOTE: |
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429 | * |
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430 | * This routine is based on the SPARC routine _CPU_ISR_install_raw_handler. |
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431 | * Install a software trap handler as an executive interrupt handler |
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432 | * (which is desirable since RTEMS takes care of window and register issues), |
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433 | * then the executive needs to know that the return address is to the trap |
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434 | * rather than the instruction following the trap. |
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435 | * |
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436 | */ |
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437 | |
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438 | void _CPU_ISR_install_raw_handler( |
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439 | uint32_t vector, |
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440 | proc_ptr new_handler, |
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441 | proc_ptr *old_handler |
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442 | ) |
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443 | { |
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444 | uint32_t real_vector; |
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445 | CPU_Trap_table_entry *slot; |
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446 | uint32_t u32_handler=0; |
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447 | |
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448 | /* |
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449 | * Get the "real" trap number for this vector ignoring the synchronous |
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450 | * versus asynchronous indicator included with our vector numbers. |
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451 | */ |
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452 | |
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453 | real_vector = vector; |
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454 | |
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455 | /* |
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456 | * Get the current base address of the trap table and calculate a pointer |
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457 | * to the slot we are interested in. |
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458 | */ |
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459 | slot = (CPU_Trap_table_entry *)ppc_exception_vector_addr( real_vector ); |
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460 | |
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461 | /* |
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462 | * Get the address of the old_handler from the trap table. |
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463 | * |
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464 | * NOTE: The old_handler returned will be bogus if it does not follow |
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465 | * the RTEMS model. |
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466 | */ |
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467 | |
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468 | #define HIGH_BITS_MASK 0xFFFFFC00 |
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469 | #define HIGH_BITS_SHIFT 10 |
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470 | #define LOW_BITS_MASK 0x000003FF |
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471 | |
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472 | if (slot->stwu_r1 == _CPU_Trap_slot_template.stwu_r1) { |
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473 | /* |
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474 | * Set u32_handler = to target address |
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475 | */ |
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476 | u32_handler = slot->b_Handler & 0x03fffffc; |
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477 | |
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478 | /* IMD FIX: sign extend address fragment... */ |
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479 | if (u32_handler & 0x02000000) { |
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480 | u32_handler |= 0xfc000000; |
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481 | } |
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482 | |
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483 | *old_handler = (proc_ptr) u32_handler; |
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484 | } else |
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485 | /* There are two kinds of handlers for the MPC860. One is the 'standard' |
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486 | * one like above. The other is for the cascaded interrupts from the SIU |
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487 | * and CPM. Therefore we must check for the alternate one if the standard |
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488 | * one is not present |
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489 | */ |
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490 | #if defined(mpc860) || defined(mpc821) |
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491 | if (slot->stwu_r1 == _CPU_Trap_slot_template_m860.stwu_r1) { |
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492 | /* |
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493 | * Set u32_handler = to target address |
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494 | */ |
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495 | u32_handler = slot->b_Handler & 0x03fffffc; |
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496 | *old_handler = (proc_ptr) u32_handler; |
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497 | } else |
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498 | #endif /* mpc860 */ |
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499 | |
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500 | *old_handler = 0; |
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501 | |
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502 | /* |
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503 | * Copy the template to the slot and then fix it. |
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504 | */ |
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505 | #if defined(mpc860) || defined(mpc821) |
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506 | if (vector >= PPC_IRQ_IRQ0) |
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507 | *slot = _CPU_Trap_slot_template_m860; |
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508 | else |
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509 | #endif /* mpc860 */ |
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510 | *slot = _CPU_Trap_slot_template; |
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511 | |
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512 | u32_handler = (uint32_t) new_handler; |
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513 | |
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514 | /* |
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515 | * IMD FIX: insert address fragment only (bits 6..29) |
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516 | * therefore check for proper address range |
---|
517 | * and remove unwanted bits |
---|
518 | */ |
---|
519 | if ((u32_handler & 0xfc000000) == 0xfc000000) { |
---|
520 | u32_handler &= ~0xfc000000; |
---|
521 | } |
---|
522 | else if ((u32_handler & 0xfc000000) != 0x00000000) { |
---|
523 | _Internal_error_Occurred(INTERNAL_ERROR_CORE, |
---|
524 | TRUE, |
---|
525 | u32_handler); |
---|
526 | } |
---|
527 | |
---|
528 | slot->b_Handler |= u32_handler; |
---|
529 | |
---|
530 | slot->li_r0_IRQ |= vector; |
---|
531 | |
---|
532 | _CPU_Data_Cache_Block_Flush( slot ); |
---|
533 | } |
---|
534 | |
---|
535 | uint32_t ppc_exception_vector_addr( |
---|
536 | uint32_t vector |
---|
537 | ) |
---|
538 | { |
---|
539 | #if (!PPC_HAS_EVPR) |
---|
540 | uint32_t Msr; |
---|
541 | #endif |
---|
542 | uint32_t Top = 0; |
---|
543 | uint32_t Offset = 0x000; |
---|
544 | |
---|
545 | #if (PPC_HAS_EXCEPTION_PREFIX) |
---|
546 | _CPU_MSR_GET ( Msr ); |
---|
547 | if ( ( Msr & PPC_MSR_EP) != 0 ) /* Vectors at FFFx_xxxx */ |
---|
548 | Top = 0xfff00000; |
---|
549 | #elif (PPC_HAS_EVPR) |
---|
550 | asm volatile( "mfspr %0,0x3d6" : "=r" (Top)); /* EVPR */ |
---|
551 | Top = Top & 0xffff0000; |
---|
552 | #endif |
---|
553 | |
---|
554 | switch ( vector ) { |
---|
555 | case PPC_IRQ_SYSTEM_RESET: /* on 40x aka PPC_IRQ_CRIT */ |
---|
556 | Offset = 0x00100; |
---|
557 | break; |
---|
558 | case PPC_IRQ_MCHECK: |
---|
559 | Offset = 0x00200; |
---|
560 | break; |
---|
561 | case PPC_IRQ_PROTECT: |
---|
562 | Offset = 0x00300; |
---|
563 | break; |
---|
564 | case PPC_IRQ_ISI: |
---|
565 | Offset = 0x00400; |
---|
566 | break; |
---|
567 | case PPC_IRQ_EXTERNAL: |
---|
568 | Offset = 0x00500; |
---|
569 | break; |
---|
570 | case PPC_IRQ_ALIGNMENT: |
---|
571 | Offset = 0x00600; |
---|
572 | break; |
---|
573 | case PPC_IRQ_PROGRAM: |
---|
574 | Offset = 0x00700; |
---|
575 | break; |
---|
576 | case PPC_IRQ_NOFP: |
---|
577 | Offset = 0x00800; |
---|
578 | break; |
---|
579 | case PPC_IRQ_DECREMENTER: |
---|
580 | Offset = 0x00900; |
---|
581 | break; |
---|
582 | case PPC_IRQ_RESERVED_A: |
---|
583 | Offset = 0x00a00; |
---|
584 | break; |
---|
585 | case PPC_IRQ_RESERVED_B: |
---|
586 | Offset = 0x00b00; |
---|
587 | break; |
---|
588 | case PPC_IRQ_SCALL: |
---|
589 | Offset = 0x00c00; |
---|
590 | break; |
---|
591 | case PPC_IRQ_TRACE: |
---|
592 | Offset = 0x00d00; |
---|
593 | break; |
---|
594 | case PPC_IRQ_FP_ASST: |
---|
595 | Offset = 0x00e00; |
---|
596 | break; |
---|
597 | |
---|
598 | #if defined(ppc403) || defined(ppc405) |
---|
599 | |
---|
600 | /* PPC_IRQ_CRIT is the same vector as PPC_IRQ_RESET |
---|
601 | case PPC_IRQ_CRIT: |
---|
602 | Offset = 0x00100; |
---|
603 | break; |
---|
604 | */ |
---|
605 | case PPC_IRQ_PIT: |
---|
606 | Offset = 0x01000; |
---|
607 | break; |
---|
608 | case PPC_IRQ_FIT: |
---|
609 | Offset = 0x01010; |
---|
610 | break; |
---|
611 | case PPC_IRQ_WATCHDOG: |
---|
612 | Offset = 0x01020; |
---|
613 | break; |
---|
614 | case PPC_IRQ_DEBUG: |
---|
615 | Offset = 0x02000; |
---|
616 | break; |
---|
617 | |
---|
618 | #elif defined(ppc601) |
---|
619 | case PPC_IRQ_TRACE: |
---|
620 | Offset = 0x02000; |
---|
621 | break; |
---|
622 | |
---|
623 | #elif defined(ppc603) || defined(ppc603e) |
---|
624 | case PPC_IRQ_TRANS_MISS: |
---|
625 | Offset = 0x1000; |
---|
626 | break; |
---|
627 | case PPC_IRQ_DATA_LOAD: |
---|
628 | Offset = 0x1100; |
---|
629 | break; |
---|
630 | case PPC_IRQ_DATA_STORE: |
---|
631 | Offset = 0x1200; |
---|
632 | break; |
---|
633 | case PPC_IRQ_ADDR_BRK: |
---|
634 | Offset = 0x1300; |
---|
635 | break; |
---|
636 | case PPC_IRQ_SYS_MGT: |
---|
637 | Offset = 0x1400; |
---|
638 | break; |
---|
639 | |
---|
640 | #elif defined(mpc604) |
---|
641 | case PPC_IRQ_ADDR_BRK: |
---|
642 | Offset = 0x1300; |
---|
643 | break; |
---|
644 | case PPC_IRQ_SYS_MGT: |
---|
645 | Offset = 0x1400; |
---|
646 | break; |
---|
647 | |
---|
648 | #elif defined(mpc860) || defined(mpc821) |
---|
649 | case PPC_IRQ_EMULATE: |
---|
650 | Offset = 0x1000; |
---|
651 | break; |
---|
652 | case PPC_IRQ_INST_MISS: |
---|
653 | Offset = 0x1100; |
---|
654 | break; |
---|
655 | case PPC_IRQ_DATA_MISS: |
---|
656 | Offset = 0x1200; |
---|
657 | break; |
---|
658 | case PPC_IRQ_INST_ERR: |
---|
659 | Offset = 0x1300; |
---|
660 | break; |
---|
661 | case PPC_IRQ_DATA_ERR: |
---|
662 | Offset = 0x1400; |
---|
663 | break; |
---|
664 | case PPC_IRQ_DATA_BPNT: |
---|
665 | Offset = 0x1c00; |
---|
666 | break; |
---|
667 | case PPC_IRQ_INST_BPNT: |
---|
668 | Offset = 0x1d00; |
---|
669 | break; |
---|
670 | case PPC_IRQ_IO_BPNT: |
---|
671 | Offset = 0x1e00; |
---|
672 | break; |
---|
673 | case PPC_IRQ_DEV_PORT: |
---|
674 | Offset = 0x1f00; |
---|
675 | break; |
---|
676 | case PPC_IRQ_IRQ0: |
---|
677 | Offset = 0x2000; |
---|
678 | break; |
---|
679 | case PPC_IRQ_LVL0: |
---|
680 | Offset = 0x2040; |
---|
681 | break; |
---|
682 | case PPC_IRQ_IRQ1: |
---|
683 | Offset = 0x2080; |
---|
684 | break; |
---|
685 | case PPC_IRQ_LVL1: |
---|
686 | Offset = 0x20c0; |
---|
687 | break; |
---|
688 | case PPC_IRQ_IRQ2: |
---|
689 | Offset = 0x2100; |
---|
690 | break; |
---|
691 | case PPC_IRQ_LVL2: |
---|
692 | Offset = 0x2140; |
---|
693 | break; |
---|
694 | case PPC_IRQ_IRQ3: |
---|
695 | Offset = 0x2180; |
---|
696 | break; |
---|
697 | case PPC_IRQ_LVL3: |
---|
698 | Offset = 0x21c0; |
---|
699 | break; |
---|
700 | case PPC_IRQ_IRQ4: |
---|
701 | Offset = 0x2200; |
---|
702 | break; |
---|
703 | case PPC_IRQ_LVL4: |
---|
704 | Offset = 0x2240; |
---|
705 | break; |
---|
706 | case PPC_IRQ_IRQ5: |
---|
707 | Offset = 0x2280; |
---|
708 | break; |
---|
709 | case PPC_IRQ_LVL5: |
---|
710 | Offset = 0x22c0; |
---|
711 | break; |
---|
712 | case PPC_IRQ_IRQ6: |
---|
713 | Offset = 0x2300; |
---|
714 | break; |
---|
715 | case PPC_IRQ_LVL6: |
---|
716 | Offset = 0x2340; |
---|
717 | break; |
---|
718 | case PPC_IRQ_IRQ7: |
---|
719 | Offset = 0x2380; |
---|
720 | break; |
---|
721 | case PPC_IRQ_LVL7: |
---|
722 | Offset = 0x23c0; |
---|
723 | break; |
---|
724 | case PPC_IRQ_CPM_ERROR: |
---|
725 | Offset = 0x2400; |
---|
726 | break; |
---|
727 | case PPC_IRQ_CPM_PC4: |
---|
728 | Offset = 0x2410; |
---|
729 | break; |
---|
730 | case PPC_IRQ_CPM_PC5: |
---|
731 | Offset = 0x2420; |
---|
732 | break; |
---|
733 | case PPC_IRQ_CPM_SMC2: |
---|
734 | Offset = 0x2430; |
---|
735 | break; |
---|
736 | case PPC_IRQ_CPM_SMC1: |
---|
737 | Offset = 0x2440; |
---|
738 | break; |
---|
739 | case PPC_IRQ_CPM_SPI: |
---|
740 | Offset = 0x2450; |
---|
741 | break; |
---|
742 | case PPC_IRQ_CPM_PC6: |
---|
743 | Offset = 0x2460; |
---|
744 | break; |
---|
745 | case PPC_IRQ_CPM_TIMER4: |
---|
746 | Offset = 0x2470; |
---|
747 | break; |
---|
748 | case PPC_IRQ_CPM_RESERVED_8: |
---|
749 | Offset = 0x2480; |
---|
750 | break; |
---|
751 | case PPC_IRQ_CPM_PC7: |
---|
752 | Offset = 0x2490; |
---|
753 | break; |
---|
754 | case PPC_IRQ_CPM_PC8: |
---|
755 | Offset = 0x24a0; |
---|
756 | break; |
---|
757 | case PPC_IRQ_CPM_PC9: |
---|
758 | Offset = 0x24b0; |
---|
759 | break; |
---|
760 | case PPC_IRQ_CPM_TIMER3: |
---|
761 | Offset = 0x24c0; |
---|
762 | break; |
---|
763 | case PPC_IRQ_CPM_RESERVED_D: |
---|
764 | Offset = 0x24d0; |
---|
765 | break; |
---|
766 | case PPC_IRQ_CPM_PC10: |
---|
767 | Offset = 0x24e0; |
---|
768 | break; |
---|
769 | case PPC_IRQ_CPM_PC11: |
---|
770 | Offset = 0x24f0; |
---|
771 | break; |
---|
772 | case PPC_IRQ_CPM_I2C: |
---|
773 | Offset = 0x2500; |
---|
774 | break; |
---|
775 | case PPC_IRQ_CPM_RISC_TIMER: |
---|
776 | Offset = 0x2510; |
---|
777 | break; |
---|
778 | case PPC_IRQ_CPM_TIMER2: |
---|
779 | Offset = 0x2520; |
---|
780 | break; |
---|
781 | case PPC_IRQ_CPM_RESERVED_13: |
---|
782 | Offset = 0x2530; |
---|
783 | break; |
---|
784 | case PPC_IRQ_CPM_IDMA2: |
---|
785 | Offset = 0x2540; |
---|
786 | break; |
---|
787 | case PPC_IRQ_CPM_IDMA1: |
---|
788 | Offset = 0x2550; |
---|
789 | break; |
---|
790 | case PPC_IRQ_CPM_SDMA_ERROR: |
---|
791 | Offset = 0x2560; |
---|
792 | break; |
---|
793 | case PPC_IRQ_CPM_PC12: |
---|
794 | Offset = 0x2570; |
---|
795 | break; |
---|
796 | case PPC_IRQ_CPM_PC13: |
---|
797 | Offset = 0x2580; |
---|
798 | break; |
---|
799 | case PPC_IRQ_CPM_TIMER1: |
---|
800 | Offset = 0x2590; |
---|
801 | break; |
---|
802 | case PPC_IRQ_CPM_PC14: |
---|
803 | Offset = 0x25a0; |
---|
804 | break; |
---|
805 | case PPC_IRQ_CPM_SCC4: |
---|
806 | Offset = 0x25b0; |
---|
807 | break; |
---|
808 | case PPC_IRQ_CPM_SCC3: |
---|
809 | Offset = 0x25c0; |
---|
810 | break; |
---|
811 | case PPC_IRQ_CPM_SCC2: |
---|
812 | Offset = 0x25d0; |
---|
813 | break; |
---|
814 | case PPC_IRQ_CPM_SCC1: |
---|
815 | Offset = 0x25e0; |
---|
816 | break; |
---|
817 | case PPC_IRQ_CPM_PC15: |
---|
818 | Offset = 0x25f0; |
---|
819 | break; |
---|
820 | #endif |
---|
821 | |
---|
822 | } |
---|
823 | Top += Offset; |
---|
824 | return Top; |
---|
825 | } |
---|
826 | |
---|
827 | /*PAGE |
---|
828 | * |
---|
829 | * This is the PowerPC specific implementation of the routine which |
---|
830 | * returns TRUE if an interrupt is in progress. |
---|
831 | * |
---|
832 | * NOTE: This is the same as the generic version. But since the |
---|
833 | * PowerPC is still supporting old and new exception processing |
---|
834 | * models and the new exception processing model has a hardware |
---|
835 | * way of doing this, we have to provide this capability here |
---|
836 | * for symmetry. |
---|
837 | */ |
---|
838 | |
---|
839 | boolean _ISR_Is_in_progress( void ) |
---|
840 | { |
---|
841 | return (_ISR_Nest_level != 0); |
---|
842 | } |
---|
843 | |
---|
844 | const unsigned int _PPC_MSR_DISABLE_MASK = PPC_MSR_DISABLE_MASK; |
---|