source: rtems/c/src/lib/libcpu/powerpc/old-exceptions/cpu.c @ d2df5ee

4.104.114.84.95
Last change on this file since d2df5ee was d2df5ee, checked in by Ralf Corsepius <ralf.corsepius@…>, on Oct 20, 2004 at 8:25:35 AM

2004-10-20 Ralf Corsepius <ralf_corsepius@…>

PR 696/bsps

  • cpu.c: Include bsp.h.
  • Property mode set to 100644
File size: 21.1 KB
Line 
1/*
2 *  PowerPC CPU Dependent Source
3 *
4 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
5 *
6 *  COPYRIGHT (c) 1995 by i-cubed ltd.
7 *
8 *  To anyone who acknowledges that this file is provided "AS IS"
9 *  without any express or implied warranty:
10 *      permission to use, copy, modify, and distribute this file
11 *      for any purpose is hereby granted without fee, provided that
12 *      the above copyright notice and this notice appears in all
13 *      copies, and that the name of i-cubed limited not be used in
14 *      advertising or publicity pertaining to distribution of the
15 *      software without specific, written prior permission.
16 *      i-cubed limited makes no representations about the suitability
17 *      of this software for any purpose.
18 *
19 *  Derived from c/src/exec/cpu/no_cpu/cpu.c:
20 *
21 *  COPYRIGHT (c) 1989-1997.
22 *  On-Line Applications Research Corporation (OAR).
23 *
24 *  The license and distribution terms for this file may be found in
25 *  the file LICENSE in this distribution or at
26 *  http://www.rtems.com/license/LICENSE.
27 *
28 *  $Id$
29 */
30
31#include <bsp.h>
32#include <rtems/system.h>
33#include <rtems/score/isr.h>
34#include <rtems/score/context.h>
35#include <rtems/score/thread.h>
36#include <rtems/score/interr.h>
37
38#include <rtems/powerpc/cache.h>
39
40/*
41 *  These are for testing purposes.
42 */
43
44/*  _CPU_Initialize
45 *
46 *  This routine performs processor dependent initialization.
47 *
48 *  INPUT PARAMETERS:
49 *    cpu_table       - CPU table to initialize
50 *    thread_dispatch - address of disptaching routine
51 */
52
53static void ppc_spurious(int, CPU_Interrupt_frame *);
54
55int _CPU_spurious_count = 0;
56int _CPU_last_spurious = 0;
57
58void _CPU_Initialize(
59  rtems_cpu_table  *cpu_table,
60  void      (*thread_dispatch)      /* ignored on this CPU */
61)
62{
63#if (PPC_USE_SPRG)
64  int i;
65#endif
66#if (PPC_ABI != PPC_ABI_POWEROPEN)
67  register uint32_t   r2 = 0;
68#if (PPC_ABI != PPC_ABI_GCC27)
69  register uint32_t   r13 = 0;
70
71  asm ("mr %0,13" : "=r" ((r13)) : "0" ((r13)));
72  _CPU_IRQ_info.Default_r13 = r13;
73#endif
74
75  asm ("mr %0,2" : "=r" ((r2)) : "0" ((r2)));
76  _CPU_IRQ_info.Default_r2 = r2;
77#endif
78
79  _CPU_IRQ_info.Nest_level = &_ISR_Nest_level;
80  _CPU_IRQ_info.Disable_level = &_Thread_Dispatch_disable_level;
81  /* fill in _CPU_IRQ_info.Vector_table later */
82#if (PPC_ABI == PPC_ABI_POWEROPEN)
83  _CPU_IRQ_info.Dispatch_r2 = ((uint32_t*)_Thread_Dispatch)[1];
84#endif
85  _CPU_IRQ_info.Switch_necessary = &_Context_Switch_necessary;
86  _CPU_IRQ_info.Signal = &_ISR_Signals_to_thread_executing;
87
88#if (PPC_USE_SPRG)
89  i = (int)&_CPU_IRQ_info;
90  asm volatile("mtspr 0x113, %0" : "=r" (i) : "0" (i)); /* SPRG 3 */
91#endif
92
93  /*
94   * Store Msr Value in the IRQ info structure.
95   */
96   _CPU_MSR_Value(_CPU_IRQ_info.msr_initial);
97
98#if (PPC_USE_SPRG)
99  i = _CPU_IRQ_info.msr_initial;
100  asm volatile("mtspr 0x112, %0" : "=r" (i) : "0" (i)); /* SPRG 2 */
101#endif
102
103  _CPU_Table = *cpu_table;
104}
105
106/*
107 *  _CPU_Initialize_vectors()
108 *
109 *  Support routine to initialize the RTEMS vector table after it is allocated.
110 *
111 *  PowerPC Specific Information:
112 *
113 *  Complete initialization since the table is now allocated.
114 */
115
116void _CPU_Initialize_vectors(void)
117{
118  int i;
119  proc_ptr handler = (proc_ptr)ppc_spurious;
120
121  _CPU_IRQ_info.Vector_table = _ISR_Vector_table;
122
123  if ( _CPU_Table.spurious_handler )
124    handler = (proc_ptr)_CPU_Table.spurious_handler;
125
126  for (i = 0; i < PPC_INTERRUPT_MAX;  i++)
127    _ISR_Vector_table[i] = handler;
128
129}
130
131/*PAGE
132 *
133 *  _CPU_ISR_Calculate_level
134 *
135 *  The PowerPC puts its interrupt enable status in the MSR register
136 *  which also contains things like endianness control.  To be more
137 *  awkward, the layout varies from processor to processor.  This
138 *  is why it was necessary to adopt a scheme which allowed the user
139 *  to specify specifically which interrupt sources were enabled.
140 */
141
142uint32_t   _CPU_ISR_Calculate_level(
143  uint32_t   new_level
144)
145{
146  register uint32_t   new_msr = 0;
147
148  /*
149   *  Set the critical interrupt enable bit
150   */
151
152#if (PPC_HAS_RFCI)
153  if ( !(new_level & PPC_INTERRUPT_LEVEL_CE) )
154    new_msr |= PPC_MSR_CE;
155#endif
156
157  if ( !(new_level & PPC_INTERRUPT_LEVEL_ME) )
158    new_msr |= PPC_MSR_ME;
159
160  if ( !(new_level & PPC_INTERRUPT_LEVEL_EE) )
161    new_msr |= PPC_MSR_EE;
162
163  return new_msr;
164}
165
166/*PAGE
167 *
168 *  _CPU_ISR_Set_level
169 *
170 *  This routine sets the requested level in the MSR.
171 */
172
173void _CPU_ISR_Set_level(
174  uint32_t   new_level
175)
176{
177  register uint32_t   tmp = 0;
178  register uint32_t   new_msr;
179
180  new_msr = _CPU_ISR_Calculate_level( new_level );
181
182  asm volatile (
183    "mfmsr %0; andc %0,%0,%1; and %2, %2, %1; or %0, %0, %2; mtmsr %0" :
184    "=&r" ((tmp)) :
185    "r" ((PPC_MSR_DISABLE_MASK)), "r" ((new_msr)), "0" ((tmp))
186  );
187}
188
189/*PAGE
190 *
191 *  _CPU_ISR_Get_level
192 *
193 *  This routine gets the current interrupt level from the MSR and
194 *  converts it to an RTEMS interrupt level.
195 */
196
197uint32_t   _CPU_ISR_Get_level( void )
198{
199  uint32_t   level = 0;
200  uint32_t   msr;
201
202  asm volatile("mfmsr %0" : "=r" ((msr)));
203
204  msr &= PPC_MSR_DISABLE_MASK;
205
206  /*
207   *  Set the critical interrupt enable bit
208   */
209
210#if (PPC_HAS_RFCI)
211  if ( !(msr & PPC_MSR_CE) )
212    level |= PPC_INTERRUPT_LEVEL_CE;
213#endif
214
215  if ( !(msr & PPC_MSR_ME) )
216    level |= PPC_INTERRUPT_LEVEL_ME;
217
218  if ( !(msr & PPC_MSR_EE) )
219    level |= PPC_INTERRUPT_LEVEL_EE;
220
221  return level;
222}
223
224/*PAGE
225 *
226 *  _CPU_Context_Initialize
227 */
228
229#if (PPC_ABI == PPC_ABI_POWEROPEN)
230#define CPU_MINIMUM_STACK_FRAME_SIZE 56
231#else /* PPC_ABI_SVR4 or PPC_ABI_EABI */
232#define CPU_MINIMUM_STACK_FRAME_SIZE 8
233#endif
234
235void _CPU_Context_Initialize(
236  Context_Control  *the_context,
237  uint32_t         *stack_base,
238  uint32_t          size,
239  uint32_t          new_level,
240  void             *entry_point,
241  boolean           is_fp
242)
243{
244  uint32_t   msr_value;
245  uint32_t   sp;
246
247  sp = (uint32_t)stack_base + size - CPU_MINIMUM_STACK_FRAME_SIZE;
248  *((uint32_t*)sp) = 0;
249  the_context->gpr1 = sp;
250
251  the_context->msr = _CPU_ISR_Calculate_level( new_level );
252
253  /*
254   *  The FP bit of the MSR should only be enabled if this is a floating
255   *  point task.  Unfortunately, the vfprintf_r routine in newlib
256   *  ends up pushing a floating point register regardless of whether or
257   *  not a floating point number is being printed.  Serious restructuring
258   *  of vfprintf.c will be required to avoid this behavior.  At this
259   *  time (7 July 1997), this restructuring is not being done.
260   */
261
262  /*if ( is_fp ) */
263    the_context->msr |= PPC_MSR_FP;
264
265  /*
266   *  Calculate the task's MSR value:
267   *
268   *     + Set the exception prefix bit to point to the exception table
269   *     + Force the RI bit
270   *     + Use the DR and IR bits
271   */
272  _CPU_MSR_Value( msr_value );
273  the_context->msr |= (msr_value & PPC_MSR_EP);
274  the_context->msr |= PPC_MSR_RI;
275  the_context->msr |= msr_value & (PPC_MSR_DR|PPC_MSR_IR);
276
277#if (PPC_ABI == PPC_ABI_POWEROPEN)
278  { uint32_t   *desc = (uint32_t*)entry_point;
279
280    the_context->pc = desc[0];
281    the_context->gpr2 = desc[1];
282  }
283#endif
284
285#if (PPC_ABI == PPC_ABI_SVR4)
286  { unsigned    r13 = 0;
287    asm volatile ("mr %0, 13" : "=r" ((r13)));
288
289    the_context->pc = (uint32_t)entry_point;
290    the_context->gpr13 = r13;
291  }
292#endif
293
294#if (PPC_ABI == PPC_ABI_EABI)
295  { uint32_t    r2 = 0;
296    unsigned    r13 = 0;
297    asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
298
299    the_context->pc = (uint32_t)entry_point;
300    the_context->gpr2 = r2;
301    the_context->gpr13 = r13;
302  }
303#endif
304}
305
306/*  _CPU_ISR_install_vector
307 *
308 *  This kernel routine installs the RTEMS handler for the
309 *  specified vector.
310 *
311 *  Input parameters:
312 *    vector      - interrupt vector number
313 *    old_handler - former ISR for this vector number
314 *    new_handler - replacement ISR for this vector number
315 *
316 *  Output parameters:  NONE
317 *
318 */
319
320void _CPU_ISR_install_vector(
321  uint32_t    vector,
322  proc_ptr    new_handler,
323  proc_ptr   *old_handler
324)
325{
326   proc_ptr   ignored;
327   *old_handler = _ISR_Vector_table[ vector ];
328
329   /*
330    *  If the interrupt vector table is a table of pointer to isr entry
331    *  points, then we need to install the appropriate RTEMS interrupt
332    *  handler for this vector number.
333    */
334
335   /*
336    * Install the wrapper so this ISR can be invoked properly.
337    */
338   if (_CPU_Table.exceptions_in_RAM)
339      _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
340
341   /*
342    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
343    *  be used by the _ISR_Handler so the user gets control.
344    */
345
346    _ISR_Vector_table[ vector ] = new_handler ? (ISR_Handler_entry)new_handler :
347       _CPU_Table.spurious_handler ?
348          (ISR_Handler_entry)_CPU_Table.spurious_handler :
349          (ISR_Handler_entry)ppc_spurious;
350}
351
352/*PAGE
353 *
354 *  _CPU_Install_interrupt_stack
355 */
356
357void _CPU_Install_interrupt_stack( void )
358{
359#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
360  _CPU_IRQ_info.Stack = _CPU_Interrupt_stack_high - 56;
361#else
362  _CPU_IRQ_info.Stack = _CPU_Interrupt_stack_high - 8;
363#endif
364}
365
366/* Handle a spurious interrupt */
367static void ppc_spurious(int v, CPU_Interrupt_frame *i)
368{
369#if 0
370    printf("Spurious interrupt on vector %d from %08.8x\n",
371           v, i->pc);
372#endif
373#if defined(ppc403) || defined(ppc405)
374    if (v == PPC_IRQ_EXTERNAL)
375        {
376            register int r = 0;
377
378            asm volatile("mtdcr 0x42, %0" :
379                "=&r" ((r)) : "0" ((r))); /* EXIER */
380        }
381    else if (v == PPC_IRQ_PIT)
382        {
383            register int r = 0x08000000;
384
385            asm volatile("mtspr 0x3d8, %0" :
386                "=&r" ((r)) : "0" ((r))); /* TSR */
387        }
388    else if (v == PPC_IRQ_FIT)
389        {
390            register int r = 0x04000000;
391
392            asm volatile("mtspr 0x3d8, %0" :
393                "=&r" ((r)) : "0" ((r))); /* TSR */
394        }
395#endif
396    ++_CPU_spurious_count;
397    _CPU_last_spurious = v;
398}
399
400void _CPU_Fatal_error(uint32_t   _error)
401{
402  asm volatile ("mr 3, %0" : : "r" ((_error)));
403  asm volatile ("tweq 5,5");
404  asm volatile ("li 0,0; mtmsr 0");
405  while (1) ;
406}
407
408#define PPC_SYNCHRONOUS_TRAP_BIT_MASK    0x100
409#define PPC_ASYNCHRONOUS_TRAP( _trap ) (_trap)
410#define PPC_SYNCHRONOUS_TRAP ( _trap ) ((_trap)+PPC_SYNCHRONOUS_TRAP_BIT_MASK)
411#define PPC_REAL_TRAP_NUMBER ( _trap ) ((_trap)%PPC_SYNCHRONOUS_TRAP_BIT_MASK)
412
413const CPU_Trap_table_entry _CPU_Trap_slot_template = {
414
415#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
416#error " Vector install not tested."
417#if (PPC_HAS_FPU)
418#error " Vector install not tested."
419  0x9421feb0,           /* stwu r1, -(20*4 + 18*8 + IP_END)(r1) */
420#else
421#error " Vector install not tested."
422  0x9421ff40,           /* stwu    r1, -(20*4 + IP_END)(r1)     */
423#endif
424#else
425  0x9421ff90,           /* stwu    r1, -(IP_END)(r1)            */
426#endif
427
428  0x90010008,           /* stw   %r0, IP_0(%r1)                 */
429  0x38000000,           /* li    %r0, PPC_IRQ                   */
430  0x48000002            /* ba    PROC (_ISR_Handler)            */
431};
432
433#if defined(mpc860) || defined(mpc821)
434const CPU_Trap_table_entry _CPU_Trap_slot_template_m860 = {
435  0x7c0803ac,           /* mtlr  %r0                            */
436  0x81210028,           /* lwz   %r9, IP_9(%r1)                 */
437  0x38000000,           /* li    %r0, PPC_IRQ                   */
438  0x48000002            /* b     PROC (_ISR_Handler)            */
439};
440#endif /* mpc860 */
441
442uint32_t    ppc_exception_vector_addr(
443  uint32_t   vector
444);
445
446/*PAGE
447 *
448 *  _CPU_ISR_install_raw_handler
449 *
450 *  This routine installs the specified handler as a "raw" non-executive
451 *  supported trap handler (a.k.a. interrupt service routine).
452 *
453 *  Input Parameters:
454 *    vector      - trap table entry number plus synchronous
455 *                    vs. asynchronous information
456 *    new_handler - address of the handler to be installed
457 *    old_handler - pointer to an address of the handler previously installed
458 *
459 *  Output Parameters: NONE
460 *    *new_handler - address of the handler previously installed
461 *
462 *  NOTE:
463 *
464 *  This routine is based on the SPARC routine _CPU_ISR_install_raw_handler.
465 *  Install a software trap handler as an executive interrupt handler
466 *  (which is desirable since RTEMS takes care of window and register issues),
467 *  then the executive needs to know that the return address is to the trap
468 *  rather than the instruction following the trap.
469 *
470 */
471
472void _CPU_ISR_install_raw_handler(
473  uint32_t    vector,
474  proc_ptr    new_handler,
475  proc_ptr   *old_handler
476)
477{
478  uint32_t               real_vector;
479  CPU_Trap_table_entry  *slot;
480  uint32_t               u32_handler=0;
481
482  /*
483   *  Get the "real" trap number for this vector ignoring the synchronous
484   *  versus asynchronous indicator included with our vector numbers.
485   */
486
487  real_vector = vector;
488
489  /*
490   *  Get the current base address of the trap table and calculate a pointer
491   *  to the slot we are interested in.
492   */
493  slot = (CPU_Trap_table_entry  *)ppc_exception_vector_addr( real_vector );
494
495  /*
496   *  Get the address of the old_handler from the trap table.
497   *
498   *  NOTE: The old_handler returned will be bogus if it does not follow
499   *        the RTEMS model.
500   */
501
502#define HIGH_BITS_MASK   0xFFFFFC00
503#define HIGH_BITS_SHIFT  10
504#define LOW_BITS_MASK    0x000003FF
505
506  if (slot->stwu_r1 == _CPU_Trap_slot_template.stwu_r1) {
507    /*
508     * Set u32_handler = to target address
509     */
510    u32_handler = slot->b_Handler & 0x03fffffc;
511
512    /* IMD FIX: sign extend address fragment... */
513    if (u32_handler & 0x02000000) {
514      u32_handler  |= 0xfc000000;
515    }
516
517    *old_handler =  (proc_ptr) u32_handler;
518  } else
519/* There are two kinds of handlers for the MPC860. One is the 'standard'
520 *  one like above. The other is for the cascaded interrupts from the SIU
521 *  and CPM. Therefore we must check for the alternate one if the standard
522 *  one is not present
523 */
524#if defined(mpc860) || defined(mpc821)
525  if (slot->stwu_r1 == _CPU_Trap_slot_template_m860.stwu_r1) {
526    /*
527     * Set u32_handler = to target address
528     */
529    u32_handler = slot->b_Handler & 0x03fffffc;
530    *old_handler =  (proc_ptr) u32_handler;
531  } else
532#endif /* mpc860 */
533
534    *old_handler = 0;
535
536  /*
537   *  Copy the template to the slot and then fix it.
538   */
539#if defined(mpc860) || defined(mpc821)
540  if (vector >= PPC_IRQ_IRQ0)
541    *slot = _CPU_Trap_slot_template_m860;
542  else
543#endif /* mpc860 */
544  *slot = _CPU_Trap_slot_template;
545
546  u32_handler = (uint32_t) new_handler;
547
548  /*
549   * IMD FIX: insert address fragment only (bits 6..29)
550   *          therefore check for proper address range
551   *          and remove unwanted bits
552   */
553  if ((u32_handler & 0xfc000000) == 0xfc000000) {
554    u32_handler  &= ~0xfc000000;
555  }
556  else if ((u32_handler & 0xfc000000) != 0x00000000) {
557    _Internal_error_Occurred(INTERNAL_ERROR_CORE,
558                             TRUE,
559                             u32_handler);
560  }
561
562  slot->b_Handler |= u32_handler;
563
564  slot->li_r0_IRQ  |= vector;
565
566  _CPU_Data_Cache_Block_Flush( slot );
567}
568
569uint32_t    ppc_exception_vector_addr(
570  uint32_t   vector
571)
572{
573#if (!PPC_HAS_EVPR)
574  uint32_t   Msr;
575#endif
576  uint32_t   Top = 0;
577  uint32_t   Offset = 0x000;
578
579#if (PPC_HAS_EXCEPTION_PREFIX)
580  _CPU_MSR_Value ( Msr );
581  if ( ( Msr & PPC_MSR_EP) != 0 ) /* Vectors at FFFx_xxxx */
582    Top = 0xfff00000;
583#elif (PPC_HAS_EVPR)
584  asm volatile( "mfspr %0,0x3d6" : "=r" (Top)); /* EVPR */
585  Top = Top & 0xffff0000;
586#endif
587
588  switch ( vector ) {
589    case PPC_IRQ_SYSTEM_RESET:   /* on 40x aka PPC_IRQ_CRIT */
590      Offset = 0x00100;
591      break;
592    case PPC_IRQ_MCHECK:
593      Offset = 0x00200;
594      break;
595    case PPC_IRQ_PROTECT:
596      Offset = 0x00300;
597      break;
598    case PPC_IRQ_ISI:
599      Offset = 0x00400;
600      break;
601    case PPC_IRQ_EXTERNAL:
602      Offset = 0x00500;
603      break;
604    case PPC_IRQ_ALIGNMENT:
605      Offset = 0x00600;
606      break;
607    case PPC_IRQ_PROGRAM:
608      Offset = 0x00700;
609      break;
610    case PPC_IRQ_NOFP:
611      Offset = 0x00800;
612      break;
613    case PPC_IRQ_DECREMENTER:
614      Offset = 0x00900;
615      break;
616    case PPC_IRQ_RESERVED_A:
617      Offset = 0x00a00;
618      break;
619    case PPC_IRQ_RESERVED_B:
620      Offset = 0x00b00;
621      break;
622    case PPC_IRQ_SCALL:
623      Offset = 0x00c00;
624      break;
625    case PPC_IRQ_TRACE:
626      Offset = 0x00d00;
627      break;
628    case PPC_IRQ_FP_ASST:
629      Offset = 0x00e00;
630      break;
631
632#if defined(ppc403) || defined(ppc405)
633
634/*  PPC_IRQ_CRIT is the same vector as PPC_IRQ_RESET
635    case PPC_IRQ_CRIT:
636      Offset = 0x00100;
637      break;
638*/
639    case PPC_IRQ_PIT:
640      Offset = 0x01000;
641      break;
642    case PPC_IRQ_FIT:
643      Offset = 0x01010;
644      break;
645    case PPC_IRQ_WATCHDOG:
646      Offset = 0x01020;
647      break;
648    case PPC_IRQ_DEBUG:
649      Offset = 0x02000;
650      break;
651
652#elif defined(ppc601)
653    case PPC_IRQ_TRACE:
654      Offset = 0x02000;
655      break;
656
657#elif defined(ppc603)
658    case PPC_IRQ_TRANS_MISS:
659      Offset = 0x1000;
660      break;
661    case PPC_IRQ_DATA_LOAD:
662      Offset = 0x1100;
663      break;
664    case PPC_IRQ_DATA_STORE:
665      Offset = 0x1200;
666      break;
667    case PPC_IRQ_ADDR_BRK:
668      Offset = 0x1300;
669      break;
670    case PPC_IRQ_SYS_MGT:
671      Offset = 0x1400;
672      break;
673
674#elif defined(ppc603e)
675    case PPC_TLB_INST_MISS:
676      Offset = 0x1000;
677      break;
678    case PPC_TLB_LOAD_MISS:
679      Offset = 0x1100;
680      break;
681    case PPC_TLB_STORE_MISS:
682      Offset = 0x1200;
683      break;
684    case PPC_IRQ_ADDRBRK:
685      Offset = 0x1300;
686      break;
687    case PPC_IRQ_SYS_MGT:
688      Offset = 0x1400;
689      break;
690
691#elif defined(mpc604)
692    case PPC_IRQ_ADDR_BRK:
693      Offset = 0x1300;
694      break;
695    case PPC_IRQ_SYS_MGT:
696      Offset = 0x1400;
697      break;
698
699#elif defined(mpc860) || defined(mpc821)
700    case PPC_IRQ_EMULATE:
701      Offset = 0x1000;
702      break;
703    case PPC_IRQ_INST_MISS:
704      Offset = 0x1100;
705      break;
706    case PPC_IRQ_DATA_MISS:
707      Offset = 0x1200;
708      break;
709    case PPC_IRQ_INST_ERR:
710      Offset = 0x1300;
711      break;
712    case PPC_IRQ_DATA_ERR:
713      Offset = 0x1400;
714      break;
715    case PPC_IRQ_DATA_BPNT:
716      Offset = 0x1c00;
717      break;
718    case PPC_IRQ_INST_BPNT:
719      Offset = 0x1d00;
720      break;
721    case PPC_IRQ_IO_BPNT:
722      Offset = 0x1e00;
723      break;
724    case PPC_IRQ_DEV_PORT:
725      Offset = 0x1f00;
726      break;
727    case PPC_IRQ_IRQ0:
728      Offset = 0x2000;
729      break;
730    case PPC_IRQ_LVL0:
731      Offset = 0x2040;
732      break;
733    case PPC_IRQ_IRQ1:
734      Offset = 0x2080;
735      break;
736    case PPC_IRQ_LVL1:
737      Offset = 0x20c0;
738      break;
739    case PPC_IRQ_IRQ2:
740      Offset = 0x2100;
741      break;
742    case PPC_IRQ_LVL2:
743      Offset = 0x2140;
744      break;
745    case PPC_IRQ_IRQ3:
746      Offset = 0x2180;
747      break;
748    case PPC_IRQ_LVL3:
749      Offset = 0x21c0;
750      break;
751    case PPC_IRQ_IRQ4:
752      Offset = 0x2200;
753      break;
754    case PPC_IRQ_LVL4:
755      Offset = 0x2240;
756      break;
757    case PPC_IRQ_IRQ5:
758      Offset = 0x2280;
759      break;
760    case PPC_IRQ_LVL5:
761      Offset = 0x22c0;
762      break;
763    case PPC_IRQ_IRQ6:
764      Offset = 0x2300;
765      break;
766    case PPC_IRQ_LVL6:
767      Offset = 0x2340;
768      break;
769    case PPC_IRQ_IRQ7:
770      Offset = 0x2380;
771      break;
772    case PPC_IRQ_LVL7:
773      Offset = 0x23c0;
774      break;
775    case PPC_IRQ_CPM_ERROR:
776      Offset = 0x2400;
777      break;
778    case PPC_IRQ_CPM_PC4:
779      Offset = 0x2410;
780      break;
781    case PPC_IRQ_CPM_PC5:
782      Offset = 0x2420;
783      break;
784    case PPC_IRQ_CPM_SMC2:
785      Offset = 0x2430;
786      break;
787    case PPC_IRQ_CPM_SMC1:
788      Offset = 0x2440;
789      break;
790    case PPC_IRQ_CPM_SPI:
791      Offset = 0x2450;
792      break;
793    case PPC_IRQ_CPM_PC6:
794      Offset = 0x2460;
795      break;
796    case PPC_IRQ_CPM_TIMER4:
797      Offset = 0x2470;
798      break;
799    case PPC_IRQ_CPM_RESERVED_8:
800      Offset = 0x2480;
801      break;
802    case PPC_IRQ_CPM_PC7:
803      Offset = 0x2490;
804      break;
805    case PPC_IRQ_CPM_PC8:
806      Offset = 0x24a0;
807      break;
808    case PPC_IRQ_CPM_PC9:
809      Offset = 0x24b0;
810      break;
811    case PPC_IRQ_CPM_TIMER3:
812      Offset = 0x24c0;
813      break;
814    case PPC_IRQ_CPM_RESERVED_D:
815      Offset = 0x24d0;
816      break;
817    case PPC_IRQ_CPM_PC10:
818      Offset = 0x24e0;
819      break;
820    case PPC_IRQ_CPM_PC11:
821      Offset = 0x24f0;
822      break;
823    case PPC_IRQ_CPM_I2C:
824      Offset = 0x2500;
825      break;
826    case PPC_IRQ_CPM_RISC_TIMER:
827      Offset = 0x2510;
828      break;
829    case PPC_IRQ_CPM_TIMER2:
830      Offset = 0x2520;
831      break;
832    case PPC_IRQ_CPM_RESERVED_13:
833      Offset = 0x2530;
834      break;
835    case PPC_IRQ_CPM_IDMA2:
836      Offset = 0x2540;
837      break;
838    case PPC_IRQ_CPM_IDMA1:
839      Offset = 0x2550;
840      break;
841    case PPC_IRQ_CPM_SDMA_ERROR:
842      Offset = 0x2560;
843      break;
844    case PPC_IRQ_CPM_PC12:
845      Offset = 0x2570;
846      break;
847    case PPC_IRQ_CPM_PC13:
848      Offset = 0x2580;
849      break;
850    case PPC_IRQ_CPM_TIMER1:
851      Offset = 0x2590;
852      break;
853    case PPC_IRQ_CPM_PC14:
854      Offset = 0x25a0;
855      break;
856    case PPC_IRQ_CPM_SCC4:
857      Offset = 0x25b0;
858      break;
859    case PPC_IRQ_CPM_SCC3:
860      Offset = 0x25c0;
861      break;
862    case PPC_IRQ_CPM_SCC2:
863      Offset = 0x25d0;
864      break;
865    case PPC_IRQ_CPM_SCC1:
866      Offset = 0x25e0;
867      break;
868    case PPC_IRQ_CPM_PC15:
869      Offset = 0x25f0;
870      break;
871#endif
872
873  }
874  Top += Offset;
875  return Top;
876}
877
878/*PAGE
879 *
880 *  This is the PowerPC specific implementation of the routine which
881 *  returns TRUE if an interrupt is in progress.
882 *
883 *  NOTE: This is the same as the generic version. But since the
884 *        PowerPC is still supporting old and new exception processing
885 *        models and the new exception processing model has a hardware
886 *        way of doing this, we have to provide this capability here
887 *        for symmetry.
888 */
889
890boolean _ISR_Is_in_progress( void )
891{
892  return (_ISR_Nest_level != 0);
893}
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