source: rtems/c/src/lib/libcpu/powerpc/old-exceptions/cpu.c @ 7b828b8

4.104.114.84.95
Last change on this file since 7b828b8 was 7b828b8, checked in by Ralf Corsepius <ralf.corsepius@…>, on Feb 15, 2005 at 1:02:04 PM

2005-02-15 Ralf Corsepius <ralf.corsepius@…>

  • cpu.c: Use _CPU_MSR_GET instead of _CPU_MSR_Value (Unify old/new exception processing API).
  • Property mode set to 100644
File size: 20.0 KB
Line 
1/*
2 *  PowerPC CPU Dependent Source
3 *
4 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
5 *
6 *  COPYRIGHT (c) 1995 by i-cubed ltd.
7 *
8 *  To anyone who acknowledges that this file is provided "AS IS"
9 *  without any express or implied warranty:
10 *      permission to use, copy, modify, and distribute this file
11 *      for any purpose is hereby granted without fee, provided that
12 *      the above copyright notice and this notice appears in all
13 *      copies, and that the name of i-cubed limited not be used in
14 *      advertising or publicity pertaining to distribution of the
15 *      software without specific, written prior permission.
16 *      i-cubed limited makes no representations about the suitability
17 *      of this software for any purpose.
18 *
19 *  Derived from c/src/exec/cpu/no_cpu/cpu.c:
20 *
21 *  COPYRIGHT (c) 1989-1997.
22 *  On-Line Applications Research Corporation (OAR).
23 *
24 *  The license and distribution terms for this file may be found in
25 *  the file LICENSE in this distribution or at
26 *  http://www.rtems.com/license/LICENSE.
27 *
28 *  $Id$
29 */
30
31#include <bsp.h>
32#include <rtems/system.h>
33#include <rtems/score/isr.h>
34#include <rtems/score/context.h>
35#include <rtems/score/thread.h>
36#include <rtems/score/interr.h>
37
38#include <rtems/powerpc/cache.h>
39#include <rtems/powerpc/powerpc.h>
40
41/*
42 *  These are for testing purposes.
43 */
44
45/*  _CPU_Initialize
46 *
47 *  This routine performs processor dependent initialization.
48 *
49 *  INPUT PARAMETERS:
50 *    cpu_table       - CPU table to initialize
51 *    thread_dispatch - address of disptaching routine
52 */
53
54static void ppc_spurious(int, CPU_Interrupt_frame *);
55
56int _CPU_spurious_count = 0;
57int _CPU_last_spurious = 0;
58
59void _CPU_Initialize(
60  rtems_cpu_table  *cpu_table,
61  void      (*thread_dispatch)      /* ignored on this CPU */
62)
63{
64#if (PPC_USE_SPRG)
65  int i;
66#endif
67  register uint32_t   r2 = 0;
68  register uint32_t   r13 = 0;
69
70  asm ("mr %0,13" : "=r" ((r13)) : "0" ((r13)));
71  _CPU_IRQ_info.Default_r13 = r13;
72
73  asm ("mr %0,2" : "=r" ((r2)) : "0" ((r2)));
74  _CPU_IRQ_info.Default_r2 = r2;
75
76  _CPU_IRQ_info.Nest_level = &_ISR_Nest_level;
77  _CPU_IRQ_info.Disable_level = &_Thread_Dispatch_disable_level;
78  /* fill in _CPU_IRQ_info.Vector_table later */
79  _CPU_IRQ_info.Switch_necessary = &_Context_Switch_necessary;
80  _CPU_IRQ_info.Signal = &_ISR_Signals_to_thread_executing;
81
82#if (PPC_USE_SPRG)
83  i = (int)&_CPU_IRQ_info;
84  asm volatile("mtspr 0x113, %0" : "=r" (i) : "0" (i)); /* SPRG 3 */
85#endif
86
87  /*
88   * Store Msr Value in the IRQ info structure.
89   */
90   _CPU_MSR_GET(_CPU_IRQ_info.msr_initial);
91
92#if (PPC_USE_SPRG)
93  i = _CPU_IRQ_info.msr_initial;
94  asm volatile("mtspr 0x112, %0" : "=r" (i) : "0" (i)); /* SPRG 2 */
95#endif
96
97  _CPU_Table = *cpu_table;
98}
99
100/*
101 *  _CPU_Initialize_vectors()
102 *
103 *  Support routine to initialize the RTEMS vector table after it is allocated.
104 *
105 *  PowerPC Specific Information:
106 *
107 *  Complete initialization since the table is now allocated.
108 */
109
110void _CPU_Initialize_vectors(void)
111{
112  int i;
113  proc_ptr handler = (proc_ptr)ppc_spurious;
114
115  _CPU_IRQ_info.Vector_table = _ISR_Vector_table;
116
117  if ( _CPU_Table.spurious_handler )
118    handler = (proc_ptr)_CPU_Table.spurious_handler;
119
120  for (i = 0; i < PPC_INTERRUPT_MAX;  i++)
121    _ISR_Vector_table[i] = handler;
122
123}
124
125/*PAGE
126 *
127 *  _CPU_ISR_Calculate_level
128 *
129 *  The PowerPC puts its interrupt enable status in the MSR register
130 *  which also contains things like endianness control.  To be more
131 *  awkward, the layout varies from processor to processor.  This
132 *  is why it was necessary to adopt a scheme which allowed the user
133 *  to specify specifically which interrupt sources were enabled.
134 */
135
136uint32_t   _CPU_ISR_Calculate_level(
137  uint32_t   new_level
138)
139{
140  register uint32_t   new_msr = 0;
141
142  /*
143   *  Set the critical interrupt enable bit
144   */
145
146#if (PPC_HAS_RFCI)
147  if ( !(new_level & PPC_INTERRUPT_LEVEL_CE) )
148    new_msr |= PPC_MSR_CE;
149#endif
150
151  if ( !(new_level & PPC_INTERRUPT_LEVEL_ME) )
152    new_msr |= PPC_MSR_ME;
153
154  if ( !(new_level & PPC_INTERRUPT_LEVEL_EE) )
155    new_msr |= PPC_MSR_EE;
156
157  return new_msr;
158}
159
160/*PAGE
161 *
162 *  _CPU_ISR_Set_level
163 *
164 *  This routine sets the requested level in the MSR.
165 */
166
167void _CPU_ISR_Set_level(
168  uint32_t   new_level
169)
170{
171  register uint32_t   tmp = 0;
172  register uint32_t   new_msr;
173
174  new_msr = _CPU_ISR_Calculate_level( new_level );
175
176  asm volatile (
177    "mfmsr %0; andc %0,%0,%1; and %2, %2, %1; or %0, %0, %2; mtmsr %0" :
178    "=&r" ((tmp)) :
179    "r" ((PPC_MSR_DISABLE_MASK)), "r" ((new_msr)), "0" ((tmp))
180  );
181}
182
183/*PAGE
184 *
185 *  _CPU_ISR_Get_level
186 *
187 *  This routine gets the current interrupt level from the MSR and
188 *  converts it to an RTEMS interrupt level.
189 */
190
191uint32_t   _CPU_ISR_Get_level( void )
192{
193  uint32_t   level = 0;
194  uint32_t   msr;
195
196  asm volatile("mfmsr %0" : "=r" ((msr)));
197
198  msr &= PPC_MSR_DISABLE_MASK;
199
200  /*
201   *  Set the critical interrupt enable bit
202   */
203
204#if (PPC_HAS_RFCI)
205  if ( !(msr & PPC_MSR_CE) )
206    level |= PPC_INTERRUPT_LEVEL_CE;
207#endif
208
209  if ( !(msr & PPC_MSR_ME) )
210    level |= PPC_INTERRUPT_LEVEL_ME;
211
212  if ( !(msr & PPC_MSR_EE) )
213    level |= PPC_INTERRUPT_LEVEL_EE;
214
215  return level;
216}
217
218/*PAGE
219 *
220 *  _CPU_Context_Initialize
221 */
222
223/* PPC_ABI_SVR4 or PPC_ABI_EABI */
224#define CPU_MINIMUM_STACK_FRAME_SIZE 8
225
226void _CPU_Context_Initialize(
227  Context_Control  *the_context,
228  uint32_t         *stack_base,
229  uint32_t          size,
230  uint32_t          new_level,
231  void             *entry_point,
232  boolean           is_fp
233)
234{
235  uint32_t   msr_value;
236  uint32_t   sp;
237
238  sp = (uint32_t)stack_base + size - CPU_MINIMUM_STACK_FRAME_SIZE;
239  *((uint32_t*)sp) = 0;
240  the_context->gpr1 = sp;
241
242  the_context->msr = _CPU_ISR_Calculate_level( new_level );
243
244  /*
245   *  The FP bit of the MSR should only be enabled if this is a floating
246   *  point task.  Unfortunately, the vfprintf_r routine in newlib
247   *  ends up pushing a floating point register regardless of whether or
248   *  not a floating point number is being printed.  Serious restructuring
249   *  of vfprintf.c will be required to avoid this behavior.  At this
250   *  time (7 July 1997), this restructuring is not being done.
251   */
252
253  /*if ( is_fp ) */
254    the_context->msr |= PPC_MSR_FP;
255
256  /*
257   *  Calculate the task's MSR value:
258   *
259   *     + Set the exception prefix bit to point to the exception table
260   *     + Force the RI bit
261   *     + Use the DR and IR bits
262   */
263  _CPU_MSR_GET( msr_value );
264  the_context->msr |= (msr_value & PPC_MSR_EP);
265  the_context->msr |= PPC_MSR_RI;
266  the_context->msr |= msr_value & (PPC_MSR_DR|PPC_MSR_IR);
267
268#if (PPC_ABI == PPC_ABI_SVR4)
269  { unsigned    r13 = 0;
270    asm volatile ("mr %0, 13" : "=r" ((r13)));
271
272    the_context->pc = (uint32_t)entry_point;
273    the_context->gpr13 = r13;
274  }
275#endif
276
277#if (PPC_ABI == PPC_ABI_EABI)
278  { uint32_t    r2 = 0;
279    unsigned    r13 = 0;
280    asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
281
282    the_context->pc = (uint32_t)entry_point;
283    the_context->gpr2 = r2;
284    the_context->gpr13 = r13;
285  }
286#endif
287}
288
289/*  _CPU_ISR_install_vector
290 *
291 *  This kernel routine installs the RTEMS handler for the
292 *  specified vector.
293 *
294 *  Input parameters:
295 *    vector      - interrupt vector number
296 *    old_handler - former ISR for this vector number
297 *    new_handler - replacement ISR for this vector number
298 *
299 *  Output parameters:  NONE
300 *
301 */
302
303void _CPU_ISR_install_vector(
304  uint32_t    vector,
305  proc_ptr    new_handler,
306  proc_ptr   *old_handler
307)
308{
309   proc_ptr   ignored;
310   *old_handler = _ISR_Vector_table[ vector ];
311
312   /*
313    *  If the interrupt vector table is a table of pointer to isr entry
314    *  points, then we need to install the appropriate RTEMS interrupt
315    *  handler for this vector number.
316    */
317
318   /*
319    * Install the wrapper so this ISR can be invoked properly.
320    */
321   if (_CPU_Table.exceptions_in_RAM)
322      _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
323
324   /*
325    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
326    *  be used by the _ISR_Handler so the user gets control.
327    */
328
329    _ISR_Vector_table[ vector ] = new_handler ? (ISR_Handler_entry)new_handler :
330       _CPU_Table.spurious_handler ?
331          (ISR_Handler_entry)_CPU_Table.spurious_handler :
332          (ISR_Handler_entry)ppc_spurious;
333}
334
335/*PAGE
336 *
337 *  _CPU_Install_interrupt_stack
338 */
339
340void _CPU_Install_interrupt_stack( void )
341{
342/* PPC_ABI_EABI */
343  _CPU_IRQ_info.Stack = _CPU_Interrupt_stack_high - 8;
344}
345
346/* Handle a spurious interrupt */
347static void ppc_spurious(int v, CPU_Interrupt_frame *i)
348{
349#if 0
350    printf("Spurious interrupt on vector %d from %08.8x\n",
351           v, i->pc);
352#endif
353#if defined(ppc403) || defined(ppc405)
354    if (v == PPC_IRQ_EXTERNAL)
355        {
356            register int r = 0;
357
358            asm volatile("mtdcr 0x42, %0" :
359                "=&r" ((r)) : "0" ((r))); /* EXIER */
360        }
361    else if (v == PPC_IRQ_PIT)
362        {
363            register int r = 0x08000000;
364
365            asm volatile("mtspr 0x3d8, %0" :
366                "=&r" ((r)) : "0" ((r))); /* TSR */
367        }
368    else if (v == PPC_IRQ_FIT)
369        {
370            register int r = 0x04000000;
371
372            asm volatile("mtspr 0x3d8, %0" :
373                "=&r" ((r)) : "0" ((r))); /* TSR */
374        }
375#endif
376    ++_CPU_spurious_count;
377    _CPU_last_spurious = v;
378}
379
380void _CPU_Fatal_error(uint32_t   _error)
381{
382  asm volatile ("mr 3, %0" : : "r" ((_error)));
383  asm volatile ("tweq 5,5");
384  asm volatile ("li 0,0; mtmsr 0");
385  while (1) ;
386}
387
388#define PPC_SYNCHRONOUS_TRAP_BIT_MASK    0x100
389#define PPC_ASYNCHRONOUS_TRAP( _trap ) (_trap)
390#define PPC_SYNCHRONOUS_TRAP ( _trap ) ((_trap)+PPC_SYNCHRONOUS_TRAP_BIT_MASK)
391#define PPC_REAL_TRAP_NUMBER ( _trap ) ((_trap)%PPC_SYNCHRONOUS_TRAP_BIT_MASK)
392
393const CPU_Trap_table_entry _CPU_Trap_slot_template = {
394
395  0x9421ff90,           /* stwu    r1, -(IP_END)(r1)            */
396
397  0x90010008,           /* stw   %r0, IP_0(%r1)                 */
398  0x38000000,           /* li    %r0, PPC_IRQ                   */
399  0x48000002            /* ba    PROC (_ISR_Handler)            */
400};
401
402#if defined(mpc860) || defined(mpc821)
403const CPU_Trap_table_entry _CPU_Trap_slot_template_m860 = {
404  0x7c0803ac,           /* mtlr  %r0                            */
405  0x81210028,           /* lwz   %r9, IP_9(%r1)                 */
406  0x38000000,           /* li    %r0, PPC_IRQ                   */
407  0x48000002            /* b     PROC (_ISR_Handler)            */
408};
409#endif /* mpc860 */
410
411uint32_t    ppc_exception_vector_addr(
412  uint32_t   vector
413);
414
415/*PAGE
416 *
417 *  _CPU_ISR_install_raw_handler
418 *
419 *  This routine installs the specified handler as a "raw" non-executive
420 *  supported trap handler (a.k.a. interrupt service routine).
421 *
422 *  Input Parameters:
423 *    vector      - trap table entry number plus synchronous
424 *                    vs. asynchronous information
425 *    new_handler - address of the handler to be installed
426 *    old_handler - pointer to an address of the handler previously installed
427 *
428 *  Output Parameters: NONE
429 *    *new_handler - address of the handler previously installed
430 *
431 *  NOTE:
432 *
433 *  This routine is based on the SPARC routine _CPU_ISR_install_raw_handler.
434 *  Install a software trap handler as an executive interrupt handler
435 *  (which is desirable since RTEMS takes care of window and register issues),
436 *  then the executive needs to know that the return address is to the trap
437 *  rather than the instruction following the trap.
438 *
439 */
440
441void _CPU_ISR_install_raw_handler(
442  uint32_t    vector,
443  proc_ptr    new_handler,
444  proc_ptr   *old_handler
445)
446{
447  uint32_t               real_vector;
448  CPU_Trap_table_entry  *slot;
449  uint32_t               u32_handler=0;
450
451  /*
452   *  Get the "real" trap number for this vector ignoring the synchronous
453   *  versus asynchronous indicator included with our vector numbers.
454   */
455
456  real_vector = vector;
457
458  /*
459   *  Get the current base address of the trap table and calculate a pointer
460   *  to the slot we are interested in.
461   */
462  slot = (CPU_Trap_table_entry  *)ppc_exception_vector_addr( real_vector );
463
464  /*
465   *  Get the address of the old_handler from the trap table.
466   *
467   *  NOTE: The old_handler returned will be bogus if it does not follow
468   *        the RTEMS model.
469   */
470
471#define HIGH_BITS_MASK   0xFFFFFC00
472#define HIGH_BITS_SHIFT  10
473#define LOW_BITS_MASK    0x000003FF
474
475  if (slot->stwu_r1 == _CPU_Trap_slot_template.stwu_r1) {
476    /*
477     * Set u32_handler = to target address
478     */
479    u32_handler = slot->b_Handler & 0x03fffffc;
480
481    /* IMD FIX: sign extend address fragment... */
482    if (u32_handler & 0x02000000) {
483      u32_handler  |= 0xfc000000;
484    }
485
486    *old_handler =  (proc_ptr) u32_handler;
487  } else
488/* There are two kinds of handlers for the MPC860. One is the 'standard'
489 *  one like above. The other is for the cascaded interrupts from the SIU
490 *  and CPM. Therefore we must check for the alternate one if the standard
491 *  one is not present
492 */
493#if defined(mpc860) || defined(mpc821)
494  if (slot->stwu_r1 == _CPU_Trap_slot_template_m860.stwu_r1) {
495    /*
496     * Set u32_handler = to target address
497     */
498    u32_handler = slot->b_Handler & 0x03fffffc;
499    *old_handler =  (proc_ptr) u32_handler;
500  } else
501#endif /* mpc860 */
502
503    *old_handler = 0;
504
505  /*
506   *  Copy the template to the slot and then fix it.
507   */
508#if defined(mpc860) || defined(mpc821)
509  if (vector >= PPC_IRQ_IRQ0)
510    *slot = _CPU_Trap_slot_template_m860;
511  else
512#endif /* mpc860 */
513  *slot = _CPU_Trap_slot_template;
514
515  u32_handler = (uint32_t) new_handler;
516
517  /*
518   * IMD FIX: insert address fragment only (bits 6..29)
519   *          therefore check for proper address range
520   *          and remove unwanted bits
521   */
522  if ((u32_handler & 0xfc000000) == 0xfc000000) {
523    u32_handler  &= ~0xfc000000;
524  }
525  else if ((u32_handler & 0xfc000000) != 0x00000000) {
526    _Internal_error_Occurred(INTERNAL_ERROR_CORE,
527                             TRUE,
528                             u32_handler);
529  }
530
531  slot->b_Handler |= u32_handler;
532
533  slot->li_r0_IRQ  |= vector;
534
535  _CPU_Data_Cache_Block_Flush( slot );
536}
537
538uint32_t    ppc_exception_vector_addr(
539  uint32_t   vector
540)
541{
542#if (!PPC_HAS_EVPR)
543  uint32_t   Msr;
544#endif
545  uint32_t   Top = 0;
546  uint32_t   Offset = 0x000;
547
548#if (PPC_HAS_EXCEPTION_PREFIX)
549  _CPU_MSR_GET ( Msr );
550  if ( ( Msr & PPC_MSR_EP) != 0 ) /* Vectors at FFFx_xxxx */
551    Top = 0xfff00000;
552#elif (PPC_HAS_EVPR)
553  asm volatile( "mfspr %0,0x3d6" : "=r" (Top)); /* EVPR */
554  Top = Top & 0xffff0000;
555#endif
556
557  switch ( vector ) {
558    case PPC_IRQ_SYSTEM_RESET:   /* on 40x aka PPC_IRQ_CRIT */
559      Offset = 0x00100;
560      break;
561    case PPC_IRQ_MCHECK:
562      Offset = 0x00200;
563      break;
564    case PPC_IRQ_PROTECT:
565      Offset = 0x00300;
566      break;
567    case PPC_IRQ_ISI:
568      Offset = 0x00400;
569      break;
570    case PPC_IRQ_EXTERNAL:
571      Offset = 0x00500;
572      break;
573    case PPC_IRQ_ALIGNMENT:
574      Offset = 0x00600;
575      break;
576    case PPC_IRQ_PROGRAM:
577      Offset = 0x00700;
578      break;
579    case PPC_IRQ_NOFP:
580      Offset = 0x00800;
581      break;
582    case PPC_IRQ_DECREMENTER:
583      Offset = 0x00900;
584      break;
585    case PPC_IRQ_RESERVED_A:
586      Offset = 0x00a00;
587      break;
588    case PPC_IRQ_RESERVED_B:
589      Offset = 0x00b00;
590      break;
591    case PPC_IRQ_SCALL:
592      Offset = 0x00c00;
593      break;
594    case PPC_IRQ_TRACE:
595      Offset = 0x00d00;
596      break;
597    case PPC_IRQ_FP_ASST:
598      Offset = 0x00e00;
599      break;
600
601#if defined(ppc403) || defined(ppc405)
602
603/*  PPC_IRQ_CRIT is the same vector as PPC_IRQ_RESET
604    case PPC_IRQ_CRIT:
605      Offset = 0x00100;
606      break;
607*/
608    case PPC_IRQ_PIT:
609      Offset = 0x01000;
610      break;
611    case PPC_IRQ_FIT:
612      Offset = 0x01010;
613      break;
614    case PPC_IRQ_WATCHDOG:
615      Offset = 0x01020;
616      break;
617    case PPC_IRQ_DEBUG:
618      Offset = 0x02000;
619      break;
620
621#elif defined(ppc601)
622    case PPC_IRQ_TRACE:
623      Offset = 0x02000;
624      break;
625
626#elif defined(ppc603) || defined(ppc603e)
627    case PPC_IRQ_TRANS_MISS:
628      Offset = 0x1000;
629      break;
630    case PPC_IRQ_DATA_LOAD:
631      Offset = 0x1100;
632      break;
633    case PPC_IRQ_DATA_STORE:
634      Offset = 0x1200;
635      break;
636    case PPC_IRQ_ADDR_BRK:
637      Offset = 0x1300;
638      break;
639    case PPC_IRQ_SYS_MGT:
640      Offset = 0x1400;
641      break;
642
643#elif defined(mpc604)
644    case PPC_IRQ_ADDR_BRK:
645      Offset = 0x1300;
646      break;
647    case PPC_IRQ_SYS_MGT:
648      Offset = 0x1400;
649      break;
650
651#elif defined(mpc860) || defined(mpc821)
652    case PPC_IRQ_EMULATE:
653      Offset = 0x1000;
654      break;
655    case PPC_IRQ_INST_MISS:
656      Offset = 0x1100;
657      break;
658    case PPC_IRQ_DATA_MISS:
659      Offset = 0x1200;
660      break;
661    case PPC_IRQ_INST_ERR:
662      Offset = 0x1300;
663      break;
664    case PPC_IRQ_DATA_ERR:
665      Offset = 0x1400;
666      break;
667    case PPC_IRQ_DATA_BPNT:
668      Offset = 0x1c00;
669      break;
670    case PPC_IRQ_INST_BPNT:
671      Offset = 0x1d00;
672      break;
673    case PPC_IRQ_IO_BPNT:
674      Offset = 0x1e00;
675      break;
676    case PPC_IRQ_DEV_PORT:
677      Offset = 0x1f00;
678      break;
679    case PPC_IRQ_IRQ0:
680      Offset = 0x2000;
681      break;
682    case PPC_IRQ_LVL0:
683      Offset = 0x2040;
684      break;
685    case PPC_IRQ_IRQ1:
686      Offset = 0x2080;
687      break;
688    case PPC_IRQ_LVL1:
689      Offset = 0x20c0;
690      break;
691    case PPC_IRQ_IRQ2:
692      Offset = 0x2100;
693      break;
694    case PPC_IRQ_LVL2:
695      Offset = 0x2140;
696      break;
697    case PPC_IRQ_IRQ3:
698      Offset = 0x2180;
699      break;
700    case PPC_IRQ_LVL3:
701      Offset = 0x21c0;
702      break;
703    case PPC_IRQ_IRQ4:
704      Offset = 0x2200;
705      break;
706    case PPC_IRQ_LVL4:
707      Offset = 0x2240;
708      break;
709    case PPC_IRQ_IRQ5:
710      Offset = 0x2280;
711      break;
712    case PPC_IRQ_LVL5:
713      Offset = 0x22c0;
714      break;
715    case PPC_IRQ_IRQ6:
716      Offset = 0x2300;
717      break;
718    case PPC_IRQ_LVL6:
719      Offset = 0x2340;
720      break;
721    case PPC_IRQ_IRQ7:
722      Offset = 0x2380;
723      break;
724    case PPC_IRQ_LVL7:
725      Offset = 0x23c0;
726      break;
727    case PPC_IRQ_CPM_ERROR:
728      Offset = 0x2400;
729      break;
730    case PPC_IRQ_CPM_PC4:
731      Offset = 0x2410;
732      break;
733    case PPC_IRQ_CPM_PC5:
734      Offset = 0x2420;
735      break;
736    case PPC_IRQ_CPM_SMC2:
737      Offset = 0x2430;
738      break;
739    case PPC_IRQ_CPM_SMC1:
740      Offset = 0x2440;
741      break;
742    case PPC_IRQ_CPM_SPI:
743      Offset = 0x2450;
744      break;
745    case PPC_IRQ_CPM_PC6:
746      Offset = 0x2460;
747      break;
748    case PPC_IRQ_CPM_TIMER4:
749      Offset = 0x2470;
750      break;
751    case PPC_IRQ_CPM_RESERVED_8:
752      Offset = 0x2480;
753      break;
754    case PPC_IRQ_CPM_PC7:
755      Offset = 0x2490;
756      break;
757    case PPC_IRQ_CPM_PC8:
758      Offset = 0x24a0;
759      break;
760    case PPC_IRQ_CPM_PC9:
761      Offset = 0x24b0;
762      break;
763    case PPC_IRQ_CPM_TIMER3:
764      Offset = 0x24c0;
765      break;
766    case PPC_IRQ_CPM_RESERVED_D:
767      Offset = 0x24d0;
768      break;
769    case PPC_IRQ_CPM_PC10:
770      Offset = 0x24e0;
771      break;
772    case PPC_IRQ_CPM_PC11:
773      Offset = 0x24f0;
774      break;
775    case PPC_IRQ_CPM_I2C:
776      Offset = 0x2500;
777      break;
778    case PPC_IRQ_CPM_RISC_TIMER:
779      Offset = 0x2510;
780      break;
781    case PPC_IRQ_CPM_TIMER2:
782      Offset = 0x2520;
783      break;
784    case PPC_IRQ_CPM_RESERVED_13:
785      Offset = 0x2530;
786      break;
787    case PPC_IRQ_CPM_IDMA2:
788      Offset = 0x2540;
789      break;
790    case PPC_IRQ_CPM_IDMA1:
791      Offset = 0x2550;
792      break;
793    case PPC_IRQ_CPM_SDMA_ERROR:
794      Offset = 0x2560;
795      break;
796    case PPC_IRQ_CPM_PC12:
797      Offset = 0x2570;
798      break;
799    case PPC_IRQ_CPM_PC13:
800      Offset = 0x2580;
801      break;
802    case PPC_IRQ_CPM_TIMER1:
803      Offset = 0x2590;
804      break;
805    case PPC_IRQ_CPM_PC14:
806      Offset = 0x25a0;
807      break;
808    case PPC_IRQ_CPM_SCC4:
809      Offset = 0x25b0;
810      break;
811    case PPC_IRQ_CPM_SCC3:
812      Offset = 0x25c0;
813      break;
814    case PPC_IRQ_CPM_SCC2:
815      Offset = 0x25d0;
816      break;
817    case PPC_IRQ_CPM_SCC1:
818      Offset = 0x25e0;
819      break;
820    case PPC_IRQ_CPM_PC15:
821      Offset = 0x25f0;
822      break;
823#endif
824
825  }
826  Top += Offset;
827  return Top;
828}
829
830/*PAGE
831 *
832 *  This is the PowerPC specific implementation of the routine which
833 *  returns TRUE if an interrupt is in progress.
834 *
835 *  NOTE: This is the same as the generic version. But since the
836 *        PowerPC is still supporting old and new exception processing
837 *        models and the new exception processing model has a hardware
838 *        way of doing this, we have to provide this capability here
839 *        for symmetry.
840 */
841
842boolean _ISR_Is_in_progress( void )
843{
844  return (_ISR_Nest_level != 0);
845}
846
847const unsigned int _PPC_MSR_DISABLE_MASK = PPC_MSR_DISABLE_MASK;
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