source: rtems/c/src/lib/libcpu/powerpc/old-exceptions/cpu.c @ 5e77d129

4.104.114.84.95
Last change on this file since 5e77d129 was 8ef3818, checked in by Joel Sherrill <joel.sherrill@…>, on Jun 12, 2000 at 7:57:02 PM

Patch from John Cotton <john.cotton@…>, Charles-Antoine Gauthier
<charles.gauthier@…>, and Darlene A. Stewart
<Darlene.Stewart@…> to add support for a number of very
significant things:

+ BSPs for many variations on the Motorola MBX8xx board series
+ Cache Manager including initial support for m68040

and PowerPC

+ Rework of mpc8xx libcpu code so all mpc8xx CPUs now use

same code base.

+ Rework of eth_comm BSP to utiltize above.

John reports this works on the 821 and 860

  • Property mode set to 100644
File size: 20.3 KB
Line 
1/*
2 *  PowerPC CPU Dependent Source
3 *
4 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
5 *
6 *  COPYRIGHT (c) 1995 by i-cubed ltd.
7 *
8 *  To anyone who acknowledges that this file is provided "AS IS"
9 *  without any express or implied warranty:
10 *      permission to use, copy, modify, and distribute this file
11 *      for any purpose is hereby granted without fee, provided that
12 *      the above copyright notice and this notice appears in all
13 *      copies, and that the name of i-cubed limited not be used in
14 *      advertising or publicity pertaining to distribution of the
15 *      software without specific, written prior permission.
16 *      i-cubed limited makes no representations about the suitability
17 *      of this software for any purpose.
18 *
19 *  Derived from c/src/exec/cpu/no_cpu/cpu.c:
20 *
21 *  COPYRIGHT (c) 1989-1997.
22 *  On-Line Applications Research Corporation (OAR).
23 *  Copyright assigned to U.S. Government, 1994.
24 *
25 *  The license and distribution terms for this file may be found in
26 *  the file LICENSE in this distribution or at
27 *  http://www.OARcorp.com/rtems/license.html.
28 *
29 *  $Id$
30 */
31
32#include <rtems/system.h>
33#include <rtems/score/isr.h>
34#include <rtems/score/context.h>
35#include <rtems/score/thread.h>
36#include <rtems/score/interr.h>
37
38/*
39 *  These are for testing purposes.
40 */
41
42/*  _CPU_Initialize
43 *
44 *  This routine performs processor dependent initialization.
45 *
46 *  INPUT PARAMETERS:
47 *    cpu_table       - CPU table to initialize
48 *    thread_dispatch - address of disptaching routine
49 */
50
51static void ppc_spurious(int, CPU_Interrupt_frame *);
52
53int _CPU_spurious_count = 0;
54int _CPU_last_spurious = 0;
55
56void _CPU_Initialize(
57  rtems_cpu_table  *cpu_table,
58  void      (*thread_dispatch)      /* ignored on this CPU */
59)
60{
61  proc_ptr handler = (proc_ptr)ppc_spurious;
62  int i;
63#if (PPC_ABI != PPC_ABI_POWEROPEN)
64  register unsigned32 r2 = 0;
65#if (PPC_ABI != PPC_ABI_GCC27)
66  register unsigned32 r13 = 0;
67
68  asm ("mr %0,13" : "=r" ((r13)) : "0" ((r13)));
69  _CPU_IRQ_info.Default_r13 = r13;
70#endif
71
72  asm ("mr %0,2" : "=r" ((r2)) : "0" ((r2)));
73  _CPU_IRQ_info.Default_r2 = r2;
74#endif
75
76  _CPU_IRQ_info.Nest_level = &_ISR_Nest_level;
77  _CPU_IRQ_info.Disable_level = &_Thread_Dispatch_disable_level;
78  _CPU_IRQ_info.Vector_table = _ISR_Vector_table;
79#if (PPC_ABI == PPC_ABI_POWEROPEN)
80  _CPU_IRQ_info.Dispatch_r2 = ((unsigned32 *)_Thread_Dispatch)[1];
81#endif
82  _CPU_IRQ_info.Switch_necessary = &_Context_Switch_necessary;
83  _CPU_IRQ_info.Signal = &_ISR_Signals_to_thread_executing;
84
85#if (PPC_USE_SPRG)
86  i = (int)&_CPU_IRQ_info;
87  asm volatile("mtspr 0x113, %0" : "=r" (i) : "0" (i)); /* SPRG 3 */
88#endif
89
90  /*
91   * Store Msr Value in the IRQ info structure.
92   */
93   _CPU_MSR_Value(_CPU_IRQ_info.msr_initial);
94 
95#if (PPC_USE_SPRG)
96  i = _CPU_IRQ_info.msr_initial;
97  asm volatile("mtspr 0x112, %0" : "=r" (i) : "0" (i)); /* SPRG 2 */
98#endif
99
100  if ( cpu_table->spurious_handler )
101    handler = (proc_ptr)cpu_table->spurious_handler;
102
103  for (i = 0; i < PPC_INTERRUPT_MAX;  i++)
104    _ISR_Vector_table[i] = handler;
105
106  _CPU_Table = *cpu_table;
107}
108
109/*PAGE
110 *
111 *  _CPU_ISR_Calculate_level
112 *
113 *  The PowerPC puts its interrupt enable status in the MSR register
114 *  which also contains things like endianness control.  To be more
115 *  awkward, the layout varies from processor to processor.  This
116 *  is why it was necessary to adopt a scheme which allowed the user
117 *  to specify specifically which interrupt sources were enabled.
118 */
119 
120unsigned32 _CPU_ISR_Calculate_level(
121  unsigned32 new_level
122)
123{
124  register unsigned32 new_msr = 0;
125
126  /*
127   *  Set the critical interrupt enable bit
128   */
129
130#if (PPC_HAS_RFCI)
131  if ( !(new_level & PPC_INTERRUPT_LEVEL_CE) )
132    new_msr |= PPC_MSR_CE;
133#endif
134
135  if ( !(new_level & PPC_INTERRUPT_LEVEL_ME) )
136    new_msr |= PPC_MSR_ME;
137
138  if ( !(new_level & PPC_INTERRUPT_LEVEL_EE) )
139    new_msr |= PPC_MSR_EE;
140
141  return new_msr;
142}
143
144/*PAGE
145 *
146 *  _CPU_ISR_Set_level
147 *
148 *  This routine sets the requested level in the MSR.
149 */
150
151void _CPU_ISR_Set_level(
152  unsigned32 new_level
153)
154{
155  register unsigned32 tmp = 0;
156  register unsigned32 new_msr;
157
158  new_msr = _CPU_ISR_Calculate_level( new_level );
159
160  asm volatile (
161    "mfmsr %0; andc %0,%0,%1; and %2, %2, %1; or %0, %0, %2; mtmsr %0" :
162    "=&r" ((tmp)) :
163    "r" ((PPC_MSR_DISABLE_MASK)), "r" ((new_msr)), "0" ((tmp))
164  );
165}
166
167/*PAGE
168 *
169 *  _CPU_ISR_Get_level
170 *
171 *  This routine gets the current interrupt level from the MSR and
172 *  converts it to an RTEMS interrupt level.
173 */
174
175unsigned32 _CPU_ISR_Get_level( void )
176{
177  unsigned32 level = 0;
178  unsigned32 msr;
179 
180  asm volatile("mfmsr %0" : "=r" ((msr)));
181 
182  msr &= PPC_MSR_DISABLE_MASK;
183
184  /*
185   *  Set the critical interrupt enable bit
186   */
187
188#if (PPC_HAS_RFCI)
189  if ( !(msr & PPC_MSR_CE) )
190    level |= PPC_INTERRUPT_LEVEL_CE;
191#endif
192
193  if ( !(msr & PPC_MSR_ME) )
194    level |= PPC_INTERRUPT_LEVEL_ME;
195
196  if ( !(msr & PPC_MSR_EE) )
197    level |= PPC_INTERRUPT_LEVEL_EE;
198
199  return level;
200}
201
202/*PAGE
203 *
204 *  _CPU_Context_Initialize
205 */
206
207#if (PPC_ABI == PPC_ABI_POWEROPEN)
208#define CPU_MINIMUM_STACK_FRAME_SIZE 56
209#else /* PPC_ABI_SVR4 or PPC_ABI_EABI */
210#define CPU_MINIMUM_STACK_FRAME_SIZE 8
211#endif
212
213void _CPU_Context_Initialize(
214  Context_Control  *the_context,
215  unsigned32       *stack_base,
216  unsigned32        size,
217  unsigned32        new_level,
218  void             *entry_point,
219  boolean           is_fp
220)
221{
222  unsigned32 msr_value;
223  unsigned32 sp;
224
225  sp = (unsigned32)stack_base + size - CPU_MINIMUM_STACK_FRAME_SIZE;
226  *((unsigned32 *)sp) = 0;
227  the_context->gpr1 = sp;
228   
229  the_context->msr = _CPU_ISR_Calculate_level( new_level );
230
231  /*
232   *  The FP bit of the MSR should only be enabled if this is a floating
233   *  point task.  Unfortunately, the vfprintf_r routine in newlib
234   *  ends up pushing a floating point register regardless of whether or
235   *  not a floating point number is being printed.  Serious restructuring
236   *  of vfprintf.c will be required to avoid this behavior.  At this
237   *  time (7 July 1997), this restructuring is not being done.
238   */
239
240  /*if ( is_fp ) */
241    the_context->msr |= PPC_MSR_FP;
242
243  /*
244   *  Calculate the task's MSR value:
245   *
246   *     + Set the exception prefix bit to point to the exception table
247   *     + Force the RI bit
248   *     + Use the DR and IR bits
249   */
250  _CPU_MSR_Value( msr_value );
251  the_context->msr |= (msr_value & PPC_MSR_EP);
252  the_context->msr |= PPC_MSR_RI;
253  the_context->msr |= msr_value & (PPC_MSR_DR|PPC_MSR_IR);
254
255#if (PPC_ABI == PPC_ABI_POWEROPEN)
256  { unsigned32 *desc = (unsigned32 *)entry_point;
257
258    the_context->pc = desc[0];
259    the_context->gpr2 = desc[1];
260  }
261#endif
262
263#if (PPC_ABI == PPC_ABI_SVR4)
264  { unsigned    r13 = 0;
265    asm volatile ("mr %0, 13" : "=r" ((r13)));
266   
267    the_context->pc = (unsigned32)entry_point;
268    the_context->gpr13 = r13;
269  }
270#endif
271
272#if (PPC_ABI == PPC_ABI_EABI)
273  { unsigned32  r2 = 0;
274    unsigned    r13 = 0;
275    asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
276 
277    the_context->pc = (unsigned32)entry_point;
278    the_context->gpr2 = r2;
279    the_context->gpr13 = r13;
280  }
281#endif
282}
283
284
285/*  _CPU_ISR_install_vector
286 *
287 *  This kernel routine installs the RTEMS handler for the
288 *  specified vector.
289 *
290 *  Input parameters:
291 *    vector      - interrupt vector number
292 *    old_handler - former ISR for this vector number
293 *    new_handler - replacement ISR for this vector number
294 *
295 *  Output parameters:  NONE
296 *
297 */
298
299void _CPU_ISR_install_vector(
300  unsigned32  vector,
301  proc_ptr    new_handler,
302  proc_ptr   *old_handler
303)
304{
305   proc_ptr   ignored;
306   *old_handler = _ISR_Vector_table[ vector ];
307
308   /*
309    *  If the interrupt vector table is a table of pointer to isr entry
310    *  points, then we need to install the appropriate RTEMS interrupt
311    *  handler for this vector number.
312    */
313
314   /*
315    * Install the wrapper so this ISR can be invoked properly.
316    */
317   if (_CPU_Table.exceptions_in_RAM) 
318      _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
319
320   /*
321    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
322    *  be used by the _ISR_Handler so the user gets control.
323    */
324
325    _ISR_Vector_table[ vector ] = new_handler ? (ISR_Handler_entry)new_handler :
326       _CPU_Table.spurious_handler ? 
327          (ISR_Handler_entry)_CPU_Table.spurious_handler :
328          (ISR_Handler_entry)ppc_spurious;
329}
330
331/*PAGE
332 *
333 *  _CPU_Install_interrupt_stack
334 */
335
336void _CPU_Install_interrupt_stack( void )
337{
338#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
339  _CPU_IRQ_info.Stack = _CPU_Interrupt_stack_high - 56;
340#else
341  _CPU_IRQ_info.Stack = _CPU_Interrupt_stack_high - 8;
342#endif
343}
344
345/* Handle a spurious interrupt */
346static void ppc_spurious(int v, CPU_Interrupt_frame *i)
347{
348#if 0
349    printf("Spurious interrupt on vector %d from %08.8x\n",
350           v, i->pc);
351#endif
352#ifdef ppc403
353    if (v == PPC_IRQ_EXTERNAL)
354        {
355            register int r = 0;
356
357            asm volatile("mtdcr 0x42, %0" :
358                "=&r" ((r)) : "0" ((r))); /* EXIER */
359        }
360    else if (v == PPC_IRQ_PIT)
361        {
362            register int r = 0x08000000;
363
364            asm volatile("mtspr 0x3d8, %0" :
365                "=&r" ((r)) : "0" ((r))); /* TSR */
366        }
367    else if (v == PPC_IRQ_FIT)
368        {
369            register int r = 0x04000000;
370
371            asm volatile("mtspr 0x3d8, %0" :
372                "=&r" ((r)) : "0" ((r))); /* TSR */
373        }
374#endif
375    ++_CPU_spurious_count;
376    _CPU_last_spurious = v;
377}
378
379void _CPU_Fatal_error(unsigned32 _error)
380{
381  asm volatile ("mr 3, %0" : : "r" ((_error)));
382  asm volatile ("tweq 5,5");
383  asm volatile ("li 0,0; mtmsr 0");
384  while (1) ;
385}
386
387#define PPC_SYNCHRONOUS_TRAP_BIT_MASK    0x100
388#define PPC_ASYNCHRONOUS_TRAP( _trap ) (_trap)
389#define PPC_SYNCHRONOUS_TRAP ( _trap ) ((_trap)+PPC_SYNCHRONOUS_TRAP_BIT_MASK)
390#define PPC_REAL_TRAP_NUMBER ( _trap ) ((_trap)%PPC_SYNCHRONOUS_TRAP_BIT_MASK)
391
392
393const CPU_Trap_table_entry _CPU_Trap_slot_template = {
394
395#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
396#error " Vector install not tested."
397#if (PPC_HAS_FPU)
398#error " Vector install not tested."
399  0x9421feb0,           /* stwu r1, -(20*4 + 18*8 + IP_END)(r1) */
400#else
401#error " Vector install not tested."
402  0x9421ff40,           /* stwu    r1, -(20*4 + IP_END)(r1)     */
403#endif
404#else
405  0x9421ff90,           /* stwu    r1, -(IP_END)(r1)            */
406#endif
407
408  0x90010008,           /* stw   %r0, IP_0(%r1)                 */
409  0x38000000,           /* li    %r0, PPC_IRQ                   */
410  0x48000002            /* ba    PROC (_ISR_Handler)            */
411};
412
413#if defined(mpc860) || defined(mpc821)
414const CPU_Trap_table_entry _CPU_Trap_slot_template_m860 = {
415  0x7c0803ac,           /* mtlr  %r0                            */
416  0x81210028,           /* lwz   %r9, IP_9(%r1)                 */
417  0x38000000,           /* li    %r0, PPC_IRQ                   */
418  0x48000002            /* b     PROC (_ISR_Handler)            */
419};
420#endif /* mpc860 */
421
422unsigned32  ppc_exception_vector_addr( 
423  unsigned32 vector
424);
425
426
427/*PAGE
428 *
429 *  _CPU_ISR_install_raw_handler
430 *
431 *  This routine installs the specified handler as a "raw" non-executive
432 *  supported trap handler (a.k.a. interrupt service routine).
433 *
434 *  Input Parameters:
435 *    vector      - trap table entry number plus synchronous
436 *                    vs. asynchronous information
437 *    new_handler - address of the handler to be installed
438 *    old_handler - pointer to an address of the handler previously installed
439 *
440 *  Output Parameters: NONE
441 *    *new_handler - address of the handler previously installed
442 *
443 *  NOTE:
444 *
445 *  This routine is based on the SPARC routine _CPU_ISR_install_raw_handler.
446 *  Install a software trap handler as an executive interrupt handler
447 *  (which is desirable since RTEMS takes care of window and register issues),
448 *  then the executive needs to know that the return address is to the trap
449 *  rather than the instruction following the trap.
450 *
451 */
452 
453void _CPU_ISR_install_raw_handler(
454  unsigned32  vector,
455  proc_ptr    new_handler,
456  proc_ptr   *old_handler
457)
458{
459  unsigned32             real_vector;
460  CPU_Trap_table_entry  *slot;
461  unsigned32             u32_handler=0;
462
463  /*
464   *  Get the "real" trap number for this vector ignoring the synchronous
465   *  versus asynchronous indicator included with our vector numbers.
466   */
467
468  real_vector = vector;
469
470  /*
471   *  Get the current base address of the trap table and calculate a pointer
472   *  to the slot we are interested in.
473   */
474  slot = (CPU_Trap_table_entry  *)ppc_exception_vector_addr( real_vector );
475
476  /*
477   *  Get the address of the old_handler from the trap table.
478   *
479   *  NOTE: The old_handler returned will be bogus if it does not follow
480   *        the RTEMS model.
481   */
482
483#define HIGH_BITS_MASK   0xFFFFFC00
484#define HIGH_BITS_SHIFT  10
485#define LOW_BITS_MASK    0x000003FF
486
487  if (slot->stwu_r1 == _CPU_Trap_slot_template.stwu_r1) {
488    /*
489     * Set u32_handler = to target address 
490     */
491    u32_handler = slot->b_Handler & 0x03fffffc;
492
493    /* IMD FIX: sign extend address fragment... */
494    if (u32_handler & 0x02000000) {
495      u32_handler  |= 0xfc000000;
496    }
497
498    *old_handler =  (proc_ptr) u32_handler;
499  } else
500/* There are two kinds of handlers for the MPC860. One is the 'standard'
501 *  one like above. The other is for the cascaded interrupts from the SIU
502 *  and CPM. Therefore we must check for the alternate one if the standard
503 *  one is not present
504 */
505#if defined(mpc860) || defined(mpc821)
506  if (slot->stwu_r1 == _CPU_Trap_slot_template_m860.stwu_r1) {
507    /*
508     * Set u32_handler = to target address 
509     */
510    u32_handler = slot->b_Handler & 0x03fffffc;
511    *old_handler =  (proc_ptr) u32_handler;
512  } else
513#endif /* mpc860 */
514
515    *old_handler = 0;
516
517  /*
518   *  Copy the template to the slot and then fix it.
519   */
520#if defined(mpc860) || defined(mpc821)
521  if (vector >= PPC_IRQ_IRQ0)
522    *slot = _CPU_Trap_slot_template_m860;
523  else
524#endif /* mpc860 */
525  *slot = _CPU_Trap_slot_template;
526
527  u32_handler = (unsigned32) new_handler;
528
529  /*
530   * IMD FIX: insert address fragment only (bits 6..29)
531   *          therefore check for proper address range
532   *          and remove unwanted bits
533   */
534  if ((u32_handler & 0xfc000000) == 0xfc000000) {
535    u32_handler  &= ~0xfc000000;
536  }
537  else if ((u32_handler & 0xfc000000) != 0x00000000) {
538    _Internal_error_Occurred(INTERNAL_ERROR_CORE,
539                             TRUE,
540                             u32_handler);
541  }
542
543  slot->b_Handler |= u32_handler;
544
545  slot->li_r0_IRQ  |= vector;
546
547  _CPU_Data_Cache_Block_Flush( slot );
548}
549
550unsigned32  ppc_exception_vector_addr( 
551  unsigned32 vector
552)
553{
554#if (!PPC_HAS_EVPR)
555  unsigned32 Msr;
556#endif
557  unsigned32 Top = 0;
558  unsigned32 Offset = 0x000;
559
560#if (PPC_HAS_EXCEPTION_PREFIX)
561  _CPU_MSR_Value ( Msr );
562  if ( ( Msr & PPC_MSR_EP) != 0 ) /* Vectors at FFFx_xxxx */
563    Top = 0xfff00000;
564#elif (PPC_HAS_EVPR)
565  asm volatile( "mfspr %0,0x3d6" : "=r" (Top)); /* EVPR */
566  Top = Top & 0xffff0000;
567#endif
568
569  switch ( vector ) {
570    case PPC_IRQ_SYSTEM_RESET:   /* on 40x aka PPC_IRQ_CRIT */
571      Offset = 0x00100;
572      break;
573    case PPC_IRQ_MCHECK:
574      Offset = 0x00200;
575      break;
576    case PPC_IRQ_PROTECT:
577      Offset = 0x00300;
578      break;
579    case PPC_IRQ_ISI:
580      Offset = 0x00400;
581      break;
582    case PPC_IRQ_EXTERNAL:
583      Offset = 0x00500;
584      break;
585    case PPC_IRQ_ALIGNMENT:
586      Offset = 0x00600;
587      break;
588    case PPC_IRQ_PROGRAM:
589      Offset = 0x00700;
590      break;
591    case PPC_IRQ_NOFP:
592      Offset = 0x00800;
593      break;
594    case PPC_IRQ_DECREMENTER:
595      Offset = 0x00900;
596      break;
597    case PPC_IRQ_RESERVED_A:
598      Offset = 0x00a00;
599      break;
600    case PPC_IRQ_RESERVED_B:
601      Offset = 0x00b00;
602      break;
603    case PPC_IRQ_SCALL:
604      Offset = 0x00c00;
605      break;
606    case PPC_IRQ_TRACE:
607      Offset = 0x00d00;
608      break;
609    case PPC_IRQ_FP_ASST:
610      Offset = 0x00e00;
611      break;
612
613#if defined(ppc403)
614                                 
615/*  PPC_IRQ_CRIT is the same vector as PPC_IRQ_RESET
616    case PPC_IRQ_CRIT:
617      Offset = 0x00100;
618      break;
619*/
620    case PPC_IRQ_PIT:
621      Offset = 0x01000;
622      break;
623    case PPC_IRQ_FIT:
624      Offset = 0x01010;
625      break;
626    case PPC_IRQ_WATCHDOG:
627      Offset = 0x01020;
628      break;
629    case PPC_IRQ_DEBUG:
630      Offset = 0x02000;
631      break;
632
633#elif defined(ppc601)
634    case PPC_IRQ_TRACE:
635      Offset = 0x02000;
636      break;
637
638#elif defined(ppc603)
639    case PPC_IRQ_TRANS_MISS:
640      Offset = 0x1000;
641      break;
642    case PPC_IRQ_DATA_LOAD:
643      Offset = 0x1100;
644      break;
645    case PPC_IRQ_DATA_STORE:
646      Offset = 0x1200;
647      break;
648    case PPC_IRQ_ADDR_BRK:
649      Offset = 0x1300;
650      break;
651    case PPC_IRQ_SYS_MGT:
652      Offset = 0x1400;
653      break;
654
655#elif defined(ppc603e)
656    case PPC_TLB_INST_MISS:
657      Offset = 0x1000;
658      break;
659    case PPC_TLB_LOAD_MISS:
660      Offset = 0x1100;
661      break;
662    case PPC_TLB_STORE_MISS:
663      Offset = 0x1200;
664      break;
665    case PPC_IRQ_ADDRBRK:
666      Offset = 0x1300;
667      break;
668    case PPC_IRQ_SYS_MGT:
669      Offset = 0x1400;
670      break;
671
672#elif defined(mpc604)
673    case PPC_IRQ_ADDR_BRK:
674      Offset = 0x1300;
675      break;
676    case PPC_IRQ_SYS_MGT:
677      Offset = 0x1400;
678      break;
679
680#elif defined(mpc860) || defined(mpc821)
681    case PPC_IRQ_EMULATE:
682      Offset = 0x1000;
683      break;
684    case PPC_IRQ_INST_MISS:
685      Offset = 0x1100;
686      break;
687    case PPC_IRQ_DATA_MISS:
688      Offset = 0x1200;
689      break;
690    case PPC_IRQ_INST_ERR:
691      Offset = 0x1300;
692      break;
693    case PPC_IRQ_DATA_ERR:
694      Offset = 0x1400;
695      break;
696    case PPC_IRQ_DATA_BPNT:
697      Offset = 0x1c00;
698      break;
699    case PPC_IRQ_INST_BPNT:
700      Offset = 0x1d00;
701      break;
702    case PPC_IRQ_IO_BPNT:
703      Offset = 0x1e00;
704      break;
705    case PPC_IRQ_DEV_PORT:
706      Offset = 0x1f00;
707      break;
708    case PPC_IRQ_IRQ0:
709      Offset = 0x2000;
710      break;
711    case PPC_IRQ_LVL0:
712      Offset = 0x2040;
713      break;
714    case PPC_IRQ_IRQ1:
715      Offset = 0x2080;
716      break;
717    case PPC_IRQ_LVL1:
718      Offset = 0x20c0;
719      break;
720    case PPC_IRQ_IRQ2:
721      Offset = 0x2100;
722      break;
723    case PPC_IRQ_LVL2:
724      Offset = 0x2140;
725      break;
726    case PPC_IRQ_IRQ3:
727      Offset = 0x2180;
728      break;
729    case PPC_IRQ_LVL3:
730      Offset = 0x21c0;
731      break;
732    case PPC_IRQ_IRQ4:
733      Offset = 0x2200;
734      break;
735    case PPC_IRQ_LVL4:
736      Offset = 0x2240;
737      break;
738    case PPC_IRQ_IRQ5:
739      Offset = 0x2280;
740      break;
741    case PPC_IRQ_LVL5:
742      Offset = 0x22c0;
743      break;
744    case PPC_IRQ_IRQ6:
745      Offset = 0x2300;
746      break;
747    case PPC_IRQ_LVL6:
748      Offset = 0x2340;
749      break;
750    case PPC_IRQ_IRQ7:
751      Offset = 0x2380;
752      break;
753    case PPC_IRQ_LVL7:
754      Offset = 0x23c0;
755      break;
756    case PPC_IRQ_CPM_ERROR:
757      Offset = 0x2400;
758      break;
759    case PPC_IRQ_CPM_PC4:
760      Offset = 0x2410;
761      break;
762    case PPC_IRQ_CPM_PC5:
763      Offset = 0x2420;
764      break;
765    case PPC_IRQ_CPM_SMC2:
766      Offset = 0x2430;
767      break;
768    case PPC_IRQ_CPM_SMC1:
769      Offset = 0x2440;
770      break;
771    case PPC_IRQ_CPM_SPI:
772      Offset = 0x2450;
773      break;
774    case PPC_IRQ_CPM_PC6:
775      Offset = 0x2460;
776      break;
777    case PPC_IRQ_CPM_TIMER4:
778      Offset = 0x2470;
779      break;
780    case PPC_IRQ_CPM_RESERVED_8:
781      Offset = 0x2480;
782      break;
783    case PPC_IRQ_CPM_PC7:
784      Offset = 0x2490;
785      break;
786    case PPC_IRQ_CPM_PC8:
787      Offset = 0x24a0;
788      break;
789    case PPC_IRQ_CPM_PC9:
790      Offset = 0x24b0;
791      break;
792    case PPC_IRQ_CPM_TIMER3:
793      Offset = 0x24c0;
794      break;
795    case PPC_IRQ_CPM_RESERVED_D:
796      Offset = 0x24d0;
797      break;
798    case PPC_IRQ_CPM_PC10:
799      Offset = 0x24e0;
800      break;
801    case PPC_IRQ_CPM_PC11:
802      Offset = 0x24f0;
803      break;
804    case PPC_IRQ_CPM_I2C:
805      Offset = 0x2500;
806      break;
807    case PPC_IRQ_CPM_RISC_TIMER:
808      Offset = 0x2510;
809      break;
810    case PPC_IRQ_CPM_TIMER2:
811      Offset = 0x2520;
812      break;
813    case PPC_IRQ_CPM_RESERVED_13:
814      Offset = 0x2530;
815      break;
816    case PPC_IRQ_CPM_IDMA2:
817      Offset = 0x2540;
818      break;
819    case PPC_IRQ_CPM_IDMA1:
820      Offset = 0x2550;
821      break;
822    case PPC_IRQ_CPM_SDMA_ERROR:
823      Offset = 0x2560;
824      break;
825    case PPC_IRQ_CPM_PC12:
826      Offset = 0x2570;
827      break;
828    case PPC_IRQ_CPM_PC13:
829      Offset = 0x2580;
830      break;
831    case PPC_IRQ_CPM_TIMER1:
832      Offset = 0x2590;
833      break;
834    case PPC_IRQ_CPM_PC14:
835      Offset = 0x25a0;
836      break;
837    case PPC_IRQ_CPM_SCC4:
838      Offset = 0x25b0;
839      break;
840    case PPC_IRQ_CPM_SCC3:
841      Offset = 0x25c0;
842      break;
843    case PPC_IRQ_CPM_SCC2:
844      Offset = 0x25d0;
845      break;
846    case PPC_IRQ_CPM_SCC1:
847      Offset = 0x25e0;
848      break;
849    case PPC_IRQ_CPM_PC15:
850      Offset = 0x25f0;
851      break;
852#endif
853
854  }
855  Top += Offset;
856  return Top;
857}
858
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