source: rtems/c/src/lib/libcpu/powerpc/old-exceptions/cpu.c @ 0567cb2

4.104.114.84.95
Last change on this file since 0567cb2 was 0567cb2, checked in by Ralf Corsepius <ralf.corsepius@…>, on Feb 10, 2005 at 3:13:34 PM

2005-02-10 Ralf Corsepius <ralf.corsepius@…>

  • cpu.c, cpu_asm.S, irq_stub.S, rtems/score/ppc_offs.h: Remove PPC_ABI_POWEROPEN.
  • Property mode set to 100644
File size: 20.2 KB
Line 
1/*
2 *  PowerPC CPU Dependent Source
3 *
4 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
5 *
6 *  COPYRIGHT (c) 1995 by i-cubed ltd.
7 *
8 *  To anyone who acknowledges that this file is provided "AS IS"
9 *  without any express or implied warranty:
10 *      permission to use, copy, modify, and distribute this file
11 *      for any purpose is hereby granted without fee, provided that
12 *      the above copyright notice and this notice appears in all
13 *      copies, and that the name of i-cubed limited not be used in
14 *      advertising or publicity pertaining to distribution of the
15 *      software without specific, written prior permission.
16 *      i-cubed limited makes no representations about the suitability
17 *      of this software for any purpose.
18 *
19 *  Derived from c/src/exec/cpu/no_cpu/cpu.c:
20 *
21 *  COPYRIGHT (c) 1989-1997.
22 *  On-Line Applications Research Corporation (OAR).
23 *
24 *  The license and distribution terms for this file may be found in
25 *  the file LICENSE in this distribution or at
26 *  http://www.rtems.com/license/LICENSE.
27 *
28 *  $Id$
29 */
30
31#include <bsp.h>
32#include <rtems/system.h>
33#include <rtems/score/isr.h>
34#include <rtems/score/context.h>
35#include <rtems/score/thread.h>
36#include <rtems/score/interr.h>
37
38#include <rtems/powerpc/cache.h>
39
40/*
41 *  These are for testing purposes.
42 */
43
44/*  _CPU_Initialize
45 *
46 *  This routine performs processor dependent initialization.
47 *
48 *  INPUT PARAMETERS:
49 *    cpu_table       - CPU table to initialize
50 *    thread_dispatch - address of disptaching routine
51 */
52
53static void ppc_spurious(int, CPU_Interrupt_frame *);
54
55int _CPU_spurious_count = 0;
56int _CPU_last_spurious = 0;
57
58void _CPU_Initialize(
59  rtems_cpu_table  *cpu_table,
60  void      (*thread_dispatch)      /* ignored on this CPU */
61)
62{
63#if (PPC_USE_SPRG)
64  int i;
65#endif
66  register uint32_t   r2 = 0;
67  register uint32_t   r13 = 0;
68
69  asm ("mr %0,13" : "=r" ((r13)) : "0" ((r13)));
70  _CPU_IRQ_info.Default_r13 = r13;
71
72  asm ("mr %0,2" : "=r" ((r2)) : "0" ((r2)));
73  _CPU_IRQ_info.Default_r2 = r2;
74
75  _CPU_IRQ_info.Nest_level = &_ISR_Nest_level;
76  _CPU_IRQ_info.Disable_level = &_Thread_Dispatch_disable_level;
77  /* fill in _CPU_IRQ_info.Vector_table later */
78  _CPU_IRQ_info.Switch_necessary = &_Context_Switch_necessary;
79  _CPU_IRQ_info.Signal = &_ISR_Signals_to_thread_executing;
80
81#if (PPC_USE_SPRG)
82  i = (int)&_CPU_IRQ_info;
83  asm volatile("mtspr 0x113, %0" : "=r" (i) : "0" (i)); /* SPRG 3 */
84#endif
85
86  /*
87   * Store Msr Value in the IRQ info structure.
88   */
89   _CPU_MSR_Value(_CPU_IRQ_info.msr_initial);
90
91#if (PPC_USE_SPRG)
92  i = _CPU_IRQ_info.msr_initial;
93  asm volatile("mtspr 0x112, %0" : "=r" (i) : "0" (i)); /* SPRG 2 */
94#endif
95
96  _CPU_Table = *cpu_table;
97}
98
99/*
100 *  _CPU_Initialize_vectors()
101 *
102 *  Support routine to initialize the RTEMS vector table after it is allocated.
103 *
104 *  PowerPC Specific Information:
105 *
106 *  Complete initialization since the table is now allocated.
107 */
108
109void _CPU_Initialize_vectors(void)
110{
111  int i;
112  proc_ptr handler = (proc_ptr)ppc_spurious;
113
114  _CPU_IRQ_info.Vector_table = _ISR_Vector_table;
115
116  if ( _CPU_Table.spurious_handler )
117    handler = (proc_ptr)_CPU_Table.spurious_handler;
118
119  for (i = 0; i < PPC_INTERRUPT_MAX;  i++)
120    _ISR_Vector_table[i] = handler;
121
122}
123
124/*PAGE
125 *
126 *  _CPU_ISR_Calculate_level
127 *
128 *  The PowerPC puts its interrupt enable status in the MSR register
129 *  which also contains things like endianness control.  To be more
130 *  awkward, the layout varies from processor to processor.  This
131 *  is why it was necessary to adopt a scheme which allowed the user
132 *  to specify specifically which interrupt sources were enabled.
133 */
134
135uint32_t   _CPU_ISR_Calculate_level(
136  uint32_t   new_level
137)
138{
139  register uint32_t   new_msr = 0;
140
141  /*
142   *  Set the critical interrupt enable bit
143   */
144
145#if (PPC_HAS_RFCI)
146  if ( !(new_level & PPC_INTERRUPT_LEVEL_CE) )
147    new_msr |= PPC_MSR_CE;
148#endif
149
150  if ( !(new_level & PPC_INTERRUPT_LEVEL_ME) )
151    new_msr |= PPC_MSR_ME;
152
153  if ( !(new_level & PPC_INTERRUPT_LEVEL_EE) )
154    new_msr |= PPC_MSR_EE;
155
156  return new_msr;
157}
158
159/*PAGE
160 *
161 *  _CPU_ISR_Set_level
162 *
163 *  This routine sets the requested level in the MSR.
164 */
165
166void _CPU_ISR_Set_level(
167  uint32_t   new_level
168)
169{
170  register uint32_t   tmp = 0;
171  register uint32_t   new_msr;
172
173  new_msr = _CPU_ISR_Calculate_level( new_level );
174
175  asm volatile (
176    "mfmsr %0; andc %0,%0,%1; and %2, %2, %1; or %0, %0, %2; mtmsr %0" :
177    "=&r" ((tmp)) :
178    "r" ((PPC_MSR_DISABLE_MASK)), "r" ((new_msr)), "0" ((tmp))
179  );
180}
181
182/*PAGE
183 *
184 *  _CPU_ISR_Get_level
185 *
186 *  This routine gets the current interrupt level from the MSR and
187 *  converts it to an RTEMS interrupt level.
188 */
189
190uint32_t   _CPU_ISR_Get_level( void )
191{
192  uint32_t   level = 0;
193  uint32_t   msr;
194
195  asm volatile("mfmsr %0" : "=r" ((msr)));
196
197  msr &= PPC_MSR_DISABLE_MASK;
198
199  /*
200   *  Set the critical interrupt enable bit
201   */
202
203#if (PPC_HAS_RFCI)
204  if ( !(msr & PPC_MSR_CE) )
205    level |= PPC_INTERRUPT_LEVEL_CE;
206#endif
207
208  if ( !(msr & PPC_MSR_ME) )
209    level |= PPC_INTERRUPT_LEVEL_ME;
210
211  if ( !(msr & PPC_MSR_EE) )
212    level |= PPC_INTERRUPT_LEVEL_EE;
213
214  return level;
215}
216
217/*PAGE
218 *
219 *  _CPU_Context_Initialize
220 */
221
222/* PPC_ABI_SVR4 or PPC_ABI_EABI */
223#define CPU_MINIMUM_STACK_FRAME_SIZE 8
224
225void _CPU_Context_Initialize(
226  Context_Control  *the_context,
227  uint32_t         *stack_base,
228  uint32_t          size,
229  uint32_t          new_level,
230  void             *entry_point,
231  boolean           is_fp
232)
233{
234  uint32_t   msr_value;
235  uint32_t   sp;
236
237  sp = (uint32_t)stack_base + size - CPU_MINIMUM_STACK_FRAME_SIZE;
238  *((uint32_t*)sp) = 0;
239  the_context->gpr1 = sp;
240
241  the_context->msr = _CPU_ISR_Calculate_level( new_level );
242
243  /*
244   *  The FP bit of the MSR should only be enabled if this is a floating
245   *  point task.  Unfortunately, the vfprintf_r routine in newlib
246   *  ends up pushing a floating point register regardless of whether or
247   *  not a floating point number is being printed.  Serious restructuring
248   *  of vfprintf.c will be required to avoid this behavior.  At this
249   *  time (7 July 1997), this restructuring is not being done.
250   */
251
252  /*if ( is_fp ) */
253    the_context->msr |= PPC_MSR_FP;
254
255  /*
256   *  Calculate the task's MSR value:
257   *
258   *     + Set the exception prefix bit to point to the exception table
259   *     + Force the RI bit
260   *     + Use the DR and IR bits
261   */
262  _CPU_MSR_Value( msr_value );
263  the_context->msr |= (msr_value & PPC_MSR_EP);
264  the_context->msr |= PPC_MSR_RI;
265  the_context->msr |= msr_value & (PPC_MSR_DR|PPC_MSR_IR);
266
267#if (PPC_ABI == PPC_ABI_SVR4)
268  { unsigned    r13 = 0;
269    asm volatile ("mr %0, 13" : "=r" ((r13)));
270
271    the_context->pc = (uint32_t)entry_point;
272    the_context->gpr13 = r13;
273  }
274#endif
275
276#if (PPC_ABI == PPC_ABI_EABI)
277  { uint32_t    r2 = 0;
278    unsigned    r13 = 0;
279    asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
280
281    the_context->pc = (uint32_t)entry_point;
282    the_context->gpr2 = r2;
283    the_context->gpr13 = r13;
284  }
285#endif
286}
287
288/*  _CPU_ISR_install_vector
289 *
290 *  This kernel routine installs the RTEMS handler for the
291 *  specified vector.
292 *
293 *  Input parameters:
294 *    vector      - interrupt vector number
295 *    old_handler - former ISR for this vector number
296 *    new_handler - replacement ISR for this vector number
297 *
298 *  Output parameters:  NONE
299 *
300 */
301
302void _CPU_ISR_install_vector(
303  uint32_t    vector,
304  proc_ptr    new_handler,
305  proc_ptr   *old_handler
306)
307{
308   proc_ptr   ignored;
309   *old_handler = _ISR_Vector_table[ vector ];
310
311   /*
312    *  If the interrupt vector table is a table of pointer to isr entry
313    *  points, then we need to install the appropriate RTEMS interrupt
314    *  handler for this vector number.
315    */
316
317   /*
318    * Install the wrapper so this ISR can be invoked properly.
319    */
320   if (_CPU_Table.exceptions_in_RAM)
321      _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
322
323   /*
324    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
325    *  be used by the _ISR_Handler so the user gets control.
326    */
327
328    _ISR_Vector_table[ vector ] = new_handler ? (ISR_Handler_entry)new_handler :
329       _CPU_Table.spurious_handler ?
330          (ISR_Handler_entry)_CPU_Table.spurious_handler :
331          (ISR_Handler_entry)ppc_spurious;
332}
333
334/*PAGE
335 *
336 *  _CPU_Install_interrupt_stack
337 */
338
339void _CPU_Install_interrupt_stack( void )
340{
341/* PPC_ABI_EABI */
342  _CPU_IRQ_info.Stack = _CPU_Interrupt_stack_high - 8;
343}
344
345/* Handle a spurious interrupt */
346static void ppc_spurious(int v, CPU_Interrupt_frame *i)
347{
348#if 0
349    printf("Spurious interrupt on vector %d from %08.8x\n",
350           v, i->pc);
351#endif
352#if defined(ppc403) || defined(ppc405)
353    if (v == PPC_IRQ_EXTERNAL)
354        {
355            register int r = 0;
356
357            asm volatile("mtdcr 0x42, %0" :
358                "=&r" ((r)) : "0" ((r))); /* EXIER */
359        }
360    else if (v == PPC_IRQ_PIT)
361        {
362            register int r = 0x08000000;
363
364            asm volatile("mtspr 0x3d8, %0" :
365                "=&r" ((r)) : "0" ((r))); /* TSR */
366        }
367    else if (v == PPC_IRQ_FIT)
368        {
369            register int r = 0x04000000;
370
371            asm volatile("mtspr 0x3d8, %0" :
372                "=&r" ((r)) : "0" ((r))); /* TSR */
373        }
374#endif
375    ++_CPU_spurious_count;
376    _CPU_last_spurious = v;
377}
378
379void _CPU_Fatal_error(uint32_t   _error)
380{
381  asm volatile ("mr 3, %0" : : "r" ((_error)));
382  asm volatile ("tweq 5,5");
383  asm volatile ("li 0,0; mtmsr 0");
384  while (1) ;
385}
386
387#define PPC_SYNCHRONOUS_TRAP_BIT_MASK    0x100
388#define PPC_ASYNCHRONOUS_TRAP( _trap ) (_trap)
389#define PPC_SYNCHRONOUS_TRAP ( _trap ) ((_trap)+PPC_SYNCHRONOUS_TRAP_BIT_MASK)
390#define PPC_REAL_TRAP_NUMBER ( _trap ) ((_trap)%PPC_SYNCHRONOUS_TRAP_BIT_MASK)
391
392const CPU_Trap_table_entry _CPU_Trap_slot_template = {
393
394  0x9421ff90,           /* stwu    r1, -(IP_END)(r1)            */
395
396  0x90010008,           /* stw   %r0, IP_0(%r1)                 */
397  0x38000000,           /* li    %r0, PPC_IRQ                   */
398  0x48000002            /* ba    PROC (_ISR_Handler)            */
399};
400
401#if defined(mpc860) || defined(mpc821)
402const CPU_Trap_table_entry _CPU_Trap_slot_template_m860 = {
403  0x7c0803ac,           /* mtlr  %r0                            */
404  0x81210028,           /* lwz   %r9, IP_9(%r1)                 */
405  0x38000000,           /* li    %r0, PPC_IRQ                   */
406  0x48000002            /* b     PROC (_ISR_Handler)            */
407};
408#endif /* mpc860 */
409
410uint32_t    ppc_exception_vector_addr(
411  uint32_t   vector
412);
413
414/*PAGE
415 *
416 *  _CPU_ISR_install_raw_handler
417 *
418 *  This routine installs the specified handler as a "raw" non-executive
419 *  supported trap handler (a.k.a. interrupt service routine).
420 *
421 *  Input Parameters:
422 *    vector      - trap table entry number plus synchronous
423 *                    vs. asynchronous information
424 *    new_handler - address of the handler to be installed
425 *    old_handler - pointer to an address of the handler previously installed
426 *
427 *  Output Parameters: NONE
428 *    *new_handler - address of the handler previously installed
429 *
430 *  NOTE:
431 *
432 *  This routine is based on the SPARC routine _CPU_ISR_install_raw_handler.
433 *  Install a software trap handler as an executive interrupt handler
434 *  (which is desirable since RTEMS takes care of window and register issues),
435 *  then the executive needs to know that the return address is to the trap
436 *  rather than the instruction following the trap.
437 *
438 */
439
440void _CPU_ISR_install_raw_handler(
441  uint32_t    vector,
442  proc_ptr    new_handler,
443  proc_ptr   *old_handler
444)
445{
446  uint32_t               real_vector;
447  CPU_Trap_table_entry  *slot;
448  uint32_t               u32_handler=0;
449
450  /*
451   *  Get the "real" trap number for this vector ignoring the synchronous
452   *  versus asynchronous indicator included with our vector numbers.
453   */
454
455  real_vector = vector;
456
457  /*
458   *  Get the current base address of the trap table and calculate a pointer
459   *  to the slot we are interested in.
460   */
461  slot = (CPU_Trap_table_entry  *)ppc_exception_vector_addr( real_vector );
462
463  /*
464   *  Get the address of the old_handler from the trap table.
465   *
466   *  NOTE: The old_handler returned will be bogus if it does not follow
467   *        the RTEMS model.
468   */
469
470#define HIGH_BITS_MASK   0xFFFFFC00
471#define HIGH_BITS_SHIFT  10
472#define LOW_BITS_MASK    0x000003FF
473
474  if (slot->stwu_r1 == _CPU_Trap_slot_template.stwu_r1) {
475    /*
476     * Set u32_handler = to target address
477     */
478    u32_handler = slot->b_Handler & 0x03fffffc;
479
480    /* IMD FIX: sign extend address fragment... */
481    if (u32_handler & 0x02000000) {
482      u32_handler  |= 0xfc000000;
483    }
484
485    *old_handler =  (proc_ptr) u32_handler;
486  } else
487/* There are two kinds of handlers for the MPC860. One is the 'standard'
488 *  one like above. The other is for the cascaded interrupts from the SIU
489 *  and CPM. Therefore we must check for the alternate one if the standard
490 *  one is not present
491 */
492#if defined(mpc860) || defined(mpc821)
493  if (slot->stwu_r1 == _CPU_Trap_slot_template_m860.stwu_r1) {
494    /*
495     * Set u32_handler = to target address
496     */
497    u32_handler = slot->b_Handler & 0x03fffffc;
498    *old_handler =  (proc_ptr) u32_handler;
499  } else
500#endif /* mpc860 */
501
502    *old_handler = 0;
503
504  /*
505   *  Copy the template to the slot and then fix it.
506   */
507#if defined(mpc860) || defined(mpc821)
508  if (vector >= PPC_IRQ_IRQ0)
509    *slot = _CPU_Trap_slot_template_m860;
510  else
511#endif /* mpc860 */
512  *slot = _CPU_Trap_slot_template;
513
514  u32_handler = (uint32_t) new_handler;
515
516  /*
517   * IMD FIX: insert address fragment only (bits 6..29)
518   *          therefore check for proper address range
519   *          and remove unwanted bits
520   */
521  if ((u32_handler & 0xfc000000) == 0xfc000000) {
522    u32_handler  &= ~0xfc000000;
523  }
524  else if ((u32_handler & 0xfc000000) != 0x00000000) {
525    _Internal_error_Occurred(INTERNAL_ERROR_CORE,
526                             TRUE,
527                             u32_handler);
528  }
529
530  slot->b_Handler |= u32_handler;
531
532  slot->li_r0_IRQ  |= vector;
533
534  _CPU_Data_Cache_Block_Flush( slot );
535}
536
537uint32_t    ppc_exception_vector_addr(
538  uint32_t   vector
539)
540{
541#if (!PPC_HAS_EVPR)
542  uint32_t   Msr;
543#endif
544  uint32_t   Top = 0;
545  uint32_t   Offset = 0x000;
546
547#if (PPC_HAS_EXCEPTION_PREFIX)
548  _CPU_MSR_Value ( Msr );
549  if ( ( Msr & PPC_MSR_EP) != 0 ) /* Vectors at FFFx_xxxx */
550    Top = 0xfff00000;
551#elif (PPC_HAS_EVPR)
552  asm volatile( "mfspr %0,0x3d6" : "=r" (Top)); /* EVPR */
553  Top = Top & 0xffff0000;
554#endif
555
556  switch ( vector ) {
557    case PPC_IRQ_SYSTEM_RESET:   /* on 40x aka PPC_IRQ_CRIT */
558      Offset = 0x00100;
559      break;
560    case PPC_IRQ_MCHECK:
561      Offset = 0x00200;
562      break;
563    case PPC_IRQ_PROTECT:
564      Offset = 0x00300;
565      break;
566    case PPC_IRQ_ISI:
567      Offset = 0x00400;
568      break;
569    case PPC_IRQ_EXTERNAL:
570      Offset = 0x00500;
571      break;
572    case PPC_IRQ_ALIGNMENT:
573      Offset = 0x00600;
574      break;
575    case PPC_IRQ_PROGRAM:
576      Offset = 0x00700;
577      break;
578    case PPC_IRQ_NOFP:
579      Offset = 0x00800;
580      break;
581    case PPC_IRQ_DECREMENTER:
582      Offset = 0x00900;
583      break;
584    case PPC_IRQ_RESERVED_A:
585      Offset = 0x00a00;
586      break;
587    case PPC_IRQ_RESERVED_B:
588      Offset = 0x00b00;
589      break;
590    case PPC_IRQ_SCALL:
591      Offset = 0x00c00;
592      break;
593    case PPC_IRQ_TRACE:
594      Offset = 0x00d00;
595      break;
596    case PPC_IRQ_FP_ASST:
597      Offset = 0x00e00;
598      break;
599
600#if defined(ppc403) || defined(ppc405)
601
602/*  PPC_IRQ_CRIT is the same vector as PPC_IRQ_RESET
603    case PPC_IRQ_CRIT:
604      Offset = 0x00100;
605      break;
606*/
607    case PPC_IRQ_PIT:
608      Offset = 0x01000;
609      break;
610    case PPC_IRQ_FIT:
611      Offset = 0x01010;
612      break;
613    case PPC_IRQ_WATCHDOG:
614      Offset = 0x01020;
615      break;
616    case PPC_IRQ_DEBUG:
617      Offset = 0x02000;
618      break;
619
620#elif defined(ppc601)
621    case PPC_IRQ_TRACE:
622      Offset = 0x02000;
623      break;
624
625#elif defined(ppc603)
626    case PPC_IRQ_TRANS_MISS:
627      Offset = 0x1000;
628      break;
629    case PPC_IRQ_DATA_LOAD:
630      Offset = 0x1100;
631      break;
632    case PPC_IRQ_DATA_STORE:
633      Offset = 0x1200;
634      break;
635    case PPC_IRQ_ADDR_BRK:
636      Offset = 0x1300;
637      break;
638    case PPC_IRQ_SYS_MGT:
639      Offset = 0x1400;
640      break;
641
642#elif defined(ppc603e)
643    case PPC_TLB_INST_MISS:
644      Offset = 0x1000;
645      break;
646    case PPC_TLB_LOAD_MISS:
647      Offset = 0x1100;
648      break;
649    case PPC_TLB_STORE_MISS:
650      Offset = 0x1200;
651      break;
652    case PPC_IRQ_ADDRBRK:
653      Offset = 0x1300;
654      break;
655    case PPC_IRQ_SYS_MGT:
656      Offset = 0x1400;
657      break;
658
659#elif defined(mpc604)
660    case PPC_IRQ_ADDR_BRK:
661      Offset = 0x1300;
662      break;
663    case PPC_IRQ_SYS_MGT:
664      Offset = 0x1400;
665      break;
666
667#elif defined(mpc860) || defined(mpc821)
668    case PPC_IRQ_EMULATE:
669      Offset = 0x1000;
670      break;
671    case PPC_IRQ_INST_MISS:
672      Offset = 0x1100;
673      break;
674    case PPC_IRQ_DATA_MISS:
675      Offset = 0x1200;
676      break;
677    case PPC_IRQ_INST_ERR:
678      Offset = 0x1300;
679      break;
680    case PPC_IRQ_DATA_ERR:
681      Offset = 0x1400;
682      break;
683    case PPC_IRQ_DATA_BPNT:
684      Offset = 0x1c00;
685      break;
686    case PPC_IRQ_INST_BPNT:
687      Offset = 0x1d00;
688      break;
689    case PPC_IRQ_IO_BPNT:
690      Offset = 0x1e00;
691      break;
692    case PPC_IRQ_DEV_PORT:
693      Offset = 0x1f00;
694      break;
695    case PPC_IRQ_IRQ0:
696      Offset = 0x2000;
697      break;
698    case PPC_IRQ_LVL0:
699      Offset = 0x2040;
700      break;
701    case PPC_IRQ_IRQ1:
702      Offset = 0x2080;
703      break;
704    case PPC_IRQ_LVL1:
705      Offset = 0x20c0;
706      break;
707    case PPC_IRQ_IRQ2:
708      Offset = 0x2100;
709      break;
710    case PPC_IRQ_LVL2:
711      Offset = 0x2140;
712      break;
713    case PPC_IRQ_IRQ3:
714      Offset = 0x2180;
715      break;
716    case PPC_IRQ_LVL3:
717      Offset = 0x21c0;
718      break;
719    case PPC_IRQ_IRQ4:
720      Offset = 0x2200;
721      break;
722    case PPC_IRQ_LVL4:
723      Offset = 0x2240;
724      break;
725    case PPC_IRQ_IRQ5:
726      Offset = 0x2280;
727      break;
728    case PPC_IRQ_LVL5:
729      Offset = 0x22c0;
730      break;
731    case PPC_IRQ_IRQ6:
732      Offset = 0x2300;
733      break;
734    case PPC_IRQ_LVL6:
735      Offset = 0x2340;
736      break;
737    case PPC_IRQ_IRQ7:
738      Offset = 0x2380;
739      break;
740    case PPC_IRQ_LVL7:
741      Offset = 0x23c0;
742      break;
743    case PPC_IRQ_CPM_ERROR:
744      Offset = 0x2400;
745      break;
746    case PPC_IRQ_CPM_PC4:
747      Offset = 0x2410;
748      break;
749    case PPC_IRQ_CPM_PC5:
750      Offset = 0x2420;
751      break;
752    case PPC_IRQ_CPM_SMC2:
753      Offset = 0x2430;
754      break;
755    case PPC_IRQ_CPM_SMC1:
756      Offset = 0x2440;
757      break;
758    case PPC_IRQ_CPM_SPI:
759      Offset = 0x2450;
760      break;
761    case PPC_IRQ_CPM_PC6:
762      Offset = 0x2460;
763      break;
764    case PPC_IRQ_CPM_TIMER4:
765      Offset = 0x2470;
766      break;
767    case PPC_IRQ_CPM_RESERVED_8:
768      Offset = 0x2480;
769      break;
770    case PPC_IRQ_CPM_PC7:
771      Offset = 0x2490;
772      break;
773    case PPC_IRQ_CPM_PC8:
774      Offset = 0x24a0;
775      break;
776    case PPC_IRQ_CPM_PC9:
777      Offset = 0x24b0;
778      break;
779    case PPC_IRQ_CPM_TIMER3:
780      Offset = 0x24c0;
781      break;
782    case PPC_IRQ_CPM_RESERVED_D:
783      Offset = 0x24d0;
784      break;
785    case PPC_IRQ_CPM_PC10:
786      Offset = 0x24e0;
787      break;
788    case PPC_IRQ_CPM_PC11:
789      Offset = 0x24f0;
790      break;
791    case PPC_IRQ_CPM_I2C:
792      Offset = 0x2500;
793      break;
794    case PPC_IRQ_CPM_RISC_TIMER:
795      Offset = 0x2510;
796      break;
797    case PPC_IRQ_CPM_TIMER2:
798      Offset = 0x2520;
799      break;
800    case PPC_IRQ_CPM_RESERVED_13:
801      Offset = 0x2530;
802      break;
803    case PPC_IRQ_CPM_IDMA2:
804      Offset = 0x2540;
805      break;
806    case PPC_IRQ_CPM_IDMA1:
807      Offset = 0x2550;
808      break;
809    case PPC_IRQ_CPM_SDMA_ERROR:
810      Offset = 0x2560;
811      break;
812    case PPC_IRQ_CPM_PC12:
813      Offset = 0x2570;
814      break;
815    case PPC_IRQ_CPM_PC13:
816      Offset = 0x2580;
817      break;
818    case PPC_IRQ_CPM_TIMER1:
819      Offset = 0x2590;
820      break;
821    case PPC_IRQ_CPM_PC14:
822      Offset = 0x25a0;
823      break;
824    case PPC_IRQ_CPM_SCC4:
825      Offset = 0x25b0;
826      break;
827    case PPC_IRQ_CPM_SCC3:
828      Offset = 0x25c0;
829      break;
830    case PPC_IRQ_CPM_SCC2:
831      Offset = 0x25d0;
832      break;
833    case PPC_IRQ_CPM_SCC1:
834      Offset = 0x25e0;
835      break;
836    case PPC_IRQ_CPM_PC15:
837      Offset = 0x25f0;
838      break;
839#endif
840
841  }
842  Top += Offset;
843  return Top;
844}
845
846/*PAGE
847 *
848 *  This is the PowerPC specific implementation of the routine which
849 *  returns TRUE if an interrupt is in progress.
850 *
851 *  NOTE: This is the same as the generic version. But since the
852 *        PowerPC is still supporting old and new exception processing
853 *        models and the new exception processing model has a hardware
854 *        way of doing this, we have to provide this capability here
855 *        for symmetry.
856 */
857
858boolean _ISR_Is_in_progress( void )
859{
860  return (_ISR_Nest_level != 0);
861}
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