[acc25ee] | 1 | /* |
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| 2 | * PowerPC CPU Dependent Source |
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| 3 | * |
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| 4 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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| 5 | * |
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| 6 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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| 7 | * |
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| 8 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 9 | * without any express or implied warranty: |
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| 10 | * permission to use, copy, modify, and distribute this file |
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| 11 | * for any purpose is hereby granted without fee, provided that |
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| 12 | * the above copyright notice and this notice appears in all |
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| 13 | * copies, and that the name of i-cubed limited not be used in |
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| 14 | * advertising or publicity pertaining to distribution of the |
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| 15 | * software without specific, written prior permission. |
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| 16 | * i-cubed limited makes no representations about the suitability |
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| 17 | * of this software for any purpose. |
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| 18 | * |
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| 19 | * Derived from c/src/exec/cpu/no_cpu/cpu.c: |
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| 20 | * |
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| 21 | * COPYRIGHT (c) 1989-1997. |
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| 22 | * On-Line Applications Research Corporation (OAR). |
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| 23 | * Copyright assigned to U.S. Government, 1994. |
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| 24 | * |
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| 25 | * The license and distribution terms for this file may be found in |
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| 26 | * the file LICENSE in this distribution or at |
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| 27 | * http://www.OARcorp.com/rtems/license.html. |
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| 28 | * |
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| 29 | * $Id$ |
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| 30 | */ |
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| 31 | |
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| 32 | #include <rtems/system.h> |
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| 33 | #include <rtems/score/isr.h> |
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| 34 | #include <rtems/score/context.h> |
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| 35 | #include <rtems/score/thread.h> |
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| 36 | #include <rtems/score/interr.h> |
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| 37 | |
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| 38 | /* |
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| 39 | * These are for testing purposes. |
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| 40 | */ |
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| 41 | |
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| 42 | /* _CPU_Initialize |
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| 43 | * |
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| 44 | * This routine performs processor dependent initialization. |
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| 45 | * |
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| 46 | * INPUT PARAMETERS: |
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| 47 | * cpu_table - CPU table to initialize |
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| 48 | * thread_dispatch - address of disptaching routine |
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| 49 | */ |
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| 50 | |
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| 51 | static void ppc_spurious(int, CPU_Interrupt_frame *); |
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| 52 | |
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| 53 | void _CPU_Initialize( |
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| 54 | rtems_cpu_table *cpu_table, |
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| 55 | void (*thread_dispatch) /* ignored on this CPU */ |
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| 56 | ) |
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| 57 | { |
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| 58 | proc_ptr handler = (proc_ptr)ppc_spurious; |
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| 59 | int i; |
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| 60 | #if (PPC_ABI != PPC_ABI_POWEROPEN) |
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| 61 | register unsigned32 r2 = 0; |
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| 62 | #if (PPC_ABI != PPC_ABI_GCC27) |
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| 63 | register unsigned32 r13 = 0; |
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| 64 | |
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| 65 | asm ("mr %0,13" : "=r" ((r13)) : "0" ((r13))); |
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| 66 | _CPU_IRQ_info.Default_r13 = r13; |
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| 67 | #endif |
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| 68 | |
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| 69 | asm ("mr %0,2" : "=r" ((r2)) : "0" ((r2))); |
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| 70 | _CPU_IRQ_info.Default_r2 = r2; |
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| 71 | #endif |
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| 72 | |
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| 73 | _CPU_IRQ_info.Nest_level = &_ISR_Nest_level; |
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| 74 | _CPU_IRQ_info.Disable_level = &_Thread_Dispatch_disable_level; |
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| 75 | _CPU_IRQ_info.Vector_table = _ISR_Vector_table; |
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| 76 | #if (PPC_ABI == PPC_ABI_POWEROPEN) |
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| 77 | _CPU_IRQ_info.Dispatch_r2 = ((unsigned32 *)_Thread_Dispatch)[1]; |
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| 78 | #endif |
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| 79 | _CPU_IRQ_info.Switch_necessary = &_Context_Switch_necessary; |
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| 80 | _CPU_IRQ_info.Signal = &_ISR_Signals_to_thread_executing; |
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| 81 | |
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| 82 | #if (PPC_USE_SPRG) |
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| 83 | i = (int)&_CPU_IRQ_info; |
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| 84 | asm volatile("mtspr 0x113, %0" : "=r" (i) : "0" (i)); /* SPRG 3 */ |
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| 85 | #endif |
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| 86 | |
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| 87 | /* |
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| 88 | * Store Msr Value in the IRQ info structure. |
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| 89 | */ |
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| 90 | _CPU_MSR_Value(_CPU_IRQ_info.msr_initial); |
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| 91 | |
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| 92 | #if (PPC_USE_SPRG) |
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| 93 | i = _CPU_IRQ_info.msr_initial; |
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| 94 | asm volatile("mtspr 0x112, %0" : "=r" (i) : "0" (i)); /* SPRG 2 */ |
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| 95 | #endif |
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| 96 | |
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| 97 | if ( cpu_table->spurious_handler ) |
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| 98 | handler = (proc_ptr)cpu_table->spurious_handler; |
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| 99 | |
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| 100 | for (i = 0; i < PPC_INTERRUPT_MAX; i++) |
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| 101 | _ISR_Vector_table[i] = handler; |
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| 102 | |
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| 103 | _CPU_Table = *cpu_table; |
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| 104 | } |
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| 105 | |
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| 106 | /*PAGE |
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| 107 | * |
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| 108 | * _CPU_ISR_Calculate_level |
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| 109 | * |
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| 110 | * The PowerPC puts its interrupt enable status in the MSR register |
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| 111 | * which also contains things like endianness control. To be more |
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| 112 | * awkward, the layout varies from processor to processor. This |
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| 113 | * is why it was necessary to adopt a scheme which allowed the user |
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| 114 | * to specify specifically which interrupt sources were enabled. |
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| 115 | */ |
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| 116 | |
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| 117 | unsigned32 _CPU_ISR_Calculate_level( |
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| 118 | unsigned32 new_level |
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| 119 | ) |
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| 120 | { |
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| 121 | register unsigned32 new_msr = 0; |
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| 122 | |
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| 123 | /* |
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| 124 | * Set the critical interrupt enable bit |
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| 125 | */ |
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| 126 | |
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| 127 | #if (PPC_HAS_RFCI) |
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| 128 | if ( !(new_level & PPC_INTERRUPT_LEVEL_CE) ) |
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| 129 | new_msr |= PPC_MSR_CE; |
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| 130 | #endif |
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| 131 | |
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| 132 | if ( !(new_level & PPC_INTERRUPT_LEVEL_ME) ) |
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| 133 | new_msr |= PPC_MSR_ME; |
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| 134 | |
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| 135 | if ( !(new_level & PPC_INTERRUPT_LEVEL_EE) ) |
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| 136 | new_msr |= PPC_MSR_EE; |
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| 137 | |
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| 138 | return new_msr; |
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| 139 | } |
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| 140 | |
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| 141 | /*PAGE |
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| 142 | * |
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| 143 | * _CPU_ISR_Set_level |
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| 144 | * |
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| 145 | * This routine sets the requested level in the MSR. |
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| 146 | */ |
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| 147 | |
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| 148 | void _CPU_ISR_Set_level( |
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| 149 | unsigned32 new_level |
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| 150 | ) |
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| 151 | { |
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| 152 | register unsigned32 tmp = 0; |
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| 153 | register unsigned32 new_msr; |
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| 154 | |
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| 155 | new_msr = _CPU_ISR_Calculate_level( new_level ); |
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| 156 | |
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| 157 | asm volatile ( |
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| 158 | "mfmsr %0; andc %0,%0,%1; and %2, %2, %1; or %0, %0, %2; mtmsr %0" : |
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| 159 | "=&r" ((tmp)) : |
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| 160 | "r" ((PPC_MSR_DISABLE_MASK)), "r" ((new_msr)), "0" ((tmp)) |
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| 161 | ); |
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| 162 | } |
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| 163 | |
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| 164 | /*PAGE |
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| 165 | * |
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| 166 | * _CPU_ISR_Get_level |
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| 167 | * |
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| 168 | * This routine gets the current interrupt level from the MSR and |
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| 169 | * converts it to an RTEMS interrupt level. |
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| 170 | */ |
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| 171 | |
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| 172 | unsigned32 _CPU_ISR_Get_level( void ) |
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| 173 | { |
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| 174 | unsigned32 level = 0; |
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| 175 | unsigned32 msr; |
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| 176 | |
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| 177 | asm volatile("mfmsr %0" : "=r" ((msr))); |
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| 178 | |
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| 179 | msr &= PPC_MSR_DISABLE_MASK; |
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| 180 | |
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| 181 | /* |
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| 182 | * Set the critical interrupt enable bit |
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| 183 | */ |
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| 184 | |
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| 185 | #if (PPC_HAS_RFCI) |
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| 186 | if ( !(msr & PPC_MSR_CE) ) |
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| 187 | level |= PPC_INTERRUPT_LEVEL_CE; |
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| 188 | #endif |
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| 189 | |
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| 190 | if ( !(msr & PPC_MSR_ME) ) |
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| 191 | level |= PPC_INTERRUPT_LEVEL_ME; |
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| 192 | |
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| 193 | if ( !(msr & PPC_MSR_EE) ) |
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| 194 | level |= PPC_INTERRUPT_LEVEL_EE; |
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| 195 | |
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| 196 | return level; |
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| 197 | } |
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| 198 | |
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| 199 | /*PAGE |
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| 200 | * |
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| 201 | * _CPU_Context_Initialize |
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| 202 | */ |
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| 203 | |
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| 204 | #if (PPC_ABI == PPC_ABI_POWEROPEN) |
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| 205 | #define CPU_MINIMUM_STACK_FRAME_SIZE 56 |
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| 206 | #else /* PPC_ABI_SVR4 or PPC_ABI_EABI */ |
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| 207 | #define CPU_MINIMUM_STACK_FRAME_SIZE 8 |
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| 208 | #endif |
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| 209 | |
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| 210 | void _CPU_Context_Initialize( |
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| 211 | Context_Control *the_context, |
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| 212 | unsigned32 *stack_base, |
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| 213 | unsigned32 size, |
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| 214 | unsigned32 new_level, |
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| 215 | void *entry_point, |
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| 216 | boolean is_fp |
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| 217 | ) |
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| 218 | { |
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| 219 | unsigned32 msr_value; |
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| 220 | unsigned32 sp; |
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| 221 | |
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| 222 | sp = (unsigned32)stack_base + size - CPU_MINIMUM_STACK_FRAME_SIZE; |
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| 223 | *((unsigned32 *)sp) = 0; |
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| 224 | the_context->gpr1 = sp; |
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| 225 | |
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| 226 | the_context->msr = _CPU_ISR_Calculate_level( new_level ); |
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| 227 | |
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| 228 | /* |
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| 229 | * The FP bit of the MSR should only be enabled if this is a floating |
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| 230 | * point task. Unfortunately, the vfprintf_r routine in newlib |
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| 231 | * ends up pushing a floating point register regardless of whether or |
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| 232 | * not a floating point number is being printed. Serious restructuring |
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| 233 | * of vfprintf.c will be required to avoid this behavior. At this |
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| 234 | * time (7 July 1997), this restructuring is not being done. |
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| 235 | */ |
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| 236 | |
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| 237 | /*if ( is_fp ) */ |
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| 238 | the_context->msr |= PPC_MSR_FP; |
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| 239 | |
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| 240 | /* |
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| 241 | * Calculate the task's MSR value: |
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| 242 | * |
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| 243 | * + Set the exception prefix bit to point to the exception table |
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| 244 | * + Force the RI bit |
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| 245 | * + Use the DR and IR bits |
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| 246 | */ |
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| 247 | _CPU_MSR_Value( msr_value ); |
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| 248 | the_context->msr |= (msr_value & PPC_MSR_EP); |
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| 249 | the_context->msr |= PPC_MSR_RI; |
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| 250 | the_context->msr |= msr_value & (PPC_MSR_DR|PPC_MSR_IR); |
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| 251 | |
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| 252 | #if (PPC_ABI == PPC_ABI_POWEROPEN) |
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| 253 | { unsigned32 *desc = (unsigned32 *)entry_point; |
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| 254 | |
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| 255 | the_context->pc = desc[0]; |
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| 256 | the_context->gpr2 = desc[1]; |
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| 257 | } |
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| 258 | #endif |
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| 259 | |
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| 260 | #if (PPC_ABI == PPC_ABI_SVR4) |
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| 261 | { unsigned r13 = 0; |
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| 262 | asm volatile ("mr %0, 13" : "=r" ((r13))); |
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| 263 | |
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| 264 | the_context->pc = (unsigned32)entry_point; |
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| 265 | the_context->gpr13 = r13; |
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| 266 | } |
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| 267 | #endif |
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| 268 | |
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| 269 | #if (PPC_ABI == PPC_ABI_EABI) |
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| 270 | { unsigned32 r2 = 0; |
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| 271 | unsigned r13 = 0; |
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| 272 | asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13))); |
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| 273 | |
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| 274 | the_context->pc = (unsigned32)entry_point; |
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| 275 | the_context->gpr2 = r2; |
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| 276 | the_context->gpr13 = r13; |
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| 277 | } |
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| 278 | #endif |
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| 279 | } |
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| 280 | |
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| 281 | |
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| 282 | /* _CPU_ISR_install_vector |
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| 283 | * |
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| 284 | * This kernel routine installs the RTEMS handler for the |
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| 285 | * specified vector. |
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| 286 | * |
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| 287 | * Input parameters: |
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| 288 | * vector - interrupt vector number |
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| 289 | * old_handler - former ISR for this vector number |
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| 290 | * new_handler - replacement ISR for this vector number |
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| 291 | * |
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| 292 | * Output parameters: NONE |
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| 293 | * |
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| 294 | */ |
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| 295 | |
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| 296 | void _CPU_ISR_install_vector( |
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| 297 | unsigned32 vector, |
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| 298 | proc_ptr new_handler, |
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| 299 | proc_ptr *old_handler |
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| 300 | ) |
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| 301 | { |
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| 302 | proc_ptr ignored; |
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| 303 | *old_handler = _ISR_Vector_table[ vector ]; |
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| 304 | |
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| 305 | /* |
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| 306 | * If the interrupt vector table is a table of pointer to isr entry |
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| 307 | * points, then we need to install the appropriate RTEMS interrupt |
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| 308 | * handler for this vector number. |
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| 309 | */ |
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| 310 | |
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| 311 | /* |
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| 312 | * Install the wrapper so this ISR can be invoked properly. |
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| 313 | */ |
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| 314 | if (_CPU_Table.exceptions_in_RAM) |
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| 315 | _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); |
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| 316 | |
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| 317 | /* |
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| 318 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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| 319 | * be used by the _ISR_Handler so the user gets control. |
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| 320 | */ |
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| 321 | |
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| 322 | _ISR_Vector_table[ vector ] = new_handler ? (ISR_Handler_entry)new_handler : |
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| 323 | _CPU_Table.spurious_handler ? |
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| 324 | (ISR_Handler_entry)_CPU_Table.spurious_handler : |
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| 325 | (ISR_Handler_entry)ppc_spurious; |
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| 326 | } |
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| 327 | |
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| 328 | /*PAGE |
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| 329 | * |
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| 330 | * _CPU_Install_interrupt_stack |
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| 331 | */ |
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| 332 | |
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| 333 | void _CPU_Install_interrupt_stack( void ) |
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| 334 | { |
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| 335 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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| 336 | _CPU_IRQ_info.Stack = _CPU_Interrupt_stack_high - 56; |
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| 337 | #else |
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| 338 | _CPU_IRQ_info.Stack = _CPU_Interrupt_stack_high - 8; |
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| 339 | #endif |
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| 340 | } |
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| 341 | |
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| 342 | /* Handle a spurious interrupt */ |
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| 343 | static void ppc_spurious(int v, CPU_Interrupt_frame *i) |
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| 344 | { |
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| 345 | #if 0 |
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| 346 | printf("Spurious interrupt on vector %d from %08.8x\n", |
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| 347 | v, i->pc); |
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| 348 | #endif |
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| 349 | #ifdef ppc403 |
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| 350 | if (v == PPC_IRQ_EXTERNAL) |
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| 351 | { |
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| 352 | register int r = 0; |
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| 353 | |
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| 354 | asm volatile("mtdcr 0x42, %0" : |
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| 355 | "=&r" ((r)) : "0" ((r))); /* EXIER */ |
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| 356 | } |
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| 357 | else if (v == PPC_IRQ_PIT) |
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| 358 | { |
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| 359 | register int r = 0x08000000; |
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| 360 | |
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| 361 | asm volatile("mtspr 0x3d8, %0" : |
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| 362 | "=&r" ((r)) : "0" ((r))); /* TSR */ |
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| 363 | } |
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| 364 | else if (v == PPC_IRQ_FIT) |
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| 365 | { |
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| 366 | register int r = 0x04000000; |
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| 367 | |
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| 368 | asm volatile("mtspr 0x3d8, %0" : |
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| 369 | "=&r" ((r)) : "0" ((r))); /* TSR */ |
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| 370 | } |
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| 371 | #endif |
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| 372 | } |
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| 373 | |
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| 374 | void _CPU_Fatal_error(unsigned32 _error) |
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| 375 | { |
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| 376 | asm volatile ("mr 3, %0" : : "r" ((_error))); |
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| 377 | asm volatile ("tweq 5,5"); |
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| 378 | asm volatile ("li 0,0; mtmsr 0"); |
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| 379 | while (1) ; |
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| 380 | } |
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| 381 | |
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| 382 | #define PPC_SYNCHRONOUS_TRAP_BIT_MASK 0x100 |
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| 383 | #define PPC_ASYNCHRONOUS_TRAP( _trap ) (_trap) |
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| 384 | #define PPC_SYNCHRONOUS_TRAP ( _trap ) ((_trap)+PPC_SYNCHRONOUS_TRAP_BIT_MASK) |
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| 385 | #define PPC_REAL_TRAP_NUMBER ( _trap ) ((_trap)%PPC_SYNCHRONOUS_TRAP_BIT_MASK) |
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| 386 | |
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| 387 | |
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| 388 | const CPU_Trap_table_entry _CPU_Trap_slot_template = { |
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| 389 | |
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| 390 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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| 391 | #error " Vector install not tested." |
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| 392 | #if (PPC_HAS_FPU) |
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| 393 | #error " Vector install not tested." |
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| 394 | 0x9421feb0, /* stwu r1, -(20*4 + 18*8 + IP_END)(r1) */ |
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| 395 | #else |
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| 396 | #error " Vector install not tested." |
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| 397 | 0x9421ff40, /* stwu r1, -(20*4 + IP_END)(r1) */ |
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| 398 | #endif |
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| 399 | #else |
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| 400 | 0x9421ff90, /* stwu r1, -(IP_END)(r1) */ |
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| 401 | #endif |
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| 402 | |
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| 403 | 0x90010008, /* stw %r0, IP_0(%r1) */ |
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| 404 | 0x38000000, /* li %r0, PPC_IRQ */ |
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| 405 | 0x48000002 /* ba PROC (_ISR_Handler) */ |
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| 406 | }; |
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| 407 | |
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| 408 | #if defined(mpc860) || defined(mpc821) |
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| 409 | const CPU_Trap_table_entry _CPU_Trap_slot_template_m860 = { |
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| 410 | 0x7c0803ac, /* mtlr %r0 */ |
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| 411 | 0x81210028, /* lwz %r9, IP_9(%r1) */ |
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| 412 | 0x38000000, /* li %r0, PPC_IRQ */ |
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| 413 | 0x48000002 /* b PROC (_ISR_Handler) */ |
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| 414 | }; |
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| 415 | #endif /* mpc860 */ |
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| 416 | |
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| 417 | unsigned32 ppc_exception_vector_addr( |
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| 418 | unsigned32 vector |
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| 419 | ); |
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| 420 | |
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| 421 | |
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| 422 | /*PAGE |
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| 423 | * |
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| 424 | * _CPU_ISR_install_raw_handler |
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| 425 | * |
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| 426 | * This routine installs the specified handler as a "raw" non-executive |
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| 427 | * supported trap handler (a.k.a. interrupt service routine). |
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| 428 | * |
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| 429 | * Input Parameters: |
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| 430 | * vector - trap table entry number plus synchronous |
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| 431 | * vs. asynchronous information |
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| 432 | * new_handler - address of the handler to be installed |
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| 433 | * old_handler - pointer to an address of the handler previously installed |
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| 434 | * |
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| 435 | * Output Parameters: NONE |
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| 436 | * *new_handler - address of the handler previously installed |
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| 437 | * |
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| 438 | * NOTE: |
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| 439 | * |
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| 440 | * This routine is based on the SPARC routine _CPU_ISR_install_raw_handler. |
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| 441 | * Install a software trap handler as an executive interrupt handler |
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| 442 | * (which is desirable since RTEMS takes care of window and register issues), |
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| 443 | * then the executive needs to know that the return address is to the trap |
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| 444 | * rather than the instruction following the trap. |
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| 445 | * |
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| 446 | */ |
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| 447 | |
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| 448 | void _CPU_ISR_install_raw_handler( |
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| 449 | unsigned32 vector, |
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| 450 | proc_ptr new_handler, |
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| 451 | proc_ptr *old_handler |
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| 452 | ) |
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| 453 | { |
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| 454 | unsigned32 real_vector; |
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| 455 | CPU_Trap_table_entry *slot; |
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| 456 | unsigned32 u32_handler=0; |
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| 457 | |
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| 458 | /* |
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| 459 | * Get the "real" trap number for this vector ignoring the synchronous |
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| 460 | * versus asynchronous indicator included with our vector numbers. |
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| 461 | */ |
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| 462 | |
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| 463 | real_vector = vector; |
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| 464 | |
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| 465 | /* |
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| 466 | * Get the current base address of the trap table and calculate a pointer |
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| 467 | * to the slot we are interested in. |
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| 468 | */ |
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| 469 | slot = (CPU_Trap_table_entry *)ppc_exception_vector_addr( real_vector ); |
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| 470 | |
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| 471 | /* |
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| 472 | * Get the address of the old_handler from the trap table. |
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| 473 | * |
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| 474 | * NOTE: The old_handler returned will be bogus if it does not follow |
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| 475 | * the RTEMS model. |
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| 476 | */ |
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| 477 | |
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| 478 | #define HIGH_BITS_MASK 0xFFFFFC00 |
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| 479 | #define HIGH_BITS_SHIFT 10 |
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| 480 | #define LOW_BITS_MASK 0x000003FF |
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| 481 | |
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| 482 | if (slot->stwu_r1 == _CPU_Trap_slot_template.stwu_r1) { |
---|
| 483 | /* |
---|
| 484 | * Set u32_handler = to target address |
---|
| 485 | */ |
---|
| 486 | u32_handler = slot->b_Handler & 0x03fffffc; |
---|
| 487 | |
---|
| 488 | /* IMD FIX: sign extend address fragment... */ |
---|
| 489 | if (u32_handler & 0x02000000) { |
---|
| 490 | u32_handler |= 0xfc000000; |
---|
| 491 | } |
---|
| 492 | |
---|
| 493 | *old_handler = (proc_ptr) u32_handler; |
---|
| 494 | } else |
---|
| 495 | /* There are two kinds of handlers for the MPC860. One is the 'standard' |
---|
| 496 | * one like above. The other is for the cascaded interrupts from the SIU |
---|
| 497 | * and CPM. Therefore we must check for the alternate one if the standard |
---|
| 498 | * one is not present |
---|
| 499 | */ |
---|
| 500 | #if defined(mpc860) || defined(mpc821) |
---|
| 501 | if (slot->stwu_r1 == _CPU_Trap_slot_template_m860.stwu_r1) { |
---|
| 502 | /* |
---|
| 503 | * Set u32_handler = to target address |
---|
| 504 | */ |
---|
| 505 | u32_handler = slot->b_Handler & 0x03fffffc; |
---|
| 506 | *old_handler = (proc_ptr) u32_handler; |
---|
| 507 | } else |
---|
| 508 | #endif /* mpc860 */ |
---|
| 509 | |
---|
| 510 | *old_handler = 0; |
---|
| 511 | |
---|
| 512 | /* |
---|
| 513 | * Copy the template to the slot and then fix it. |
---|
| 514 | */ |
---|
| 515 | #if defined(mpc860) || defined(mpc821) |
---|
| 516 | if (vector >= PPC_IRQ_IRQ0) |
---|
| 517 | *slot = _CPU_Trap_slot_template_m860; |
---|
| 518 | else |
---|
| 519 | #endif /* mpc860 */ |
---|
| 520 | *slot = _CPU_Trap_slot_template; |
---|
| 521 | |
---|
| 522 | u32_handler = (unsigned32) new_handler; |
---|
| 523 | |
---|
| 524 | /* |
---|
| 525 | * IMD FIX: insert address fragment only (bits 6..29) |
---|
| 526 | * therefore check for proper address range |
---|
| 527 | * and remove unwanted bits |
---|
| 528 | */ |
---|
| 529 | if ((u32_handler & 0xfc000000) == 0xfc000000) { |
---|
| 530 | u32_handler &= ~0xfc000000; |
---|
| 531 | } |
---|
| 532 | else if ((u32_handler & 0xfc000000) != 0x00000000) { |
---|
| 533 | _Internal_error_Occurred(INTERNAL_ERROR_CORE, |
---|
| 534 | TRUE, |
---|
| 535 | u32_handler); |
---|
| 536 | } |
---|
| 537 | |
---|
| 538 | slot->b_Handler |= u32_handler; |
---|
| 539 | |
---|
| 540 | slot->li_r0_IRQ |= vector; |
---|
| 541 | |
---|
| 542 | _CPU_Data_Cache_Block_Flush( slot ); |
---|
| 543 | } |
---|
| 544 | |
---|
| 545 | unsigned32 ppc_exception_vector_addr( |
---|
| 546 | unsigned32 vector |
---|
| 547 | ) |
---|
| 548 | { |
---|
| 549 | #if (!PPC_HAS_EVPR) |
---|
| 550 | unsigned32 Msr; |
---|
| 551 | #endif |
---|
| 552 | unsigned32 Top = 0; |
---|
| 553 | unsigned32 Offset = 0x000; |
---|
| 554 | |
---|
| 555 | #if (PPC_HAS_EXCEPTION_PREFIX) |
---|
| 556 | _CPU_MSR_Value ( Msr ); |
---|
| 557 | if ( ( Msr & PPC_MSR_EP) != 0 ) /* Vectors at FFFx_xxxx */ |
---|
| 558 | Top = 0xfff00000; |
---|
| 559 | #elif (PPC_HAS_EVPR) |
---|
| 560 | asm volatile( "mfspr %0,0x3d6" : "=r" (Top)); /* EVPR */ |
---|
| 561 | Top = Top & 0xffff0000; |
---|
| 562 | #endif |
---|
| 563 | |
---|
| 564 | switch ( vector ) { |
---|
| 565 | case PPC_IRQ_SYSTEM_RESET: /* on 40x aka PPC_IRQ_CRIT */ |
---|
| 566 | Offset = 0x00100; |
---|
| 567 | break; |
---|
| 568 | case PPC_IRQ_MCHECK: |
---|
| 569 | Offset = 0x00200; |
---|
| 570 | break; |
---|
| 571 | case PPC_IRQ_PROTECT: |
---|
| 572 | Offset = 0x00300; |
---|
| 573 | break; |
---|
| 574 | case PPC_IRQ_ISI: |
---|
| 575 | Offset = 0x00400; |
---|
| 576 | break; |
---|
| 577 | case PPC_IRQ_EXTERNAL: |
---|
| 578 | Offset = 0x00500; |
---|
| 579 | break; |
---|
| 580 | case PPC_IRQ_ALIGNMENT: |
---|
| 581 | Offset = 0x00600; |
---|
| 582 | break; |
---|
| 583 | case PPC_IRQ_PROGRAM: |
---|
| 584 | Offset = 0x00700; |
---|
| 585 | break; |
---|
| 586 | case PPC_IRQ_NOFP: |
---|
| 587 | Offset = 0x00800; |
---|
| 588 | break; |
---|
| 589 | case PPC_IRQ_DECREMENTER: |
---|
| 590 | Offset = 0x00900; |
---|
| 591 | break; |
---|
| 592 | case PPC_IRQ_RESERVED_A: |
---|
| 593 | Offset = 0x00a00; |
---|
| 594 | break; |
---|
| 595 | case PPC_IRQ_RESERVED_B: |
---|
| 596 | Offset = 0x00b00; |
---|
| 597 | break; |
---|
| 598 | case PPC_IRQ_SCALL: |
---|
| 599 | Offset = 0x00c00; |
---|
| 600 | break; |
---|
| 601 | case PPC_IRQ_TRACE: |
---|
| 602 | Offset = 0x00d00; |
---|
| 603 | break; |
---|
| 604 | case PPC_IRQ_FP_ASST: |
---|
| 605 | Offset = 0x00e00; |
---|
| 606 | break; |
---|
| 607 | |
---|
| 608 | #if defined(ppc403) |
---|
| 609 | |
---|
| 610 | /* PPC_IRQ_CRIT is the same vector as PPC_IRQ_RESET |
---|
| 611 | case PPC_IRQ_CRIT: |
---|
| 612 | Offset = 0x00100; |
---|
| 613 | break; |
---|
| 614 | */ |
---|
| 615 | case PPC_IRQ_PIT: |
---|
| 616 | Offset = 0x01000; |
---|
| 617 | break; |
---|
| 618 | case PPC_IRQ_FIT: |
---|
| 619 | Offset = 0x01010; |
---|
| 620 | break; |
---|
| 621 | case PPC_IRQ_WATCHDOG: |
---|
| 622 | Offset = 0x01020; |
---|
| 623 | break; |
---|
| 624 | case PPC_IRQ_DEBUG: |
---|
| 625 | Offset = 0x02000; |
---|
| 626 | break; |
---|
| 627 | |
---|
| 628 | #elif defined(ppc601) |
---|
| 629 | case PPC_IRQ_TRACE: |
---|
| 630 | Offset = 0x02000; |
---|
| 631 | break; |
---|
| 632 | |
---|
| 633 | #elif defined(ppc603) |
---|
| 634 | case PPC_IRQ_TRANS_MISS: |
---|
| 635 | Offset = 0x1000; |
---|
| 636 | break; |
---|
| 637 | case PPC_IRQ_DATA_LOAD: |
---|
| 638 | Offset = 0x1100; |
---|
| 639 | break; |
---|
| 640 | case PPC_IRQ_DATA_STORE: |
---|
| 641 | Offset = 0x1200; |
---|
| 642 | break; |
---|
| 643 | case PPC_IRQ_ADDR_BRK: |
---|
| 644 | Offset = 0x1300; |
---|
| 645 | break; |
---|
| 646 | case PPC_IRQ_SYS_MGT: |
---|
| 647 | Offset = 0x1400; |
---|
| 648 | break; |
---|
| 649 | |
---|
| 650 | #elif defined(ppc603e) |
---|
| 651 | case PPC_TLB_INST_MISS: |
---|
| 652 | Offset = 0x1000; |
---|
| 653 | break; |
---|
| 654 | case PPC_TLB_LOAD_MISS: |
---|
| 655 | Offset = 0x1100; |
---|
| 656 | break; |
---|
| 657 | case PPC_TLB_STORE_MISS: |
---|
| 658 | Offset = 0x1200; |
---|
| 659 | break; |
---|
| 660 | case PPC_IRQ_ADDRBRK: |
---|
| 661 | Offset = 0x1300; |
---|
| 662 | break; |
---|
| 663 | case PPC_IRQ_SYS_MGT: |
---|
| 664 | Offset = 0x1400; |
---|
| 665 | break; |
---|
| 666 | |
---|
| 667 | #elif defined(mpc604) |
---|
| 668 | case PPC_IRQ_ADDR_BRK: |
---|
| 669 | Offset = 0x1300; |
---|
| 670 | break; |
---|
| 671 | case PPC_IRQ_SYS_MGT: |
---|
| 672 | Offset = 0x1400; |
---|
| 673 | break; |
---|
| 674 | |
---|
| 675 | #elif defined(mpc860) || defined(mpc821) |
---|
| 676 | case PPC_IRQ_EMULATE: |
---|
| 677 | Offset = 0x1000; |
---|
| 678 | break; |
---|
| 679 | case PPC_IRQ_INST_MISS: |
---|
| 680 | Offset = 0x1100; |
---|
| 681 | break; |
---|
| 682 | case PPC_IRQ_DATA_MISS: |
---|
| 683 | Offset = 0x1200; |
---|
| 684 | break; |
---|
| 685 | case PPC_IRQ_INST_ERR: |
---|
| 686 | Offset = 0x1300; |
---|
| 687 | break; |
---|
| 688 | case PPC_IRQ_DATA_ERR: |
---|
| 689 | Offset = 0x1400; |
---|
| 690 | break; |
---|
| 691 | case PPC_IRQ_DATA_BPNT: |
---|
| 692 | Offset = 0x1c00; |
---|
| 693 | break; |
---|
| 694 | case PPC_IRQ_INST_BPNT: |
---|
| 695 | Offset = 0x1d00; |
---|
| 696 | break; |
---|
| 697 | case PPC_IRQ_IO_BPNT: |
---|
| 698 | Offset = 0x1e00; |
---|
| 699 | break; |
---|
| 700 | case PPC_IRQ_DEV_PORT: |
---|
| 701 | Offset = 0x1f00; |
---|
| 702 | break; |
---|
| 703 | case PPC_IRQ_IRQ0: |
---|
| 704 | Offset = 0x2000; |
---|
| 705 | break; |
---|
| 706 | case PPC_IRQ_LVL0: |
---|
| 707 | Offset = 0x2040; |
---|
| 708 | break; |
---|
| 709 | case PPC_IRQ_IRQ1: |
---|
| 710 | Offset = 0x2080; |
---|
| 711 | break; |
---|
| 712 | case PPC_IRQ_LVL1: |
---|
| 713 | Offset = 0x20c0; |
---|
| 714 | break; |
---|
| 715 | case PPC_IRQ_IRQ2: |
---|
| 716 | Offset = 0x2100; |
---|
| 717 | break; |
---|
| 718 | case PPC_IRQ_LVL2: |
---|
| 719 | Offset = 0x2140; |
---|
| 720 | break; |
---|
| 721 | case PPC_IRQ_IRQ3: |
---|
| 722 | Offset = 0x2180; |
---|
| 723 | break; |
---|
| 724 | case PPC_IRQ_LVL3: |
---|
| 725 | Offset = 0x21c0; |
---|
| 726 | break; |
---|
| 727 | case PPC_IRQ_IRQ4: |
---|
| 728 | Offset = 0x2200; |
---|
| 729 | break; |
---|
| 730 | case PPC_IRQ_LVL4: |
---|
| 731 | Offset = 0x2240; |
---|
| 732 | break; |
---|
| 733 | case PPC_IRQ_IRQ5: |
---|
| 734 | Offset = 0x2280; |
---|
| 735 | break; |
---|
| 736 | case PPC_IRQ_LVL5: |
---|
| 737 | Offset = 0x22c0; |
---|
| 738 | break; |
---|
| 739 | case PPC_IRQ_IRQ6: |
---|
| 740 | Offset = 0x2300; |
---|
| 741 | break; |
---|
| 742 | case PPC_IRQ_LVL6: |
---|
| 743 | Offset = 0x2340; |
---|
| 744 | break; |
---|
| 745 | case PPC_IRQ_IRQ7: |
---|
| 746 | Offset = 0x2380; |
---|
| 747 | break; |
---|
| 748 | case PPC_IRQ_LVL7: |
---|
| 749 | Offset = 0x23c0; |
---|
| 750 | break; |
---|
| 751 | case PPC_IRQ_CPM_RESERVED_0: |
---|
| 752 | Offset = 0x2400; |
---|
| 753 | break; |
---|
| 754 | case PPC_IRQ_CPM_PC4: |
---|
| 755 | Offset = 0x2410; |
---|
| 756 | break; |
---|
| 757 | case PPC_IRQ_CPM_PC5: |
---|
| 758 | Offset = 0x2420; |
---|
| 759 | break; |
---|
| 760 | case PPC_IRQ_CPM_SMC2: |
---|
| 761 | Offset = 0x2430; |
---|
| 762 | break; |
---|
| 763 | case PPC_IRQ_CPM_SMC1: |
---|
| 764 | Offset = 0x2440; |
---|
| 765 | break; |
---|
| 766 | case PPC_IRQ_CPM_SPI: |
---|
| 767 | Offset = 0x2450; |
---|
| 768 | break; |
---|
| 769 | case PPC_IRQ_CPM_PC6: |
---|
| 770 | Offset = 0x2460; |
---|
| 771 | break; |
---|
| 772 | case PPC_IRQ_CPM_TIMER4: |
---|
| 773 | Offset = 0x2470; |
---|
| 774 | break; |
---|
| 775 | case PPC_IRQ_CPM_RESERVED_8: |
---|
| 776 | Offset = 0x2480; |
---|
| 777 | break; |
---|
| 778 | case PPC_IRQ_CPM_PC7: |
---|
| 779 | Offset = 0x2490; |
---|
| 780 | break; |
---|
| 781 | case PPC_IRQ_CPM_PC8: |
---|
| 782 | Offset = 0x24a0; |
---|
| 783 | break; |
---|
| 784 | case PPC_IRQ_CPM_PC9: |
---|
| 785 | Offset = 0x24b0; |
---|
| 786 | break; |
---|
| 787 | case PPC_IRQ_CPM_TIMER3: |
---|
| 788 | Offset = 0x24c0; |
---|
| 789 | break; |
---|
| 790 | case PPC_IRQ_CPM_RESERVED_D: |
---|
| 791 | Offset = 0x24d0; |
---|
| 792 | break; |
---|
| 793 | case PPC_IRQ_CPM_PC10: |
---|
| 794 | Offset = 0x24e0; |
---|
| 795 | break; |
---|
| 796 | case PPC_IRQ_CPM_PC11: |
---|
| 797 | Offset = 0x24f0; |
---|
| 798 | break; |
---|
| 799 | case PPC_IRQ_CPM_I2C: |
---|
| 800 | Offset = 0x2500; |
---|
| 801 | break; |
---|
| 802 | case PPC_IRQ_CPM_RISC_TIMER: |
---|
| 803 | Offset = 0x2510; |
---|
| 804 | break; |
---|
| 805 | case PPC_IRQ_CPM_TIMER2: |
---|
| 806 | Offset = 0x2520; |
---|
| 807 | break; |
---|
| 808 | case PPC_IRQ_CPM_RESERVED_13: |
---|
| 809 | Offset = 0x2530; |
---|
| 810 | break; |
---|
| 811 | case PPC_IRQ_CPM_IDMA2: |
---|
| 812 | Offset = 0x2540; |
---|
| 813 | break; |
---|
| 814 | case PPC_IRQ_CPM_IDMA1: |
---|
| 815 | Offset = 0x2550; |
---|
| 816 | break; |
---|
| 817 | case PPC_IRQ_CPM_SDMA_ERROR: |
---|
| 818 | Offset = 0x2560; |
---|
| 819 | break; |
---|
| 820 | case PPC_IRQ_CPM_PC12: |
---|
| 821 | Offset = 0x2570; |
---|
| 822 | break; |
---|
| 823 | case PPC_IRQ_CPM_PC13: |
---|
| 824 | Offset = 0x2580; |
---|
| 825 | break; |
---|
| 826 | case PPC_IRQ_CPM_TIMER1: |
---|
| 827 | Offset = 0x2590; |
---|
| 828 | break; |
---|
| 829 | case PPC_IRQ_CPM_PC14: |
---|
| 830 | Offset = 0x25a0; |
---|
| 831 | break; |
---|
| 832 | case PPC_IRQ_CPM_SCC4: |
---|
| 833 | Offset = 0x25b0; |
---|
| 834 | break; |
---|
| 835 | case PPC_IRQ_CPM_SCC3: |
---|
| 836 | Offset = 0x25c0; |
---|
| 837 | break; |
---|
| 838 | case PPC_IRQ_CPM_SCC2: |
---|
| 839 | Offset = 0x25d0; |
---|
| 840 | break; |
---|
| 841 | case PPC_IRQ_CPM_SCC1: |
---|
| 842 | Offset = 0x25e0; |
---|
| 843 | break; |
---|
| 844 | case PPC_IRQ_CPM_PC15: |
---|
| 845 | Offset = 0x25f0; |
---|
| 846 | break; |
---|
| 847 | #endif |
---|
| 848 | |
---|
| 849 | } |
---|
| 850 | Top += Offset; |
---|
| 851 | return Top; |
---|
| 852 | } |
---|
| 853 | |
---|