[acc25ee] | 1 | /* |
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| 2 | * PowerPC CPU Dependent Source |
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| 3 | * |
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| 4 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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| 5 | * |
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| 6 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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| 7 | * |
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| 8 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 9 | * without any express or implied warranty: |
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| 10 | * permission to use, copy, modify, and distribute this file |
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| 11 | * for any purpose is hereby granted without fee, provided that |
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| 12 | * the above copyright notice and this notice appears in all |
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| 13 | * copies, and that the name of i-cubed limited not be used in |
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| 14 | * advertising or publicity pertaining to distribution of the |
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| 15 | * software without specific, written prior permission. |
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| 16 | * i-cubed limited makes no representations about the suitability |
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| 17 | * of this software for any purpose. |
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| 18 | * |
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| 19 | * Derived from c/src/exec/cpu/no_cpu/cpu.c: |
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| 20 | * |
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| 21 | * COPYRIGHT (c) 1989-1997. |
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| 22 | * On-Line Applications Research Corporation (OAR). |
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| 23 | * |
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| 24 | * The license and distribution terms for this file may be found in |
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| 25 | * the file LICENSE in this distribution or at |
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[9563a3a] | 26 | * http://www.rtems.com/license/LICENSE. |
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[acc25ee] | 27 | * |
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| 28 | * $Id$ |
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| 29 | */ |
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| 30 | |
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| 31 | #include <rtems/system.h> |
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| 32 | #include <rtems/score/isr.h> |
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| 33 | #include <rtems/score/context.h> |
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| 34 | #include <rtems/score/thread.h> |
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| 35 | #include <rtems/score/interr.h> |
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| 36 | |
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[b97b2202] | 37 | #include <rtems/powerpc/cache.h> |
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| 38 | |
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[acc25ee] | 39 | /* |
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| 40 | * These are for testing purposes. |
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| 41 | */ |
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| 42 | |
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| 43 | /* _CPU_Initialize |
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| 44 | * |
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| 45 | * This routine performs processor dependent initialization. |
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| 46 | * |
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| 47 | * INPUT PARAMETERS: |
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| 48 | * cpu_table - CPU table to initialize |
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| 49 | * thread_dispatch - address of disptaching routine |
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| 50 | */ |
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| 51 | |
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| 52 | static void ppc_spurious(int, CPU_Interrupt_frame *); |
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| 53 | |
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[8ef3818] | 54 | int _CPU_spurious_count = 0; |
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| 55 | int _CPU_last_spurious = 0; |
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| 56 | |
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[acc25ee] | 57 | void _CPU_Initialize( |
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| 58 | rtems_cpu_table *cpu_table, |
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| 59 | void (*thread_dispatch) /* ignored on this CPU */ |
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| 60 | ) |
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| 61 | { |
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[aebde08e] | 62 | #if (PPC_USE_SPRG) |
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[acc25ee] | 63 | int i; |
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[aebde08e] | 64 | #endif |
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[acc25ee] | 65 | #if (PPC_ABI != PPC_ABI_POWEROPEN) |
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[ffe6331] | 66 | register uint32_t r2 = 0; |
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[acc25ee] | 67 | #if (PPC_ABI != PPC_ABI_GCC27) |
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[ffe6331] | 68 | register uint32_t r13 = 0; |
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[acc25ee] | 69 | |
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| 70 | asm ("mr %0,13" : "=r" ((r13)) : "0" ((r13))); |
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| 71 | _CPU_IRQ_info.Default_r13 = r13; |
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| 72 | #endif |
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| 73 | |
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| 74 | asm ("mr %0,2" : "=r" ((r2)) : "0" ((r2))); |
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| 75 | _CPU_IRQ_info.Default_r2 = r2; |
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| 76 | #endif |
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| 77 | |
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| 78 | _CPU_IRQ_info.Nest_level = &_ISR_Nest_level; |
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| 79 | _CPU_IRQ_info.Disable_level = &_Thread_Dispatch_disable_level; |
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[5e67b98] | 80 | /* fill in _CPU_IRQ_info.Vector_table later */ |
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[acc25ee] | 81 | #if (PPC_ABI == PPC_ABI_POWEROPEN) |
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[ffe6331] | 82 | _CPU_IRQ_info.Dispatch_r2 = ((uint32_t*)_Thread_Dispatch)[1]; |
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[acc25ee] | 83 | #endif |
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| 84 | _CPU_IRQ_info.Switch_necessary = &_Context_Switch_necessary; |
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| 85 | _CPU_IRQ_info.Signal = &_ISR_Signals_to_thread_executing; |
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| 86 | |
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| 87 | #if (PPC_USE_SPRG) |
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| 88 | i = (int)&_CPU_IRQ_info; |
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| 89 | asm volatile("mtspr 0x113, %0" : "=r" (i) : "0" (i)); /* SPRG 3 */ |
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| 90 | #endif |
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| 91 | |
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| 92 | /* |
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| 93 | * Store Msr Value in the IRQ info structure. |
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| 94 | */ |
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| 95 | _CPU_MSR_Value(_CPU_IRQ_info.msr_initial); |
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| 96 | |
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| 97 | #if (PPC_USE_SPRG) |
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| 98 | i = _CPU_IRQ_info.msr_initial; |
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| 99 | asm volatile("mtspr 0x112, %0" : "=r" (i) : "0" (i)); /* SPRG 2 */ |
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| 100 | #endif |
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| 101 | |
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[5e67b98] | 102 | _CPU_Table = *cpu_table; |
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| 103 | } |
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| 104 | |
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| 105 | /* |
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| 106 | * _CPU_Initialize_vectors() |
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| 107 | * |
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| 108 | * Support routine to initialize the RTEMS vector table after it is allocated. |
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| 109 | * |
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| 110 | * PowerPC Specific Information: |
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| 111 | * |
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| 112 | * Complete initialization since the table is now allocated. |
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| 113 | */ |
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| 114 | |
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| 115 | void _CPU_Initialize_vectors(void) |
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| 116 | { |
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| 117 | int i; |
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| 118 | proc_ptr handler = (proc_ptr)ppc_spurious; |
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| 119 | |
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| 120 | _CPU_IRQ_info.Vector_table = _ISR_Vector_table; |
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| 121 | |
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| 122 | if ( _CPU_Table.spurious_handler ) |
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| 123 | handler = (proc_ptr)_CPU_Table.spurious_handler; |
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[acc25ee] | 124 | |
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| 125 | for (i = 0; i < PPC_INTERRUPT_MAX; i++) |
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| 126 | _ISR_Vector_table[i] = handler; |
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| 127 | |
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| 128 | } |
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[5e67b98] | 129 | |
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[acc25ee] | 130 | /*PAGE |
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| 131 | * |
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| 132 | * _CPU_ISR_Calculate_level |
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| 133 | * |
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| 134 | * The PowerPC puts its interrupt enable status in the MSR register |
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| 135 | * which also contains things like endianness control. To be more |
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| 136 | * awkward, the layout varies from processor to processor. This |
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| 137 | * is why it was necessary to adopt a scheme which allowed the user |
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| 138 | * to specify specifically which interrupt sources were enabled. |
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| 139 | */ |
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| 140 | |
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[ffe6331] | 141 | uint32_t _CPU_ISR_Calculate_level( |
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| 142 | uint32_t new_level |
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[acc25ee] | 143 | ) |
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| 144 | { |
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[ffe6331] | 145 | register uint32_t new_msr = 0; |
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[acc25ee] | 146 | |
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| 147 | /* |
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| 148 | * Set the critical interrupt enable bit |
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| 149 | */ |
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| 150 | |
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| 151 | #if (PPC_HAS_RFCI) |
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| 152 | if ( !(new_level & PPC_INTERRUPT_LEVEL_CE) ) |
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| 153 | new_msr |= PPC_MSR_CE; |
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| 154 | #endif |
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| 155 | |
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| 156 | if ( !(new_level & PPC_INTERRUPT_LEVEL_ME) ) |
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| 157 | new_msr |= PPC_MSR_ME; |
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| 158 | |
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| 159 | if ( !(new_level & PPC_INTERRUPT_LEVEL_EE) ) |
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| 160 | new_msr |= PPC_MSR_EE; |
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| 161 | |
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| 162 | return new_msr; |
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| 163 | } |
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| 164 | |
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| 165 | /*PAGE |
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| 166 | * |
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| 167 | * _CPU_ISR_Set_level |
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| 168 | * |
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| 169 | * This routine sets the requested level in the MSR. |
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| 170 | */ |
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| 171 | |
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| 172 | void _CPU_ISR_Set_level( |
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[ffe6331] | 173 | uint32_t new_level |
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[acc25ee] | 174 | ) |
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| 175 | { |
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[ffe6331] | 176 | register uint32_t tmp = 0; |
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| 177 | register uint32_t new_msr; |
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[acc25ee] | 178 | |
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| 179 | new_msr = _CPU_ISR_Calculate_level( new_level ); |
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| 180 | |
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| 181 | asm volatile ( |
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| 182 | "mfmsr %0; andc %0,%0,%1; and %2, %2, %1; or %0, %0, %2; mtmsr %0" : |
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| 183 | "=&r" ((tmp)) : |
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| 184 | "r" ((PPC_MSR_DISABLE_MASK)), "r" ((new_msr)), "0" ((tmp)) |
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| 185 | ); |
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| 186 | } |
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| 187 | |
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| 188 | /*PAGE |
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| 189 | * |
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| 190 | * _CPU_ISR_Get_level |
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| 191 | * |
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| 192 | * This routine gets the current interrupt level from the MSR and |
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| 193 | * converts it to an RTEMS interrupt level. |
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| 194 | */ |
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| 195 | |
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[ffe6331] | 196 | uint32_t _CPU_ISR_Get_level( void ) |
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[acc25ee] | 197 | { |
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[ffe6331] | 198 | uint32_t level = 0; |
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| 199 | uint32_t msr; |
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[acc25ee] | 200 | |
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| 201 | asm volatile("mfmsr %0" : "=r" ((msr))); |
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| 202 | |
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| 203 | msr &= PPC_MSR_DISABLE_MASK; |
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| 204 | |
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| 205 | /* |
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| 206 | * Set the critical interrupt enable bit |
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| 207 | */ |
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| 208 | |
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| 209 | #if (PPC_HAS_RFCI) |
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| 210 | if ( !(msr & PPC_MSR_CE) ) |
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| 211 | level |= PPC_INTERRUPT_LEVEL_CE; |
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| 212 | #endif |
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| 213 | |
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| 214 | if ( !(msr & PPC_MSR_ME) ) |
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| 215 | level |= PPC_INTERRUPT_LEVEL_ME; |
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| 216 | |
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| 217 | if ( !(msr & PPC_MSR_EE) ) |
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| 218 | level |= PPC_INTERRUPT_LEVEL_EE; |
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| 219 | |
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| 220 | return level; |
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| 221 | } |
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| 222 | |
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| 223 | /*PAGE |
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| 224 | * |
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| 225 | * _CPU_Context_Initialize |
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| 226 | */ |
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| 227 | |
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| 228 | #if (PPC_ABI == PPC_ABI_POWEROPEN) |
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| 229 | #define CPU_MINIMUM_STACK_FRAME_SIZE 56 |
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| 230 | #else /* PPC_ABI_SVR4 or PPC_ABI_EABI */ |
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| 231 | #define CPU_MINIMUM_STACK_FRAME_SIZE 8 |
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| 232 | #endif |
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| 233 | |
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| 234 | void _CPU_Context_Initialize( |
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| 235 | Context_Control *the_context, |
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[ffe6331] | 236 | uint32_t *stack_base, |
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| 237 | uint32_t size, |
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| 238 | uint32_t new_level, |
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[acc25ee] | 239 | void *entry_point, |
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| 240 | boolean is_fp |
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| 241 | ) |
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| 242 | { |
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[ffe6331] | 243 | uint32_t msr_value; |
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| 244 | uint32_t sp; |
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[acc25ee] | 245 | |
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[ffe6331] | 246 | sp = (uint32_t)stack_base + size - CPU_MINIMUM_STACK_FRAME_SIZE; |
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| 247 | *((uint32_t*)sp) = 0; |
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[acc25ee] | 248 | the_context->gpr1 = sp; |
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| 249 | |
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| 250 | the_context->msr = _CPU_ISR_Calculate_level( new_level ); |
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| 251 | |
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| 252 | /* |
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| 253 | * The FP bit of the MSR should only be enabled if this is a floating |
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| 254 | * point task. Unfortunately, the vfprintf_r routine in newlib |
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| 255 | * ends up pushing a floating point register regardless of whether or |
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| 256 | * not a floating point number is being printed. Serious restructuring |
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| 257 | * of vfprintf.c will be required to avoid this behavior. At this |
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| 258 | * time (7 July 1997), this restructuring is not being done. |
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| 259 | */ |
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| 260 | |
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| 261 | /*if ( is_fp ) */ |
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| 262 | the_context->msr |= PPC_MSR_FP; |
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| 263 | |
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| 264 | /* |
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| 265 | * Calculate the task's MSR value: |
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| 266 | * |
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| 267 | * + Set the exception prefix bit to point to the exception table |
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| 268 | * + Force the RI bit |
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| 269 | * + Use the DR and IR bits |
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| 270 | */ |
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| 271 | _CPU_MSR_Value( msr_value ); |
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| 272 | the_context->msr |= (msr_value & PPC_MSR_EP); |
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| 273 | the_context->msr |= PPC_MSR_RI; |
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| 274 | the_context->msr |= msr_value & (PPC_MSR_DR|PPC_MSR_IR); |
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| 275 | |
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| 276 | #if (PPC_ABI == PPC_ABI_POWEROPEN) |
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[ffe6331] | 277 | { uint32_t *desc = (uint32_t*)entry_point; |
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[acc25ee] | 278 | |
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| 279 | the_context->pc = desc[0]; |
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| 280 | the_context->gpr2 = desc[1]; |
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| 281 | } |
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| 282 | #endif |
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| 283 | |
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| 284 | #if (PPC_ABI == PPC_ABI_SVR4) |
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| 285 | { unsigned r13 = 0; |
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| 286 | asm volatile ("mr %0, 13" : "=r" ((r13))); |
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| 287 | |
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[ffe6331] | 288 | the_context->pc = (uint32_t)entry_point; |
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[acc25ee] | 289 | the_context->gpr13 = r13; |
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| 290 | } |
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| 291 | #endif |
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| 292 | |
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| 293 | #if (PPC_ABI == PPC_ABI_EABI) |
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[ffe6331] | 294 | { uint32_t r2 = 0; |
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[acc25ee] | 295 | unsigned r13 = 0; |
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| 296 | asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13))); |
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| 297 | |
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[ffe6331] | 298 | the_context->pc = (uint32_t)entry_point; |
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[acc25ee] | 299 | the_context->gpr2 = r2; |
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| 300 | the_context->gpr13 = r13; |
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| 301 | } |
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| 302 | #endif |
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| 303 | } |
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| 304 | |
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| 305 | |
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| 306 | /* _CPU_ISR_install_vector |
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| 307 | * |
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| 308 | * This kernel routine installs the RTEMS handler for the |
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| 309 | * specified vector. |
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| 310 | * |
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| 311 | * Input parameters: |
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| 312 | * vector - interrupt vector number |
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| 313 | * old_handler - former ISR for this vector number |
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| 314 | * new_handler - replacement ISR for this vector number |
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| 315 | * |
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| 316 | * Output parameters: NONE |
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| 317 | * |
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| 318 | */ |
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| 319 | |
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| 320 | void _CPU_ISR_install_vector( |
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[ffe6331] | 321 | uint32_t vector, |
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[acc25ee] | 322 | proc_ptr new_handler, |
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| 323 | proc_ptr *old_handler |
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| 324 | ) |
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| 325 | { |
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| 326 | proc_ptr ignored; |
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| 327 | *old_handler = _ISR_Vector_table[ vector ]; |
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| 328 | |
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| 329 | /* |
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| 330 | * If the interrupt vector table is a table of pointer to isr entry |
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| 331 | * points, then we need to install the appropriate RTEMS interrupt |
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| 332 | * handler for this vector number. |
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| 333 | */ |
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| 334 | |
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| 335 | /* |
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| 336 | * Install the wrapper so this ISR can be invoked properly. |
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| 337 | */ |
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| 338 | if (_CPU_Table.exceptions_in_RAM) |
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| 339 | _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); |
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| 340 | |
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| 341 | /* |
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| 342 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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| 343 | * be used by the _ISR_Handler so the user gets control. |
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| 344 | */ |
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| 345 | |
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| 346 | _ISR_Vector_table[ vector ] = new_handler ? (ISR_Handler_entry)new_handler : |
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| 347 | _CPU_Table.spurious_handler ? |
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| 348 | (ISR_Handler_entry)_CPU_Table.spurious_handler : |
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| 349 | (ISR_Handler_entry)ppc_spurious; |
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| 350 | } |
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| 351 | |
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| 352 | /*PAGE |
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| 353 | * |
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| 354 | * _CPU_Install_interrupt_stack |
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| 355 | */ |
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| 356 | |
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| 357 | void _CPU_Install_interrupt_stack( void ) |
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| 358 | { |
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| 359 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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| 360 | _CPU_IRQ_info.Stack = _CPU_Interrupt_stack_high - 56; |
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| 361 | #else |
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| 362 | _CPU_IRQ_info.Stack = _CPU_Interrupt_stack_high - 8; |
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| 363 | #endif |
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| 364 | } |
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| 365 | |
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| 366 | /* Handle a spurious interrupt */ |
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| 367 | static void ppc_spurious(int v, CPU_Interrupt_frame *i) |
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| 368 | { |
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| 369 | #if 0 |
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| 370 | printf("Spurious interrupt on vector %d from %08.8x\n", |
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| 371 | v, i->pc); |
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| 372 | #endif |
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[e9ae97fb] | 373 | #if defined(ppc403) || defined(ppc405) |
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[acc25ee] | 374 | if (v == PPC_IRQ_EXTERNAL) |
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| 375 | { |
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| 376 | register int r = 0; |
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| 377 | |
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| 378 | asm volatile("mtdcr 0x42, %0" : |
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| 379 | "=&r" ((r)) : "0" ((r))); /* EXIER */ |
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| 380 | } |
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| 381 | else if (v == PPC_IRQ_PIT) |
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| 382 | { |
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| 383 | register int r = 0x08000000; |
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| 384 | |
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| 385 | asm volatile("mtspr 0x3d8, %0" : |
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| 386 | "=&r" ((r)) : "0" ((r))); /* TSR */ |
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| 387 | } |
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| 388 | else if (v == PPC_IRQ_FIT) |
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| 389 | { |
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| 390 | register int r = 0x04000000; |
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| 391 | |
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| 392 | asm volatile("mtspr 0x3d8, %0" : |
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| 393 | "=&r" ((r)) : "0" ((r))); /* TSR */ |
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| 394 | } |
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| 395 | #endif |
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[8ef3818] | 396 | ++_CPU_spurious_count; |
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| 397 | _CPU_last_spurious = v; |
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[acc25ee] | 398 | } |
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| 399 | |
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[ffe6331] | 400 | void _CPU_Fatal_error(uint32_t _error) |
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[acc25ee] | 401 | { |
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| 402 | asm volatile ("mr 3, %0" : : "r" ((_error))); |
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| 403 | asm volatile ("tweq 5,5"); |
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| 404 | asm volatile ("li 0,0; mtmsr 0"); |
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| 405 | while (1) ; |
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| 406 | } |
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| 407 | |
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| 408 | #define PPC_SYNCHRONOUS_TRAP_BIT_MASK 0x100 |
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| 409 | #define PPC_ASYNCHRONOUS_TRAP( _trap ) (_trap) |
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| 410 | #define PPC_SYNCHRONOUS_TRAP ( _trap ) ((_trap)+PPC_SYNCHRONOUS_TRAP_BIT_MASK) |
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| 411 | #define PPC_REAL_TRAP_NUMBER ( _trap ) ((_trap)%PPC_SYNCHRONOUS_TRAP_BIT_MASK) |
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| 412 | |
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| 413 | |
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| 414 | const CPU_Trap_table_entry _CPU_Trap_slot_template = { |
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| 415 | |
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| 416 | #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) |
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| 417 | #error " Vector install not tested." |
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| 418 | #if (PPC_HAS_FPU) |
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| 419 | #error " Vector install not tested." |
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| 420 | 0x9421feb0, /* stwu r1, -(20*4 + 18*8 + IP_END)(r1) */ |
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| 421 | #else |
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| 422 | #error " Vector install not tested." |
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| 423 | 0x9421ff40, /* stwu r1, -(20*4 + IP_END)(r1) */ |
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| 424 | #endif |
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| 425 | #else |
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| 426 | 0x9421ff90, /* stwu r1, -(IP_END)(r1) */ |
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| 427 | #endif |
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| 428 | |
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| 429 | 0x90010008, /* stw %r0, IP_0(%r1) */ |
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| 430 | 0x38000000, /* li %r0, PPC_IRQ */ |
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| 431 | 0x48000002 /* ba PROC (_ISR_Handler) */ |
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| 432 | }; |
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| 433 | |
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| 434 | #if defined(mpc860) || defined(mpc821) |
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| 435 | const CPU_Trap_table_entry _CPU_Trap_slot_template_m860 = { |
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| 436 | 0x7c0803ac, /* mtlr %r0 */ |
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| 437 | 0x81210028, /* lwz %r9, IP_9(%r1) */ |
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| 438 | 0x38000000, /* li %r0, PPC_IRQ */ |
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| 439 | 0x48000002 /* b PROC (_ISR_Handler) */ |
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| 440 | }; |
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| 441 | #endif /* mpc860 */ |
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| 442 | |
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[ffe6331] | 443 | uint32_t ppc_exception_vector_addr( |
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| 444 | uint32_t vector |
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[acc25ee] | 445 | ); |
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| 446 | |
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| 447 | |
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| 448 | /*PAGE |
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| 449 | * |
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| 450 | * _CPU_ISR_install_raw_handler |
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| 451 | * |
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| 452 | * This routine installs the specified handler as a "raw" non-executive |
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| 453 | * supported trap handler (a.k.a. interrupt service routine). |
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| 454 | * |
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| 455 | * Input Parameters: |
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| 456 | * vector - trap table entry number plus synchronous |
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| 457 | * vs. asynchronous information |
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| 458 | * new_handler - address of the handler to be installed |
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| 459 | * old_handler - pointer to an address of the handler previously installed |
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| 460 | * |
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| 461 | * Output Parameters: NONE |
---|
| 462 | * *new_handler - address of the handler previously installed |
---|
| 463 | * |
---|
| 464 | * NOTE: |
---|
| 465 | * |
---|
| 466 | * This routine is based on the SPARC routine _CPU_ISR_install_raw_handler. |
---|
| 467 | * Install a software trap handler as an executive interrupt handler |
---|
| 468 | * (which is desirable since RTEMS takes care of window and register issues), |
---|
| 469 | * then the executive needs to know that the return address is to the trap |
---|
| 470 | * rather than the instruction following the trap. |
---|
| 471 | * |
---|
| 472 | */ |
---|
| 473 | |
---|
| 474 | void _CPU_ISR_install_raw_handler( |
---|
[ffe6331] | 475 | uint32_t vector, |
---|
[acc25ee] | 476 | proc_ptr new_handler, |
---|
| 477 | proc_ptr *old_handler |
---|
| 478 | ) |
---|
| 479 | { |
---|
[ffe6331] | 480 | uint32_t real_vector; |
---|
[acc25ee] | 481 | CPU_Trap_table_entry *slot; |
---|
[ffe6331] | 482 | uint32_t u32_handler=0; |
---|
[acc25ee] | 483 | |
---|
| 484 | /* |
---|
| 485 | * Get the "real" trap number for this vector ignoring the synchronous |
---|
| 486 | * versus asynchronous indicator included with our vector numbers. |
---|
| 487 | */ |
---|
| 488 | |
---|
| 489 | real_vector = vector; |
---|
| 490 | |
---|
| 491 | /* |
---|
| 492 | * Get the current base address of the trap table and calculate a pointer |
---|
| 493 | * to the slot we are interested in. |
---|
| 494 | */ |
---|
| 495 | slot = (CPU_Trap_table_entry *)ppc_exception_vector_addr( real_vector ); |
---|
| 496 | |
---|
| 497 | /* |
---|
| 498 | * Get the address of the old_handler from the trap table. |
---|
| 499 | * |
---|
| 500 | * NOTE: The old_handler returned will be bogus if it does not follow |
---|
| 501 | * the RTEMS model. |
---|
| 502 | */ |
---|
| 503 | |
---|
| 504 | #define HIGH_BITS_MASK 0xFFFFFC00 |
---|
| 505 | #define HIGH_BITS_SHIFT 10 |
---|
| 506 | #define LOW_BITS_MASK 0x000003FF |
---|
| 507 | |
---|
| 508 | if (slot->stwu_r1 == _CPU_Trap_slot_template.stwu_r1) { |
---|
| 509 | /* |
---|
| 510 | * Set u32_handler = to target address |
---|
| 511 | */ |
---|
| 512 | u32_handler = slot->b_Handler & 0x03fffffc; |
---|
| 513 | |
---|
| 514 | /* IMD FIX: sign extend address fragment... */ |
---|
| 515 | if (u32_handler & 0x02000000) { |
---|
| 516 | u32_handler |= 0xfc000000; |
---|
| 517 | } |
---|
| 518 | |
---|
| 519 | *old_handler = (proc_ptr) u32_handler; |
---|
| 520 | } else |
---|
| 521 | /* There are two kinds of handlers for the MPC860. One is the 'standard' |
---|
| 522 | * one like above. The other is for the cascaded interrupts from the SIU |
---|
| 523 | * and CPM. Therefore we must check for the alternate one if the standard |
---|
| 524 | * one is not present |
---|
| 525 | */ |
---|
| 526 | #if defined(mpc860) || defined(mpc821) |
---|
| 527 | if (slot->stwu_r1 == _CPU_Trap_slot_template_m860.stwu_r1) { |
---|
| 528 | /* |
---|
| 529 | * Set u32_handler = to target address |
---|
| 530 | */ |
---|
| 531 | u32_handler = slot->b_Handler & 0x03fffffc; |
---|
| 532 | *old_handler = (proc_ptr) u32_handler; |
---|
| 533 | } else |
---|
| 534 | #endif /* mpc860 */ |
---|
| 535 | |
---|
| 536 | *old_handler = 0; |
---|
| 537 | |
---|
| 538 | /* |
---|
| 539 | * Copy the template to the slot and then fix it. |
---|
| 540 | */ |
---|
| 541 | #if defined(mpc860) || defined(mpc821) |
---|
| 542 | if (vector >= PPC_IRQ_IRQ0) |
---|
| 543 | *slot = _CPU_Trap_slot_template_m860; |
---|
| 544 | else |
---|
| 545 | #endif /* mpc860 */ |
---|
| 546 | *slot = _CPU_Trap_slot_template; |
---|
| 547 | |
---|
[ffe6331] | 548 | u32_handler = (uint32_t) new_handler; |
---|
[acc25ee] | 549 | |
---|
| 550 | /* |
---|
| 551 | * IMD FIX: insert address fragment only (bits 6..29) |
---|
| 552 | * therefore check for proper address range |
---|
| 553 | * and remove unwanted bits |
---|
| 554 | */ |
---|
| 555 | if ((u32_handler & 0xfc000000) == 0xfc000000) { |
---|
| 556 | u32_handler &= ~0xfc000000; |
---|
| 557 | } |
---|
| 558 | else if ((u32_handler & 0xfc000000) != 0x00000000) { |
---|
| 559 | _Internal_error_Occurred(INTERNAL_ERROR_CORE, |
---|
| 560 | TRUE, |
---|
| 561 | u32_handler); |
---|
| 562 | } |
---|
| 563 | |
---|
| 564 | slot->b_Handler |= u32_handler; |
---|
| 565 | |
---|
| 566 | slot->li_r0_IRQ |= vector; |
---|
| 567 | |
---|
| 568 | _CPU_Data_Cache_Block_Flush( slot ); |
---|
| 569 | } |
---|
| 570 | |
---|
[ffe6331] | 571 | uint32_t ppc_exception_vector_addr( |
---|
| 572 | uint32_t vector |
---|
[acc25ee] | 573 | ) |
---|
| 574 | { |
---|
| 575 | #if (!PPC_HAS_EVPR) |
---|
[ffe6331] | 576 | uint32_t Msr; |
---|
[acc25ee] | 577 | #endif |
---|
[ffe6331] | 578 | uint32_t Top = 0; |
---|
| 579 | uint32_t Offset = 0x000; |
---|
[acc25ee] | 580 | |
---|
| 581 | #if (PPC_HAS_EXCEPTION_PREFIX) |
---|
| 582 | _CPU_MSR_Value ( Msr ); |
---|
| 583 | if ( ( Msr & PPC_MSR_EP) != 0 ) /* Vectors at FFFx_xxxx */ |
---|
| 584 | Top = 0xfff00000; |
---|
| 585 | #elif (PPC_HAS_EVPR) |
---|
| 586 | asm volatile( "mfspr %0,0x3d6" : "=r" (Top)); /* EVPR */ |
---|
| 587 | Top = Top & 0xffff0000; |
---|
| 588 | #endif |
---|
| 589 | |
---|
| 590 | switch ( vector ) { |
---|
| 591 | case PPC_IRQ_SYSTEM_RESET: /* on 40x aka PPC_IRQ_CRIT */ |
---|
| 592 | Offset = 0x00100; |
---|
| 593 | break; |
---|
| 594 | case PPC_IRQ_MCHECK: |
---|
| 595 | Offset = 0x00200; |
---|
| 596 | break; |
---|
| 597 | case PPC_IRQ_PROTECT: |
---|
| 598 | Offset = 0x00300; |
---|
| 599 | break; |
---|
| 600 | case PPC_IRQ_ISI: |
---|
| 601 | Offset = 0x00400; |
---|
| 602 | break; |
---|
| 603 | case PPC_IRQ_EXTERNAL: |
---|
| 604 | Offset = 0x00500; |
---|
| 605 | break; |
---|
| 606 | case PPC_IRQ_ALIGNMENT: |
---|
| 607 | Offset = 0x00600; |
---|
| 608 | break; |
---|
| 609 | case PPC_IRQ_PROGRAM: |
---|
| 610 | Offset = 0x00700; |
---|
| 611 | break; |
---|
| 612 | case PPC_IRQ_NOFP: |
---|
| 613 | Offset = 0x00800; |
---|
| 614 | break; |
---|
| 615 | case PPC_IRQ_DECREMENTER: |
---|
| 616 | Offset = 0x00900; |
---|
| 617 | break; |
---|
| 618 | case PPC_IRQ_RESERVED_A: |
---|
| 619 | Offset = 0x00a00; |
---|
| 620 | break; |
---|
| 621 | case PPC_IRQ_RESERVED_B: |
---|
| 622 | Offset = 0x00b00; |
---|
| 623 | break; |
---|
| 624 | case PPC_IRQ_SCALL: |
---|
| 625 | Offset = 0x00c00; |
---|
| 626 | break; |
---|
| 627 | case PPC_IRQ_TRACE: |
---|
| 628 | Offset = 0x00d00; |
---|
| 629 | break; |
---|
| 630 | case PPC_IRQ_FP_ASST: |
---|
| 631 | Offset = 0x00e00; |
---|
| 632 | break; |
---|
| 633 | |
---|
[e9ae97fb] | 634 | #if defined(ppc403) || defined(ppc405) |
---|
[acc25ee] | 635 | |
---|
| 636 | /* PPC_IRQ_CRIT is the same vector as PPC_IRQ_RESET |
---|
| 637 | case PPC_IRQ_CRIT: |
---|
| 638 | Offset = 0x00100; |
---|
| 639 | break; |
---|
| 640 | */ |
---|
| 641 | case PPC_IRQ_PIT: |
---|
| 642 | Offset = 0x01000; |
---|
| 643 | break; |
---|
| 644 | case PPC_IRQ_FIT: |
---|
| 645 | Offset = 0x01010; |
---|
| 646 | break; |
---|
| 647 | case PPC_IRQ_WATCHDOG: |
---|
| 648 | Offset = 0x01020; |
---|
| 649 | break; |
---|
| 650 | case PPC_IRQ_DEBUG: |
---|
| 651 | Offset = 0x02000; |
---|
| 652 | break; |
---|
| 653 | |
---|
| 654 | #elif defined(ppc601) |
---|
| 655 | case PPC_IRQ_TRACE: |
---|
| 656 | Offset = 0x02000; |
---|
| 657 | break; |
---|
| 658 | |
---|
| 659 | #elif defined(ppc603) |
---|
| 660 | case PPC_IRQ_TRANS_MISS: |
---|
| 661 | Offset = 0x1000; |
---|
| 662 | break; |
---|
| 663 | case PPC_IRQ_DATA_LOAD: |
---|
| 664 | Offset = 0x1100; |
---|
| 665 | break; |
---|
| 666 | case PPC_IRQ_DATA_STORE: |
---|
| 667 | Offset = 0x1200; |
---|
| 668 | break; |
---|
| 669 | case PPC_IRQ_ADDR_BRK: |
---|
| 670 | Offset = 0x1300; |
---|
| 671 | break; |
---|
| 672 | case PPC_IRQ_SYS_MGT: |
---|
| 673 | Offset = 0x1400; |
---|
| 674 | break; |
---|
| 675 | |
---|
| 676 | #elif defined(ppc603e) |
---|
| 677 | case PPC_TLB_INST_MISS: |
---|
| 678 | Offset = 0x1000; |
---|
| 679 | break; |
---|
| 680 | case PPC_TLB_LOAD_MISS: |
---|
| 681 | Offset = 0x1100; |
---|
| 682 | break; |
---|
| 683 | case PPC_TLB_STORE_MISS: |
---|
| 684 | Offset = 0x1200; |
---|
| 685 | break; |
---|
| 686 | case PPC_IRQ_ADDRBRK: |
---|
| 687 | Offset = 0x1300; |
---|
| 688 | break; |
---|
| 689 | case PPC_IRQ_SYS_MGT: |
---|
| 690 | Offset = 0x1400; |
---|
| 691 | break; |
---|
| 692 | |
---|
| 693 | #elif defined(mpc604) |
---|
| 694 | case PPC_IRQ_ADDR_BRK: |
---|
| 695 | Offset = 0x1300; |
---|
| 696 | break; |
---|
| 697 | case PPC_IRQ_SYS_MGT: |
---|
| 698 | Offset = 0x1400; |
---|
| 699 | break; |
---|
| 700 | |
---|
| 701 | #elif defined(mpc860) || defined(mpc821) |
---|
| 702 | case PPC_IRQ_EMULATE: |
---|
| 703 | Offset = 0x1000; |
---|
| 704 | break; |
---|
| 705 | case PPC_IRQ_INST_MISS: |
---|
| 706 | Offset = 0x1100; |
---|
| 707 | break; |
---|
| 708 | case PPC_IRQ_DATA_MISS: |
---|
| 709 | Offset = 0x1200; |
---|
| 710 | break; |
---|
| 711 | case PPC_IRQ_INST_ERR: |
---|
| 712 | Offset = 0x1300; |
---|
| 713 | break; |
---|
| 714 | case PPC_IRQ_DATA_ERR: |
---|
| 715 | Offset = 0x1400; |
---|
| 716 | break; |
---|
| 717 | case PPC_IRQ_DATA_BPNT: |
---|
| 718 | Offset = 0x1c00; |
---|
| 719 | break; |
---|
| 720 | case PPC_IRQ_INST_BPNT: |
---|
| 721 | Offset = 0x1d00; |
---|
| 722 | break; |
---|
| 723 | case PPC_IRQ_IO_BPNT: |
---|
| 724 | Offset = 0x1e00; |
---|
| 725 | break; |
---|
| 726 | case PPC_IRQ_DEV_PORT: |
---|
| 727 | Offset = 0x1f00; |
---|
| 728 | break; |
---|
| 729 | case PPC_IRQ_IRQ0: |
---|
| 730 | Offset = 0x2000; |
---|
| 731 | break; |
---|
| 732 | case PPC_IRQ_LVL0: |
---|
| 733 | Offset = 0x2040; |
---|
| 734 | break; |
---|
| 735 | case PPC_IRQ_IRQ1: |
---|
| 736 | Offset = 0x2080; |
---|
| 737 | break; |
---|
| 738 | case PPC_IRQ_LVL1: |
---|
| 739 | Offset = 0x20c0; |
---|
| 740 | break; |
---|
| 741 | case PPC_IRQ_IRQ2: |
---|
| 742 | Offset = 0x2100; |
---|
| 743 | break; |
---|
| 744 | case PPC_IRQ_LVL2: |
---|
| 745 | Offset = 0x2140; |
---|
| 746 | break; |
---|
| 747 | case PPC_IRQ_IRQ3: |
---|
| 748 | Offset = 0x2180; |
---|
| 749 | break; |
---|
| 750 | case PPC_IRQ_LVL3: |
---|
| 751 | Offset = 0x21c0; |
---|
| 752 | break; |
---|
| 753 | case PPC_IRQ_IRQ4: |
---|
| 754 | Offset = 0x2200; |
---|
| 755 | break; |
---|
| 756 | case PPC_IRQ_LVL4: |
---|
| 757 | Offset = 0x2240; |
---|
| 758 | break; |
---|
| 759 | case PPC_IRQ_IRQ5: |
---|
| 760 | Offset = 0x2280; |
---|
| 761 | break; |
---|
| 762 | case PPC_IRQ_LVL5: |
---|
| 763 | Offset = 0x22c0; |
---|
| 764 | break; |
---|
| 765 | case PPC_IRQ_IRQ6: |
---|
| 766 | Offset = 0x2300; |
---|
| 767 | break; |
---|
| 768 | case PPC_IRQ_LVL6: |
---|
| 769 | Offset = 0x2340; |
---|
| 770 | break; |
---|
| 771 | case PPC_IRQ_IRQ7: |
---|
| 772 | Offset = 0x2380; |
---|
| 773 | break; |
---|
| 774 | case PPC_IRQ_LVL7: |
---|
| 775 | Offset = 0x23c0; |
---|
| 776 | break; |
---|
[8ef3818] | 777 | case PPC_IRQ_CPM_ERROR: |
---|
[acc25ee] | 778 | Offset = 0x2400; |
---|
| 779 | break; |
---|
| 780 | case PPC_IRQ_CPM_PC4: |
---|
| 781 | Offset = 0x2410; |
---|
| 782 | break; |
---|
| 783 | case PPC_IRQ_CPM_PC5: |
---|
| 784 | Offset = 0x2420; |
---|
| 785 | break; |
---|
| 786 | case PPC_IRQ_CPM_SMC2: |
---|
| 787 | Offset = 0x2430; |
---|
| 788 | break; |
---|
| 789 | case PPC_IRQ_CPM_SMC1: |
---|
| 790 | Offset = 0x2440; |
---|
| 791 | break; |
---|
| 792 | case PPC_IRQ_CPM_SPI: |
---|
| 793 | Offset = 0x2450; |
---|
| 794 | break; |
---|
| 795 | case PPC_IRQ_CPM_PC6: |
---|
| 796 | Offset = 0x2460; |
---|
| 797 | break; |
---|
| 798 | case PPC_IRQ_CPM_TIMER4: |
---|
| 799 | Offset = 0x2470; |
---|
| 800 | break; |
---|
| 801 | case PPC_IRQ_CPM_RESERVED_8: |
---|
| 802 | Offset = 0x2480; |
---|
| 803 | break; |
---|
| 804 | case PPC_IRQ_CPM_PC7: |
---|
| 805 | Offset = 0x2490; |
---|
| 806 | break; |
---|
| 807 | case PPC_IRQ_CPM_PC8: |
---|
| 808 | Offset = 0x24a0; |
---|
| 809 | break; |
---|
| 810 | case PPC_IRQ_CPM_PC9: |
---|
| 811 | Offset = 0x24b0; |
---|
| 812 | break; |
---|
| 813 | case PPC_IRQ_CPM_TIMER3: |
---|
| 814 | Offset = 0x24c0; |
---|
| 815 | break; |
---|
| 816 | case PPC_IRQ_CPM_RESERVED_D: |
---|
| 817 | Offset = 0x24d0; |
---|
| 818 | break; |
---|
| 819 | case PPC_IRQ_CPM_PC10: |
---|
| 820 | Offset = 0x24e0; |
---|
| 821 | break; |
---|
| 822 | case PPC_IRQ_CPM_PC11: |
---|
| 823 | Offset = 0x24f0; |
---|
| 824 | break; |
---|
| 825 | case PPC_IRQ_CPM_I2C: |
---|
| 826 | Offset = 0x2500; |
---|
| 827 | break; |
---|
| 828 | case PPC_IRQ_CPM_RISC_TIMER: |
---|
| 829 | Offset = 0x2510; |
---|
| 830 | break; |
---|
| 831 | case PPC_IRQ_CPM_TIMER2: |
---|
| 832 | Offset = 0x2520; |
---|
| 833 | break; |
---|
| 834 | case PPC_IRQ_CPM_RESERVED_13: |
---|
| 835 | Offset = 0x2530; |
---|
| 836 | break; |
---|
| 837 | case PPC_IRQ_CPM_IDMA2: |
---|
| 838 | Offset = 0x2540; |
---|
| 839 | break; |
---|
| 840 | case PPC_IRQ_CPM_IDMA1: |
---|
| 841 | Offset = 0x2550; |
---|
| 842 | break; |
---|
| 843 | case PPC_IRQ_CPM_SDMA_ERROR: |
---|
| 844 | Offset = 0x2560; |
---|
| 845 | break; |
---|
| 846 | case PPC_IRQ_CPM_PC12: |
---|
| 847 | Offset = 0x2570; |
---|
| 848 | break; |
---|
| 849 | case PPC_IRQ_CPM_PC13: |
---|
| 850 | Offset = 0x2580; |
---|
| 851 | break; |
---|
| 852 | case PPC_IRQ_CPM_TIMER1: |
---|
| 853 | Offset = 0x2590; |
---|
| 854 | break; |
---|
| 855 | case PPC_IRQ_CPM_PC14: |
---|
| 856 | Offset = 0x25a0; |
---|
| 857 | break; |
---|
| 858 | case PPC_IRQ_CPM_SCC4: |
---|
| 859 | Offset = 0x25b0; |
---|
| 860 | break; |
---|
| 861 | case PPC_IRQ_CPM_SCC3: |
---|
| 862 | Offset = 0x25c0; |
---|
| 863 | break; |
---|
| 864 | case PPC_IRQ_CPM_SCC2: |
---|
| 865 | Offset = 0x25d0; |
---|
| 866 | break; |
---|
| 867 | case PPC_IRQ_CPM_SCC1: |
---|
| 868 | Offset = 0x25e0; |
---|
| 869 | break; |
---|
| 870 | case PPC_IRQ_CPM_PC15: |
---|
| 871 | Offset = 0x25f0; |
---|
| 872 | break; |
---|
| 873 | #endif |
---|
| 874 | |
---|
| 875 | } |
---|
| 876 | Top += Offset; |
---|
| 877 | return Top; |
---|
| 878 | } |
---|
| 879 | |
---|
[75ad7376] | 880 | /*PAGE |
---|
| 881 | * |
---|
| 882 | * This is the PowerPC specific implementation of the routine which |
---|
| 883 | * returns TRUE if an interrupt is in progress. |
---|
| 884 | * |
---|
| 885 | * NOTE: This is the same as the generic version. But since the |
---|
| 886 | * PowerPC is still supporting old and new exception processing |
---|
| 887 | * models and the new exception processing model has a hardware |
---|
| 888 | * way of doing this, we have to provide this capability here |
---|
| 889 | * for symmetry. |
---|
| 890 | */ |
---|
| 891 | |
---|
| 892 | boolean _ISR_Is_in_progress( void ) |
---|
| 893 | { |
---|
| 894 | return (_ISR_Nest_level != 0); |
---|
| 895 | } |
---|