source: rtems/c/src/lib/libcpu/powerpc/new-exceptions/raw_exception.h @ ea39487

4.104.114.95
Last change on this file since ea39487 was ea39487, checked in by Till Straumann <strauman@…>, on 12/01/07 at 01:26:41

2007-11-30 Till Straumann <strauman@…>

  • new-exceptions/raw_exception.c, new-exceptions/raw_exception.h, old-exception/cpu.c: define bsp_exceptions_in_RAM variable. This is probably only used by the simulator (were else can you install something to ROM ??).
  • Property mode set to 100644
File size: 10.0 KB
Line 
1/*
2 * raw_execption.h
3 *
4 *          This file contains implementation of C function to
5 *          Instantiate 60x ppc primary exception entries.
6 *          More detailed information can be found on motorola
7 *          site and more precisely in the following book :
8 *
9 *              MPC750
10 *              Risc Microporcessor User's Manual
11 *              Mtorola REF : MPC750UM/AD 8/97
12 *
13 * Copyright (C) 1999  Eric Valette (valette@crf.canon.fr)
14 *                     Canon Centre Recherche France.
15 *
16 * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com>
17 * to support 603, 603e, 604, 604e exceptions
18 *
19 * moved to "libcpu/powerpc/new-exceptions and consolidated
20 * by Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
21 * to be common for all PPCs with new excpetions
22 *
23 *  The license and distribution terms for this file may be
24 *  found in found in the file LICENSE in this distribution or at
25 *  http://www.rtems.com/license/LICENSE.
26 *
27 * $Id$
28 */
29
30#ifndef _LIBCPU_RAW_EXCEPTION_H
31#define _LIBCPU_RAW_EXCEPTION_H
32
33#include <rtems/powerpc/powerpc.h>
34/*
35 * find out, whether we want to (re)enable the MMU in the assembly code
36 * FIXME: move this to a better location
37 */
38#if (defined(ppc403) || defined(ppc405))
39#define PPC_USE_MMU 0
40#else
41#define PPC_USE_MMU 1
42#endif
43
44/*
45 * Exception Vectors and offsets as defined in the MCP750 manual
46 * used by most PPCs
47 */
48
49#define ASM_RESET_VECTOR                0x01
50#define ASM_RESET_VECTOR_OFFSET         (ASM_RESET_VECTOR << 8)
51
52#define ASM_MACH_VECTOR                 0x02
53#define ASM_MACH_VECTOR_OFFSET          (ASM_MACH_VECTOR  << 8)
54
55#define ASM_PROT_VECTOR                 0x03
56#define ASM_PROT_VECTOR_OFFSET          (ASM_PROT_VECTOR  << 8)
57
58#define ASM_ISI_VECTOR                  0x04
59#define ASM_ISI_VECTOR_OFFSET           (ASM_ISI_VECTOR   << 8)
60
61#define ASM_EXT_VECTOR                  0x05
62#define ASM_EXT_VECTOR_OFFSET           (ASM_EXT_VECTOR   << 8)
63
64#define ASM_ALIGN_VECTOR                0x06
65#define ASM_ALIGN_VECTOR_OFFSET         (ASM_ALIGN_VECTOR << 8)
66
67#define ASM_PROG_VECTOR                 0x07
68#define ASM_PROG_VECTOR_OFFSET          (ASM_PROG_VECTOR  << 8)
69
70#define ASM_FLOAT_VECTOR                0x08
71#define ASM_FLOAT_VECTOR_OFFSET         (ASM_FLOAT_VECTOR << 8)
72
73#define ASM_DEC_VECTOR                  0x09
74#define ASM_DEC_VECTOR_OFFSET           (ASM_DEC_VECTOR   << 8)
75
76/* Bummer: Altivec unavailable doesn't fit into this scheme... (0xf20).
77 *    We'd like to avoid reserved vectors but OTOH we don't want to use
78 *    just an available high number because tables (and copies) are of
79 *    size LAST_VALID_EXC.
80 *    So until there is a CPU that uses 0xA we'll just use that :-(
81 */
82#define ASM_VEC_VECTOR                  0x0A
83#define ASM_VEC_VECTOR_OFFSET           (0xf20)
84
85#define ASM_SYS_VECTOR                  0x0C
86#define ASM_SYS_VECTOR_OFFSET           (ASM_SYS_VECTOR   << 8)
87
88#define ASM_TRACE_VECTOR                0x0D
89#define ASM_TRACE_VECTOR_OFFSET         (ASM_TRACE_VECTOR << 8)
90
91#if defined(ppc405)
92     /*
93      * vectors for PPC405
94      */
95#define ASM_CRIT_VECTOR                 ASM_RESET_VECTOR
96#define ASM_CRIT_VECTOR_OFFSET          (ASM_CRIT_VECTOR << 8) 
97
98#define ASM_PIT_VECTOR                  0x10
99#define ASM_PIT_VECTOR_OFFSET           (ASM_PIT_VECTOR      << 8)
100
101#define ASM_ITLBMISS_VECTOR             0x11
102#define ASM_ITLBMISS_VECTOR_OFFSET      (ASM_ITLBMISS_VECTOR << 8)
103
104#define ASM_DTLBMISS_VECTOR             0x12
105#define ASM_DTLBMISS_VECTOR_OFFSET      (ASM_DTLBMISS_VECTOR << 8)
106
107#define ASM_FIT_VECTOR                  0x13
108#define ASM_FIT_VECTOR_OFFSET           (0x1010)
109
110#define ASM_WDOG_VECTOR                 0x14
111#define ASM_WDOG_VECTOR_OFFSET          (0x1020)
112
113#define LAST_VALID_EXC                  ASM_WDOG_VECTOR
114
115/*
116 * bit mask of all exception vectors, that are handled
117 * as "critical" exsceptions (using SRR2/SRR3/rfci)
118 * this value will be evaluated in the default exception entry/exit
119 * code to determine, whether to use SRR0/SRR1/rfi or SRR2/SRR3/rfci
120 */
121#define ASM_VECTORS_CRITICAL                    \
122  (( 1 << (31-ASM_CRIT_VECTOR))                 \
123   |(1 << (31-ASM_MACH_VECTOR))                 \
124   |(1 << (31-ASM_WDOG_VECTOR)))
125
126#elif ( defined(mpc860) || defined(mpc821) )
127     /*
128      * vectors for MPC8xx
129      */
130
131/*
132 * FIXME: even more vector names might get used in common,
133 * but the names have diverged between different PPC families
134 */
135#define ASM_FLOATASSIST_VECTOR        0x0E
136#define ASM_FLOATASSIST_VECTOR_OFFSET (ASM_FLOATASSIST_VECTOR << 8)
137
138#define ASM_SOFTEMUL_VECTOR           0x10
139#define ASM_SOFTEMUL_VECTOR_OFFSET    (ASM_SOFTEMUL_VECTOR << 8)
140
141#define ASM_ITLBMISS_VECTOR           0x11
142#define ASM_ITLBMISS_VECTOR_OFFSET    (ASM_ITLBMISS_VECTOR << 8)
143
144#define ASM_DTLBMISS_VECTOR           0x12
145#define ASM_DTLBMISS_VECTOR_OFFSET    (ASM_DTLBMISS_VECTOR << 8)
146
147#define ASM_ITLBERROR_VECTOR          0x13
148#define ASM_ITLBERROR_VECTOR_OFFSET   (ASM_ITLBERROR_VECTOR << 8)
149
150#define ASM_DTLBERROR_VECTOR          0x14
151#define ASM_DTLBERROR_VECTOR_OFFSET   (ASM_DTLBERROR_VECTOR << 8)
152
153#define ASM_DBREAK_VECTOR             0x1C
154#define ASM_DBREAK_VECTOR_OFFSET      (ASM_DBREAK_VECTOR << 8)
155
156#define ASM_IBREAK_VECTOR             0x1D
157#define ASM_IBREAK_VECTOR_OFFSET      (ASM_IBREAK_VECTOR << 8)
158
159#define ASM_PERIFBREAK_VECTOR         0x1E
160#define ASM_PERIFBREAK_VECTOR_OFFSET  (ASM_PERIFBREAK_VECTOR << 8)
161
162#define ASM_DEVPORT_VECTOR            0x1F
163#define ASM_DEVPORT_VECTOR_OFFSET     (ASM_DEVPORT_VECTOR_OFFSET << 8)
164
165#define LAST_VALID_EXC          ASM_DEVPORT_VECTOR
166
167#elif (defined(mpc555) || defined(mpc505))
168     /*
169      * vectorx for MPC5xx
170      */
171#define ASM_FLOATASSIST_VECTOR  0x0E
172
173#define ASM_SOFTEMUL_VECTOR     0x10
174
175#define ASM_IPROT_VECTOR        0x13
176#define ASM_DPROT_VECTOR        0x14
177
178#define ASM_DBREAK_VECTOR       0x1C
179#define ASM_IBREAK_VECTOR       0x1D
180#define ASM_MEBREAK_VECTOR      0x1E
181#define ASM_NMEBREAK_VECTOR     0x1F
182
183#define LAST_VALID_EXC          ASM_NMEBREAK_VECTOR
184
185#else /* 60x style cpu types */
186#define PPC_HAS_60X_VECTORS
187
188#define ASM_PERFMON_VECTOR              0x0F
189#define ASM_PERFMON_VECTOR_OFFSET       (ASM_PERFMON_VECTOR << 8)
190
191#define ASM_IMISS_VECTOR                0x10
192
193#define ASM_DLMISS_VECTOR               0x11
194
195#define ASM_DSMISS_VECTOR               0x12
196
197#define ASM_ADDR_VECTOR                 0x13
198#define ASM_ADDR_VECTOR_OFFSET          (ASM_ADDR_VECTOR  << 8)
199
200#define ASM_SYSMGMT_VECTOR              0x14
201#define ASM_SYSMGMT_VECTOR_OFFSET       (ASM_SYSMGMT_VECTOR << 8)
202
203#define ASM_VEC_ASSIST_VECTOR           0x16
204#define ASM_VEC_ASSIST_VECTOR_OFFSET    (ASM_VEC_ASSIST_VECTOR << 8)
205
206#define ASM_ITM_VECTOR                  0x17
207#define ASM_ITM_VECTOR_OFFSET           (ASM_ITM_VECTOR   << 8)
208
209#define LAST_VALID_EXC                  ASM_ITM_VECTOR
210
211#endif
212
213     /*
214      * bits to be set in MSR in exception entry code
215      */
216#if                     ( PPC_HAS_RI) && ( PPC_USE_MMU)
217#define PPC_MSR_EXC_BITS (PPC_MSR_RI   | PPC_MSR_DR | PPC_MSR_IR)
218#elif                   ( PPC_HAS_RI) && (!PPC_USE_MMU)
219#define PPC_MSR_EXC_BITS (PPC_MSR_RI)
220#elif                   (!PPC_HAS_RI) && ( PPC_USE_MMU)
221#define PPC_MSR_EXC_BITS (               PPC_MSR_DR | PPC_MSR_IR)
222#else
223#endif
224
225
226
227#ifndef ASM
228
229/*
230 * Type definition for raw exceptions.
231 */
232
233typedef unsigned char  rtems_vector;
234struct  __rtems_raw_except_connect_data__;
235typedef void            (*rtems_raw_except_func)                (void);
236typedef unsigned long   rtems_raw_except_hdl_size;
237
238typedef struct {
239  rtems_vector                  vector;
240  rtems_raw_except_func         raw_hdl;
241  rtems_raw_except_hdl_size     raw_hdl_size;
242}rtems_raw_except_hdl;
243 
244typedef void (*rtems_raw_except_enable)         (const struct __rtems_raw_except_connect_data__*);
245typedef void (*rtems_raw_except_disable)        (const struct __rtems_raw_except_connect_data__*);
246typedef int  (*rtems_raw_except_is_enabled)     (const struct __rtems_raw_except_connect_data__*);
247
248typedef struct __rtems_raw_except_connect_data__{
249 /*
250  * Exception vector (As defined in the manual)
251  */
252  rtems_vector                  exceptIndex;
253  /*
254   * Exception raw handler. See comment on handler properties below in function prototype.
255   */
256  rtems_raw_except_hdl          hdl;
257  /*
258   * function for enabling raw exceptions. In order to be consistent
259   * with the fact that the raw connexion can defined in the
260   * libcpu library, this library should have no knowledge of
261   * board specific hardware to manage exceptions and thus the
262   * "on" routine must enable the except at processor level only.
263   *
264   */
265    rtems_raw_except_enable     on;     
266  /*
267   * function for disabling raw exceptions. In order to be consistent
268   * with the fact that the raw connexion can defined in the
269   * libcpu library, this library should have no knowledge of
270   * board specific hardware to manage exceptions and thus the
271   * "on" routine must disable the except both at device and PIC level.
272   *
273   */
274  rtems_raw_except_disable      off;
275  /*
276   * function enabling to know what exception may currently occur
277   */
278  rtems_raw_except_is_enabled   isOn;
279}rtems_raw_except_connect_data;
280
281typedef struct {
282  /*
283   * size of all the table fields (*Tbl) described below.
284   */
285  unsigned int                          exceptSize;
286  /*
287   * Default handler used when disconnecting exceptions.
288   */
289  rtems_raw_except_connect_data         defaultRawEntry;
290  /*
291   * Table containing initials/current value.
292   */
293  rtems_raw_except_connect_data*        rawExceptHdlTbl;
294}rtems_raw_except_global_settings;
295
296/*
297 * C callable function enabling to set up one raw idt entry
298 */
299extern int ppc_set_exception (const rtems_raw_except_connect_data*);
300
301/*
302 * C callable function enabling to get one current raw idt entry
303 */
304extern int ppc_get_current_exception (rtems_raw_except_connect_data*);
305
306/*
307 * C callable function enabling to remove one current raw idt entry
308 */
309extern int ppc_delete_exception (const rtems_raw_except_connect_data*);
310
311/*
312 * C callable function enabling to check if vector is valid
313 */
314extern int ppc_vector_is_valid(rtems_vector vector);
315
316/*
317 * Exception global init.
318 */
319extern int ppc_init_exceptions (rtems_raw_except_global_settings* config);
320extern int ppc_get_exception_config (rtems_raw_except_global_settings** config);
321
322/* This variable is initialized to 'TRUE' by default;
323 * BSPs which have their vectors in ROM should set it
324 * to FALSE prior to initializing raw exceptions.
325 *
326 * I suspect the only candidate is the simulator.
327 * After all, the value of this variable is used to
328 * determine where to install the prologue code and
329 * installing to ROM on anyting that's real ROM
330 * will fail anyways.
331 *
332 * This should probably go away... (T.S. 2007/11/30)
333 */
334extern boolean bsp_exceptions_in_RAM;
335
336# endif /* ASM */
337
338#endif
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