1 | /* |
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2 | * raw_execption.h |
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3 | * |
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4 | * This file contains implementation of C function to |
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5 | * Instantiate 60x ppc primary exception entries. |
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6 | * More detailed information can be found on motorola |
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7 | * site and more precisely in the following book : |
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8 | * |
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9 | * MPC750 |
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10 | * Risc Microporcessor User's Manual |
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11 | * Mtorola REF : MPC750UM/AD 8/97 |
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12 | * |
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13 | * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) |
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14 | * Canon Centre Recherche France. |
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15 | * |
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16 | * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com> |
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17 | * to support 603, 603e, 604, 604e exceptions |
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18 | * |
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19 | * moved to "libcpu/powerpc/new-exceptions and consolidated |
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20 | * by Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> |
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21 | * to be common for all PPCs with new excpetions |
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22 | * |
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23 | * The license and distribution terms for this file may be |
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24 | * found in found in the file LICENSE in this distribution or at |
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25 | * http://www.rtems.com/license/LICENSE. |
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26 | * |
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27 | * $Id$ |
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28 | */ |
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29 | |
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30 | #ifndef _LIBCPU_RAW_EXCEPTION_H |
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31 | #define _LIBCPU_RAW_EXCEPTION_H |
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32 | |
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33 | #include <rtems/powerpc/powerpc.h> |
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34 | /* |
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35 | * find out, whether we want to (re)enable the MMU in the assembly code |
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36 | * FIXME: move this to a better location |
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37 | */ |
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38 | #if (defined(ppc403) || defined(ppc405)) |
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39 | #define PPC_USE_MMU 0 |
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40 | #else |
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41 | #define PPC_USE_MMU 1 |
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42 | #endif |
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43 | |
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44 | /* |
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45 | * Exception Vectors and offsets as defined in the MCP750 manual |
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46 | * used by most PPCs |
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47 | */ |
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48 | |
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49 | #define ASM_RESET_VECTOR 0x01 |
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50 | #define ASM_RESET_VECTOR_OFFSET (ASM_RESET_VECTOR << 8) |
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51 | |
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52 | #define ASM_MACH_VECTOR 0x02 |
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53 | #define ASM_MACH_VECTOR_OFFSET (ASM_MACH_VECTOR << 8) |
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54 | |
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55 | #define ASM_PROT_VECTOR 0x03 |
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56 | #define ASM_PROT_VECTOR_OFFSET (ASM_PROT_VECTOR << 8) |
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57 | |
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58 | #define ASM_ISI_VECTOR 0x04 |
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59 | #define ASM_ISI_VECTOR_OFFSET (ASM_ISI_VECTOR << 8) |
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60 | |
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61 | #define ASM_EXT_VECTOR 0x05 |
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62 | #define ASM_EXT_VECTOR_OFFSET (ASM_EXT_VECTOR << 8) |
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63 | |
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64 | #define ASM_ALIGN_VECTOR 0x06 |
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65 | #define ASM_ALIGN_VECTOR_OFFSET (ASM_ALIGN_VECTOR << 8) |
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66 | |
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67 | #define ASM_PROG_VECTOR 0x07 |
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68 | #define ASM_PROG_VECTOR_OFFSET (ASM_PROG_VECTOR << 8) |
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69 | |
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70 | #define ASM_FLOAT_VECTOR 0x08 |
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71 | #define ASM_FLOAT_VECTOR_OFFSET (ASM_FLOAT_VECTOR << 8) |
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72 | |
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73 | #define ASM_DEC_VECTOR 0x09 |
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74 | #define ASM_DEC_VECTOR_OFFSET (ASM_DEC_VECTOR << 8) |
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75 | |
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76 | /* Bummer: Altivec unavailable doesn't fit into this scheme... (0xf20). |
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77 | * We'd like to avoid reserved vectors but OTOH we don't want to use |
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78 | * just an available high number because tables (and copies) are of |
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79 | * size LAST_VALID_EXC. |
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80 | * So until there is a CPU that uses 0xA we'll just use that :-( |
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81 | */ |
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82 | #define ASM_VEC_VECTOR 0x0A |
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83 | #define ASM_VEC_VECTOR_OFFSET (0xf20) |
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84 | |
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85 | #define ASM_SYS_VECTOR 0x0C |
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86 | #define ASM_SYS_VECTOR_OFFSET (ASM_SYS_VECTOR << 8) |
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87 | |
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88 | #define ASM_TRACE_VECTOR 0x0D |
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89 | #define ASM_TRACE_VECTOR_OFFSET (ASM_TRACE_VECTOR << 8) |
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90 | |
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91 | #if defined(ppc405) |
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92 | /* |
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93 | * vectors for PPC405 |
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94 | */ |
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95 | #define ASM_CRIT_VECTOR ASM_RESET_VECTOR |
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96 | #define ASM_CRIT_VECTOR_OFFSET (ASM_CRIT_VECTOR << 8) |
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97 | |
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98 | #define ASM_PIT_VECTOR 0x10 |
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99 | #define ASM_PIT_VECTOR_OFFSET (ASM_PIT_VECTOR << 8) |
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100 | |
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101 | #define ASM_ITLBMISS_VECTOR 0x11 |
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102 | #define ASM_ITLBMISS_VECTOR_OFFSET (ASM_ITLBMISS_VECTOR << 8) |
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103 | |
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104 | #define ASM_DTLBMISS_VECTOR 0x12 |
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105 | #define ASM_DTLBMISS_VECTOR_OFFSET (ASM_DTLBMISS_VECTOR << 8) |
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106 | |
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107 | #define ASM_FIT_VECTOR 0x13 |
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108 | #define ASM_FIT_VECTOR_OFFSET (0x1010) |
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109 | |
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110 | #define ASM_WDOG_VECTOR 0x14 |
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111 | #define ASM_WDOG_VECTOR_OFFSET (0x1020) |
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112 | |
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113 | #define LAST_VALID_EXC ASM_WDOG_VECTOR |
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114 | |
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115 | /* |
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116 | * bit mask of all exception vectors, that are handled |
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117 | * as "critical" exsceptions (using SRR2/SRR3/rfci) |
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118 | * this value will be evaluated in the default exception entry/exit |
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119 | * code to determine, whether to use SRR0/SRR1/rfi or SRR2/SRR3/rfci |
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120 | */ |
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121 | #define ASM_VECTORS_CRITICAL \ |
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122 | (( 1 << (31-ASM_CRIT_VECTOR)) \ |
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123 | |(1 << (31-ASM_MACH_VECTOR)) \ |
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124 | |(1 << (31-ASM_WDOG_VECTOR))) |
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125 | |
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126 | #elif ( defined(mpc860) || defined(mpc821) ) |
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127 | /* |
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128 | * vectors for MPC8xx |
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129 | */ |
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130 | |
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131 | /* |
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132 | * FIXME: even more vector names might get used in common, |
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133 | * but the names have diverged between different PPC families |
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134 | */ |
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135 | #define ASM_FLOATASSIST_VECTOR 0x0E |
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136 | #define ASM_FLOATASSIST_VECTOR_OFFSET (ASM_FLOATASSIST_VECTOR << 8) |
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137 | |
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138 | #define ASM_SOFTEMUL_VECTOR 0x10 |
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139 | #define ASM_SOFTEMUL_VECTOR_OFFSET (ASM_SOFTEMUL_VECTOR << 8) |
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140 | |
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141 | #define ASM_ITLBMISS_VECTOR 0x11 |
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142 | #define ASM_ITLBMISS_VECTOR_OFFSET (ASM_ITLBMISS_VECTOR << 8) |
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143 | |
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144 | #define ASM_DTLBMISS_VECTOR 0x12 |
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145 | #define ASM_DTLBMISS_VECTOR_OFFSET (ASM_DTLBMISS_VECTOR << 8) |
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146 | |
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147 | #define ASM_ITLBERROR_VECTOR 0x13 |
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148 | #define ASM_ITLBERROR_VECTOR_OFFSET (ASM_ITLBERROR_VECTOR << 8) |
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149 | |
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150 | #define ASM_DTLBERROR_VECTOR 0x14 |
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151 | #define ASM_DTLBERROR_VECTOR_OFFSET (ASM_DTLBERROR_VECTOR << 8) |
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152 | |
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153 | #define ASM_DBREAK_VECTOR 0x1C |
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154 | #define ASM_DBREAK_VECTOR_OFFSET (ASM_DBREAK_VECTOR << 8) |
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155 | |
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156 | #define ASM_IBREAK_VECTOR 0x1D |
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157 | #define ASM_IBREAK_VECTOR_OFFSET (ASM_IBREAK_VECTOR << 8) |
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158 | |
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159 | #define ASM_PERIFBREAK_VECTOR 0x1E |
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160 | #define ASM_PERIFBREAK_VECTOR_OFFSET (ASM_PERIFBREAK_VECTOR << 8) |
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161 | |
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162 | #define ASM_DEVPORT_VECTOR 0x1F |
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163 | #define ASM_DEVPORT_VECTOR_OFFSET (ASM_DEVPORT_VECTOR_OFFSET << 8) |
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164 | |
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165 | #define LAST_VALID_EXC ASM_DEVPORT_VECTOR |
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166 | |
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167 | #elif (defined(mpc555) || defined(mpc505)) |
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168 | /* |
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169 | * vectorx for MPC5xx |
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170 | */ |
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171 | #define ASM_FLOATASSIST_VECTOR 0x0E |
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172 | |
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173 | #define ASM_SOFTEMUL_VECTOR 0x10 |
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174 | |
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175 | #define ASM_IPROT_VECTOR 0x13 |
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176 | #define ASM_DPROT_VECTOR 0x14 |
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177 | |
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178 | #define ASM_DBREAK_VECTOR 0x1C |
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179 | #define ASM_IBREAK_VECTOR 0x1D |
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180 | #define ASM_MEBREAK_VECTOR 0x1E |
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181 | #define ASM_NMEBREAK_VECTOR 0x1F |
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182 | |
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183 | #define LAST_VALID_EXC ASM_NMEBREAK_VECTOR |
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184 | |
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185 | #else /* 60x style cpu types */ |
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186 | #define PPC_HAS_60X_VECTORS |
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187 | |
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188 | #define ASM_PERFMON_VECTOR 0x0F |
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189 | #define ASM_PERFMON_VECTOR_OFFSET (ASM_PERFMON_VECTOR << 8) |
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190 | |
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191 | #define ASM_IMISS_VECTOR 0x10 |
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192 | |
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193 | #define ASM_DLMISS_VECTOR 0x11 |
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194 | |
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195 | #define ASM_DSMISS_VECTOR 0x12 |
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196 | |
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197 | #define ASM_ADDR_VECTOR 0x13 |
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198 | #define ASM_ADDR_VECTOR_OFFSET (ASM_ADDR_VECTOR << 8) |
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199 | |
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200 | #define ASM_SYSMGMT_VECTOR 0x14 |
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201 | #define ASM_SYSMGMT_VECTOR_OFFSET (ASM_SYSMGMT_VECTOR << 8) |
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202 | |
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203 | #define ASM_VEC_ASSIST_VECTOR 0x16 |
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204 | #define ASM_VEC_ASSIST_VECTOR_OFFSET (ASM_VEC_ASSIST_VECTOR << 8) |
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205 | |
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206 | #define ASM_ITM_VECTOR 0x17 |
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207 | #define ASM_ITM_VECTOR_OFFSET (ASM_ITM_VECTOR << 8) |
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208 | |
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209 | #define LAST_VALID_EXC ASM_ITM_VECTOR |
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210 | |
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211 | #endif |
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212 | |
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213 | /* |
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214 | * bits to be set in MSR in exception entry code |
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215 | */ |
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216 | #if ( PPC_HAS_RI) && ( PPC_USE_MMU) |
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217 | #define PPC_MSR_EXC_BITS (PPC_MSR_RI | PPC_MSR_DR | PPC_MSR_IR) |
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218 | #elif ( PPC_HAS_RI) && (!PPC_USE_MMU) |
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219 | #define PPC_MSR_EXC_BITS (PPC_MSR_RI) |
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220 | #elif (!PPC_HAS_RI) && ( PPC_USE_MMU) |
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221 | #define PPC_MSR_EXC_BITS ( PPC_MSR_DR | PPC_MSR_IR) |
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222 | #else |
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223 | #endif |
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224 | |
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225 | |
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226 | |
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227 | #ifndef ASM |
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228 | |
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229 | /* |
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230 | * Type definition for raw exceptions. |
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231 | */ |
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232 | |
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233 | typedef unsigned char rtems_vector; |
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234 | struct __rtems_raw_except_connect_data__; |
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235 | typedef void (*rtems_raw_except_func) (void); |
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236 | typedef unsigned long rtems_raw_except_hdl_size; |
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237 | |
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238 | typedef struct { |
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239 | rtems_vector vector; |
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240 | rtems_raw_except_func raw_hdl; |
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241 | rtems_raw_except_hdl_size raw_hdl_size; |
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242 | }rtems_raw_except_hdl; |
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243 | |
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244 | typedef void (*rtems_raw_except_enable) (const struct __rtems_raw_except_connect_data__*); |
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245 | typedef void (*rtems_raw_except_disable) (const struct __rtems_raw_except_connect_data__*); |
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246 | typedef int (*rtems_raw_except_is_enabled) (const struct __rtems_raw_except_connect_data__*); |
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247 | |
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248 | typedef struct __rtems_raw_except_connect_data__{ |
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249 | /* |
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250 | * Exception vector (As defined in the manual) |
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251 | */ |
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252 | rtems_vector exceptIndex; |
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253 | /* |
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254 | * Exception raw handler. See comment on handler properties below in function prototype. |
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255 | */ |
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256 | rtems_raw_except_hdl hdl; |
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257 | /* |
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258 | * function for enabling raw exceptions. In order to be consistent |
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259 | * with the fact that the raw connexion can defined in the |
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260 | * libcpu library, this library should have no knowledge of |
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261 | * board specific hardware to manage exceptions and thus the |
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262 | * "on" routine must enable the except at processor level only. |
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263 | * |
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264 | */ |
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265 | rtems_raw_except_enable on; |
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266 | /* |
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267 | * function for disabling raw exceptions. In order to be consistent |
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268 | * with the fact that the raw connexion can defined in the |
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269 | * libcpu library, this library should have no knowledge of |
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270 | * board specific hardware to manage exceptions and thus the |
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271 | * "on" routine must disable the except both at device and PIC level. |
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272 | * |
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273 | */ |
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274 | rtems_raw_except_disable off; |
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275 | /* |
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276 | * function enabling to know what exception may currently occur |
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277 | */ |
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278 | rtems_raw_except_is_enabled isOn; |
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279 | }rtems_raw_except_connect_data; |
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280 | |
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281 | typedef struct { |
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282 | /* |
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283 | * size of all the table fields (*Tbl) described below. |
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284 | */ |
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285 | unsigned int exceptSize; |
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286 | /* |
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287 | * Default handler used when disconnecting exceptions. |
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288 | */ |
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289 | rtems_raw_except_connect_data defaultRawEntry; |
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290 | /* |
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291 | * Table containing initials/current value. |
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292 | */ |
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293 | rtems_raw_except_connect_data* rawExceptHdlTbl; |
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294 | }rtems_raw_except_global_settings; |
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295 | |
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296 | /* |
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297 | * C callable function enabling to set up one raw idt entry |
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298 | */ |
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299 | extern int ppc_set_exception (const rtems_raw_except_connect_data*); |
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300 | |
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301 | /* |
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302 | * C callable function enabling to get one current raw idt entry |
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303 | */ |
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304 | extern int ppc_get_current_exception (rtems_raw_except_connect_data*); |
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305 | |
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306 | /* |
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307 | * C callable function enabling to remove one current raw idt entry |
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308 | */ |
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309 | extern int ppc_delete_exception (const rtems_raw_except_connect_data*); |
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310 | |
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311 | /* |
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312 | * C callable function enabling to check if vector is valid |
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313 | */ |
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314 | extern int ppc_vector_is_valid(rtems_vector vector); |
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315 | |
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316 | /* |
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317 | * Exception global init. |
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318 | */ |
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319 | extern int ppc_init_exceptions (rtems_raw_except_global_settings* config); |
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320 | extern int ppc_get_exception_config (rtems_raw_except_global_settings** config); |
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321 | |
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322 | /* This variable is initialized to 'TRUE' by default; |
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323 | * BSPs which have their vectors in ROM should set it |
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324 | * to FALSE prior to initializing raw exceptions. |
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325 | * |
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326 | * I suspect the only candidate is the simulator. |
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327 | * After all, the value of this variable is used to |
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328 | * determine where to install the prologue code and |
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329 | * installing to ROM on anyting that's real ROM |
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330 | * will fail anyways. |
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331 | * |
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332 | * This should probably go away... (T.S. 2007/11/30) |
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333 | */ |
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334 | extern boolean bsp_exceptions_in_RAM; |
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335 | |
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336 | # endif /* ASM */ |
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337 | |
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338 | #endif |
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